656 lines
22 KiB
C
656 lines
22 KiB
C
/*
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* Copyright (c) 2002-2004 M. Warner Losh.
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* Copyright (c) 2000-2001 Jonathan Chen.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1998, 1999 and 2000
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* HAYAKAWA Koichi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by HAYAKAWA Koichi.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for PCI to CardBus Bridge chips
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*
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* References:
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* TI Datasheets:
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* http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
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*
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* Written by Jonathan Chen <jon@freebsd.org>
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* The author would like to acknowledge:
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* * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
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* * Warner Losh: Newbus/newcard guru and author of the pccard side of things
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* * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
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* * David Cross: Author of the initial ugly hack for a specific cardbus card
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/condvar.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <sys/kthread.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <sys/module.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/clock.h>
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#include <dev/pccard/pccardreg.h>
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#include <dev/pccard/pccardvar.h>
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#include <dev/exca/excareg.h>
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#include <dev/exca/excavar.h>
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#include <dev/pccbb/pccbbreg.h>
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#include <dev/pccbb/pccbbvar.h>
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#include "power_if.h"
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#include "card_if.h"
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#include "pcib_if.h"
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#define DPRINTF(x) do { if (cbb_debug) printf x; } while (0)
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#define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
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#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
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pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
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#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
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pci_write_config(DEV, REG, ( \
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pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
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static void cbb_chipinit(struct cbb_softc *sc);
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static struct yenta_chipinfo {
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uint32_t yc_id;
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const char *yc_name;
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int yc_chiptype;
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} yc_chipsets[] = {
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/* Texas Instruments chips */
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{PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
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{PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
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{PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
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{PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
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{PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
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{PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
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{PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
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{PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
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{PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
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/* ENE */
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{PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
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/* Ricoh chips */
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{PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
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{PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
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{PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
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{PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
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{PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
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{PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
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/* Toshiba products */
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{PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
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{PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
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{PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
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{PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
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/* Cirrus Logic */
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{PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
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/* 02Micro */
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{PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
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/* sentinel */
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{0 /* null id */, "unknown", CB_UNKNOWN},
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};
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/************************************************************************/
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/* Probe/Attach */
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/************************************************************************/
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static int
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cbb_chipset(uint32_t pci_id, const char **namep)
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{
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struct yenta_chipinfo *ycp;
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for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
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continue;
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if (namep != NULL)
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*namep = ycp->yc_name;
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return (ycp->yc_chiptype);
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}
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static int
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cbb_pci_probe(device_t brdev)
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{
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const char *name;
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uint32_t progif;
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uint32_t subclass;
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/*
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* Do we know that we support the chipset? If so, then we
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* accept the device.
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*/
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if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
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device_set_desc(brdev, name);
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return (0);
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}
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/*
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* We do support generic CardBus bridges. All that we've seen
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* to date have progif 0 (the Yenta spec, and successors mandate
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* this). We do not support PCI PCMCIA bridges (with one exception)
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* with this driver since they generally are I/O mapped. Those
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* are supported by the pcic driver. This should help us be more
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* future proof.
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*/
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subclass = pci_get_subclass(brdev);
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progif = pci_get_progif(brdev);
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if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) {
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device_set_desc(brdev, "PCI-CardBus Bridge");
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return (0);
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}
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return (ENXIO);
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}
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#ifndef BURN_BRIDGES
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/*
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* Still need this because the pci code only does power for type 0
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* header devices.
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*/
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static void
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cbb_powerstate_d0(device_t dev)
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{
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u_int32_t membase, irq;
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if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
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/* Save important PCI config data. */
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membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
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irq = pci_read_config(dev, PCIR_INTLINE, 4);
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/* Reset the power state. */
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device_printf(dev, "chip is in D%d power mode "
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"-- setting to D0\n", pci_get_powerstate(dev));
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pci_set_powerstate(dev, PCI_POWERSTATE_D0);
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/* Restore PCI config data. */
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pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
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pci_write_config(dev, PCIR_INTLINE, irq, 4);
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}
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}
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#endif
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/*
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* Print out the config space
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*/
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static void
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cbb_print_config(device_t dev)
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{
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int i;
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device_printf(dev, "PCI Configuration space:");
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for (i = 0; i < 256; i += 4) {
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if (i % 16 == 0)
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printf("\n 0x%02x: ", i);
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printf("0x%08x ", pci_read_config(dev, i, 4));
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}
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printf("\n");
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}
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static int
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cbb_pci_attach(device_t brdev)
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{
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static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
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struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
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int rid, bus, pribus;
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device_t parent;
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parent = device_get_parent(brdev);
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mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
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cv_init(&sc->cv, "cbb cv");
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sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
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sc->dev = brdev;
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sc->cbdev = NULL;
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sc->exca[0].pccarddev = NULL;
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sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
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sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
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SLIST_INIT(&sc->rl);
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STAILQ_INIT(&sc->intr_handlers);
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#ifndef BURN_BRIDGES
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cbb_powerstate_d0(brdev);
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#endif
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rid = CBBR_SOCKBASE;
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sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->base_res) {
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device_printf(brdev, "Could not map register memory\n");
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mtx_destroy(&sc->mtx);
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cv_destroy(&sc->cv);
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return (ENOMEM);
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} else {
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DEVPRINTF((brdev, "Found memory at %08lx\n",
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rman_get_start(sc->base_res)));
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}
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sc->bst = rman_get_bustag(sc->base_res);
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sc->bsh = rman_get_bushandle(sc->base_res);
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exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
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sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
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sc->exca[0].chipset = EXCA_CARDBUS;
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sc->chipinit = cbb_chipinit;
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sc->chipinit(sc);
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/*
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* This is a gross hack. We should be scanning the entire pci
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* tree, assigning bus numbers in a way such that we (1) can
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* reserve 1 extra bus just in case and (2) all sub busses
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* are in an appropriate range.
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*/
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bus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
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pribus = pcib_get_bus(parent);
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DEVPRINTF((brdev, "Secondary bus is %d\n", bus));
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if (bus == 0) {
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if (curr_bus_number <= pribus)
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curr_bus_number = pribus + 1;
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if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) {
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DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus));
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pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1);
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}
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bus = curr_bus_number;
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DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus,
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bus + 1));
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sc->secbus = bus;
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sc->subbus = bus + 1;
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pci_write_config(brdev, PCIR_SECBUS_2, bus, 1);
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pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1);
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curr_bus_number += 2;
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}
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/* attach children */
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sc->cbdev = device_add_child(brdev, "cardbus", -1);
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if (sc->cbdev == NULL)
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DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
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else if (device_probe_and_attach(sc->cbdev) != 0)
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DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
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sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
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if (sc->exca[0].pccarddev == NULL)
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DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
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else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
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DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
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/* Map and establish the interrupt. */
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->irq_res == NULL) {
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printf("cbb: Unable to map IRQ...\n");
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goto err;
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}
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if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
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cbb_intr, sc, &sc->intrhand)) {
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device_printf(brdev, "couldn't establish interrupt");
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goto err;
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}
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/* reset 16-bit pcmcia bus */
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exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
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/* turn off power */
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cbb_power(brdev, CARD_OFF);
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/* CSC Interrupt: Card detect interrupt on */
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cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
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/* reset interrupt */
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cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
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if (bootverbose)
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cbb_print_config(brdev);
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/* Start the thread */
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if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
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"%s", device_get_nameunit(brdev))) {
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device_printf(brdev, "unable to create event thread.\n");
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panic("cbb_create_event_thread");
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}
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return (0);
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err:
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if (sc->irq_res)
|
|
bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
|
|
if (sc->base_res) {
|
|
bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
|
|
sc->base_res);
|
|
}
|
|
mtx_destroy(&sc->mtx);
|
|
cv_destroy(&sc->cv);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
static void
|
|
cbb_chipinit(struct cbb_softc *sc)
|
|
{
|
|
uint32_t mux, sysctrl, reg;
|
|
|
|
/* Set CardBus latency timer */
|
|
if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
|
|
pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1);
|
|
|
|
/* Set PCI latency timer */
|
|
if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
|
|
pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
|
|
|
|
/* Enable memory access */
|
|
PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
|
|
| PCIM_CMD_MEMEN
|
|
| PCIM_CMD_PORTEN
|
|
| PCIM_CMD_BUSMASTEREN, 2);
|
|
|
|
/* disable Legacy IO */
|
|
switch (sc->chipset) {
|
|
case CB_RF5C46X:
|
|
PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
|
|
& ~(CBBM_BRIDGECTRL_RL_3E0_EN |
|
|
CBBM_BRIDGECTRL_RL_3E2_EN), 2);
|
|
break;
|
|
default:
|
|
pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
|
|
break;
|
|
}
|
|
|
|
/* Use PCI interrupt for interrupt routing */
|
|
PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
|
|
& ~(CBBM_BRIDGECTRL_MASTER_ABORT |
|
|
CBBM_BRIDGECTRL_INTR_IREQ_EN),
|
|
| CBBM_BRIDGECTRL_WRITE_POST_EN,
|
|
2);
|
|
|
|
/*
|
|
* XXX this should be a function table, ala OLDCARD. This means
|
|
* that we could more easily support ISA interrupts for pccard
|
|
* cards if we had to.
|
|
*/
|
|
switch (sc->chipset) {
|
|
case CB_TI113X:
|
|
/*
|
|
* The TI 1031, TI 1130 and TI 1131 all require another bit
|
|
* be set to enable PCI routing of interrupts, and then
|
|
* a bit for each of the CSC and Function interrupts we
|
|
* want routed.
|
|
*/
|
|
PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
|
|
| CBBM_CBCTRL_113X_PCI_INTR |
|
|
CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
|
|
1);
|
|
PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
|
|
& ~(CBBM_DEVCTRL_INT_SERIAL |
|
|
CBBM_DEVCTRL_INT_PCI), 1);
|
|
break;
|
|
case CB_TI12XX:
|
|
/*
|
|
* Some TI 12xx (and [14][45]xx) based pci cards
|
|
* sometimes have issues with the MFUNC register not
|
|
* being initialized due to a bad EEPROM on board.
|
|
* Laptops that this matters on have this register
|
|
* properly initialized.
|
|
*
|
|
* The TI125X parts have a different register.
|
|
*/
|
|
mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
|
|
sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
|
|
if (mux == 0) {
|
|
mux = (mux & ~CBBM_MFUNC_PIN0) |
|
|
CBBM_MFUNC_PIN0_INTA;
|
|
if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
|
|
mux = (mux & ~CBBM_MFUNC_PIN1) |
|
|
CBBM_MFUNC_PIN1_INTB;
|
|
pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
|
|
}
|
|
/*FALLTHROUGH*/
|
|
case CB_TI125X:
|
|
/*
|
|
* Disable zoom video. Some machines initialize this
|
|
* improperly and exerpience has shown that this helps
|
|
* prevent strange behavior.
|
|
*/
|
|
pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
|
|
break;
|
|
case CB_O2MICRO:
|
|
/*
|
|
* Issue #1: INT# generated at the same time as
|
|
* selected ISA IRQ. When IREQ# or STSCHG# is active,
|
|
* in addition to the ISA IRQ being generated, INT#
|
|
* will also be generated at the same time.
|
|
*
|
|
* Some of the older controllers have an issue in
|
|
* which the slot's PCI INT# will be asserted whenever
|
|
* IREQ# or STSCGH# is asserted even if ExCA registers
|
|
* 03h or 05h have an ISA IRQ selected.
|
|
*
|
|
* The fix for this issue, which will work for any
|
|
* controller (old or new), is to set ExCA registers
|
|
* 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
|
|
* These bits are undocumented. By setting this
|
|
* register (of each slot) to '1010xxxxb' a routing of
|
|
* IREQ# to INTC# and STSCHG# to INTC# is selected.
|
|
* Since INTC# isn't connected there will be no
|
|
* unexpected PCI INT when IREQ# or STSCHG# is active.
|
|
* However, INTA# (slot 0) or INTB# (slot 1) will
|
|
* still be correctly generated if NO ISA IRQ is
|
|
* selected (ExCA regs 03h or 05h are cleared).
|
|
*/
|
|
reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);
|
|
reg = (reg & 0x0f) |
|
|
EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
|
|
exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);
|
|
|
|
break;
|
|
case CB_TOPIC97:
|
|
/*
|
|
* Disable Zoom Video, ToPIC 97, 100.
|
|
*/
|
|
pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1);
|
|
/*
|
|
* ToPIC 97, 100
|
|
* At offset 0xa1: INTERRUPT CONTROL register
|
|
* 0x1: Turn on INT interrupts.
|
|
*/
|
|
PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL,
|
|
| CBBM_TOPIC_INTCTRL_INTIRQSEL, 1);
|
|
goto topic_common;
|
|
case CB_TOPIC95:
|
|
/*
|
|
* SOCKETCTRL appears to be TOPIC 95/B specific
|
|
*/
|
|
PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL,
|
|
| CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4);
|
|
|
|
topic_common:;
|
|
/*
|
|
* At offset 0xa0: SLOT CONTROL
|
|
* 0x80 Enable CardBus Functionality
|
|
* 0x40 Enable CardBus and PC Card registers
|
|
* 0x20 Lock ID in exca regs
|
|
* 0x10 Write protect ID in config regs
|
|
* Clear the rest of the bits, which defaults the slot
|
|
* in legacy mode to 0x3e0 and offset 0. (legacy
|
|
* mode is determined elsewhere)
|
|
*/
|
|
pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL,
|
|
CBBM_TOPIC_SLOTCTRL_SLOTON |
|
|
CBBM_TOPIC_SLOTCTRL_SLOTEN |
|
|
CBBM_TOPIC_SLOTCTRL_ID_LOCK |
|
|
CBBM_TOPIC_SLOTCTRL_ID_WP, 1);
|
|
|
|
/*
|
|
* At offset 0xa3 Card Detect Control Register
|
|
* 0x80 CARDBUS enbale
|
|
* 0x01 Cleared for hardware change detect
|
|
*/
|
|
PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC,
|
|
| CBBM_TOPIC_CDC_CARDBUS,
|
|
& ~CBBM_TOPIC_CDC_SWDETECT, 4);
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Need to tell ExCA registers to CSC interrupts route via PCI
|
|
* interrupts. There are two ways to do this. Once is to set
|
|
* INTR_ENABLE and the other is to set CSC to 0. Since both
|
|
* methods are mutually compatible, we do both.
|
|
*/
|
|
exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE);
|
|
exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0);
|
|
|
|
cbb_disable_func_intr(sc);
|
|
|
|
/* close all memory and io windows */
|
|
pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
|
|
pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
|
|
pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
|
|
pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
|
|
pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
|
|
pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
|
|
pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
|
|
pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
|
|
}
|
|
|
|
static device_method_t cbb_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, cbb_pci_probe),
|
|
DEVMETHOD(device_attach, cbb_pci_attach),
|
|
DEVMETHOD(device_detach, cbb_detach),
|
|
DEVMETHOD(device_shutdown, cbb_shutdown),
|
|
DEVMETHOD(device_suspend, cbb_suspend),
|
|
DEVMETHOD(device_resume, cbb_resume),
|
|
|
|
/* bus methods */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, cbb_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, cbb_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, cbb_release_resource),
|
|
DEVMETHOD(bus_activate_resource, cbb_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
|
|
DEVMETHOD(bus_driver_added, cbb_driver_added),
|
|
DEVMETHOD(bus_child_detached, cbb_child_detached),
|
|
DEVMETHOD(bus_setup_intr, cbb_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
|
|
DEVMETHOD(bus_child_present, cbb_child_present),
|
|
|
|
/* 16-bit card interface */
|
|
DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
|
|
DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
|
|
|
|
/* power interface */
|
|
DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
|
|
DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
|
|
|
|
/* pcib compatibility interface */
|
|
DEVMETHOD(pcib_maxslots, cbb_maxslots),
|
|
DEVMETHOD(pcib_read_config, cbb_read_config),
|
|
DEVMETHOD(pcib_write_config, cbb_write_config),
|
|
{0,0}
|
|
};
|
|
|
|
static driver_t cbb_driver = {
|
|
"cbb",
|
|
cbb_methods,
|
|
sizeof(struct cbb_softc)
|
|
};
|
|
|
|
DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0);
|
|
MODULE_DEPEND(cbb, exca, 1, 1, 1);
|