49b49cda41
Files required for the NIC driver Import from vendor-sys/alpine-hal/2.7 SVN rev.: 294828 HAL version: 2.7 Obtained from: Semihalf Sponsored by: Annapurna Labs
496 lines
15 KiB
C
496 lines
15 KiB
C
/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @{
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* @file al_hal_serdes_regs.h
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*
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* @brief ... registers
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*
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*/
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#ifndef __AL_HAL_SERDES_REGS_H__
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#define __AL_HAL_SERDES_REGS_H__
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#include "al_hal_plat_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Unit Registers
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*/
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struct serdes_gen {
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/* [0x0] SerDes Registers Version */
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uint32_t version;
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uint32_t rsrvd_0[3];
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/* [0x10] SerDes register file address */
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uint32_t reg_addr;
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/* [0x14] SerDes register file data */
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uint32_t reg_data;
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uint32_t rsrvd_1[2];
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/* [0x20] SerDes control */
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uint32_t ictl_multi_bist;
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/* [0x24] SerDes control */
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uint32_t ictl_pcs;
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/* [0x28] SerDes control */
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uint32_t ictl_pma;
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uint32_t rsrvd_2;
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/* [0x30] SerDes control */
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uint32_t ipd_multi_synth;
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/* [0x34] SerDes control */
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uint32_t irst;
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/* [0x38] SerDes control */
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uint32_t octl_multi_synthready;
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/* [0x3c] SerDes control */
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uint32_t octl_multi_synthstatus;
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/* [0x40] SerDes control */
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uint32_t clk_out;
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uint32_t rsrvd[47];
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};
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struct serdes_lane {
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uint32_t rsrvd1[4];
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/* [0x10] SerDes status */
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uint32_t octl_pma;
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/* [0x14] SerDes control */
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uint32_t ictl_multi_andme;
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/* [0x18] SerDes control */
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uint32_t ictl_multi_lb;
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/* [0x1c] SerDes control */
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uint32_t ictl_multi_rxbist;
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/* [0x20] SerDes control */
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uint32_t ictl_multi_txbist;
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/* [0x24] SerDes control */
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uint32_t ictl_multi;
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/* [0x28] SerDes control */
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uint32_t ictl_multi_rxeq;
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/* [0x2c] SerDes control */
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uint32_t ictl_multi_rxeq_l_low;
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/* [0x30] SerDes control */
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uint32_t ictl_multi_rxeq_l_high;
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/* [0x34] SerDes control */
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uint32_t ictl_multi_rxeyediag;
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/* [0x38] SerDes control */
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uint32_t ictl_multi_txdeemph;
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/* [0x3c] SerDes control */
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uint32_t ictl_multi_txmargin;
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/* [0x40] SerDes control */
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uint32_t ictl_multi_txswing;
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/* [0x44] SerDes control */
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uint32_t idat_multi;
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/* [0x48] SerDes control */
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uint32_t ipd_multi;
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/* [0x4c] SerDes control */
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uint32_t octl_multi_rxbist;
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/* [0x50] SerDes control */
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uint32_t octl_multi;
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/* [0x54] SerDes control */
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uint32_t octl_multi_rxeyediag;
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/* [0x58] SerDes control */
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uint32_t odat_multi_rxbist;
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/* [0x5c] SerDes control */
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uint32_t odat_multi_rxeq;
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/* [0x60] SerDes control */
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uint32_t multi_rx_dvalid;
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/* [0x64] SerDes control */
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uint32_t reserved;
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uint32_t rsrvd[6];
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};
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struct al_serdes_regs {
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uint32_t rsrvd_0[64];
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struct serdes_gen gen; /* [0x100] */
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struct serdes_lane lane[4]; /* [0x200] */
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};
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/*
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* Registers Fields
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*/
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/**** version register ****/
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/* Revision number (Minor) */
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#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
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#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
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/* Revision number (Major) */
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#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
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#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
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/* Date of release */
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#define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000
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#define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16
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/* Month of release */
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#define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
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#define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21
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/* Year of release (starting from 2000) */
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#define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
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#define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25
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/* Reserved */
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#define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000
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#define SERDES_GEN_VERSION_RESERVED_SHIFT 30
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/**** reg_addr register ****/
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/* Address value */
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#define SERDES_GEN_REG_ADDR_VAL_MASK 0x0000FFFF
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#define SERDES_GEN_REG_ADDR_VAL_SHIFT 0
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/**** reg_data register ****/
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/* Data value */
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#define SERDES_GEN_REG_DATA_VAL_MASK 0x000000FF
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#define SERDES_GEN_REG_DATA_VAL_SHIFT 0
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/**** ICTL_MULTI_BIST register ****/
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#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007
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#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0
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/**** ICTL_PCS register ****/
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#define SERDES_GEN_ICTL_PCS_EN_NT (1 << 0)
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/**** ICTL_PMA register ****/
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#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007
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#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0
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#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \
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(0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \
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(3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \
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(4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070
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#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4
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#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \
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(0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \
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(2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \
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(3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700
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#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8
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#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \
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(0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \
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(2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \
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(3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
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#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC (1 << 11)
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#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS (0 << 11)
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#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER (1 << 11)
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#define SERDES_GEN_ICTL_PMA_TXENABLE_A (1 << 12)
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#define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13)
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/**** IPD_MULTI_SYNTH register ****/
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#define SERDES_GEN_IPD_MULTI_SYNTH_B (1 << 0)
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/**** IRST register ****/
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#define SERDES_GEN_IRST_PIPE_RST_L3_B_A (1 << 0)
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#define SERDES_GEN_IRST_PIPE_RST_L2_B_A (1 << 1)
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#define SERDES_GEN_IRST_PIPE_RST_L1_B_A (1 << 2)
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#define SERDES_GEN_IRST_PIPE_RST_L0_B_A (1 << 3)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7)
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#define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8)
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#define SERDES_GEN_IRST_POR_B_A (1 << 12)
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#define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16)
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#define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17)
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#define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18)
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#define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22)
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#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23)
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/**** OCTL_MULTI_SYNTHREADY register ****/
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#define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0)
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/**** OCTL_MULTI_SYNTHSTATUS register ****/
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#define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0)
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/**** clk_out register ****/
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#define SERDES_GEN_CLK_OUT_SEL_MASK 0x0000003F
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#define SERDES_GEN_CLK_OUT_SEL_SHIFT 0
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/**** OCTL_PMA register ****/
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#define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0)
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/**** ICTL_MULTI_ANDME register ****/
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#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0)
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#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1)
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/**** ICTL_MULTI_LB register ****/
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#define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0)
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#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1)
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#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2)
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#define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3)
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#define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4)
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#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8)
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#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9)
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/**** ICTL_MULTI_RXBIST register ****/
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#define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0)
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/**** ICTL_MULTI_TXBIST register ****/
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#define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0)
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/**** ICTL_MULTI register ****/
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#define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003
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#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0
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#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2)
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#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070
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#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4
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#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8)
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#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9)
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#define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12)
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#define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13)
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#define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000
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#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16
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#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19)
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#define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000
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#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20
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#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23)
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#define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000
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#define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24
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#define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27)
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#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000
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#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28
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/**** ICTL_MULTI_RXEQ register ****/
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#define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0)
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#define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1)
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#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070
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#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4
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/**** ICTL_MULTI_RXEQ_L_high register ****/
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#define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0)
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/**** ICTL_MULTI_RXEYEDIAG register ****/
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#define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0)
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/**** ICTL_MULTI_TXDEEMPH register ****/
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK 0x7c0
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT 6
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK 0xf000
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT 12
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK 0x7
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#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT 0
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/**** ICTL_MULTI_TXMARGIN register ****/
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#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007
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#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0
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/**** ICTL_MULTI_TXSWING register ****/
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#define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0)
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/**** IDAT_MULTI register ****/
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#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F
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#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0
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#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4)
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/**** IPD_MULTI register ****/
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#define SERDES_LANE_IPD_MULTI_TX_L_B (1 << 0)
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#define SERDES_LANE_IPD_MULTI_RX_L_B (1 << 1)
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/**** OCTL_MULTI_RXBIST register ****/
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#define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0)
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#define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1)
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/**** OCTL_MULTI register ****/
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#define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0)
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#define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1)
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#define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2)
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#define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3)
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#define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4)
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#define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5)
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#define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6)
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#define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7)
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/**** OCTL_MULTI_RXEYEDIAG register ****/
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#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF
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#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0
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#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16)
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#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17)
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/**** ODAT_MULTI_RXBIST register ****/
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#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF
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#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0
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#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16)
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/**** ODAT_MULTI_RXEQ register ****/
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#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF
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#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0
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/**** MULTI_RX_DVALID register ****/
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#define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0)
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#define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1)
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#define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2)
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#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3)
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#define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4)
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#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5)
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#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000
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#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16
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#define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30)
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#define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31)
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/**** reserved register ****/
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#define SERDES_LANE_RESERVED_OUT_MASK 0x000000FF
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#define SERDES_LANE_RESERVED_OUT_SHIFT 0
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#define SERDES_LANE_RESERVED_IN_MASK 0x00FF0000
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#define SERDES_LANE_RESERVED_IN_SHIFT 16
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AL_HAL_serdes_REGS_H__ */
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/** @} end of ... group */
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