14c32b5f40
o don't strip the Ethernet header from inbound packets; pass packets up the stack intact (required significant changes to some drivers) o reference common definitions in net/ethernet.h (e.g. ETHER_ALIGN) o track ether_ifattach/ether_ifdetach API changes o track bpf changes (use BPF_TAP and BPF_MTAP) o track vlan changes (ifnet capabilities, revised processing scheme, etc.) o use if_input to pass packets "up" o call ether_ioctl for default handling of ioctls Reviewed by: many Approved by: re
169 lines
5.3 KiB
C
169 lines
5.3 KiB
C
/*-
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* Copyright (c) 1999,2000,2001 Jonathan Lemon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#if __FreeBSD_version < 500000
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#define GX_LOCK(gx)
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#define GX_UNLOCK(gx)
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#define mtx_init(a, b, c, d)
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#define mtx_destroy(a)
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struct mtx { int filler; };
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#else
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#define GX_LOCK(gx) mtx_lock(&(gx)->gx_mtx)
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#define GX_UNLOCK(gx) mtx_unlock(&(gx)->gx_mtx)
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#endif
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#ifdef __alpha__
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#undef vtophys
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#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
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#endif
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#ifndef PCIM_CMD_MWIEN
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#define PCIM_CMD_MWIEN 0x0010
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#endif
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/* CSR_WRITE_8 assumes the register is in low/high order */
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#define CSR_WRITE_8(gx, reg, val) do { \
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bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \
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reg, (val) & 0xffffffff); \
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bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \
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(reg) + 4, (val) >> 32); \
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} while (0)
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#define CSR_WRITE_4(gx, reg, val) \
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bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
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#define CSR_WRITE_2(gx, reg, val) \
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bus_space_write_2((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
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#define CSR_WRITE_1(gx, reg, val) \
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bus_space_write_1((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
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#define CSR_READ_4(gx, reg) \
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bus_space_read_4((gx)->gx_btag, (gx)->gx_bhandle, reg)
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#define CSR_READ_2(gx, reg) \
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bus_space_read_2((gx)->gx_btag, (gx)->gx_bhandle, reg)
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#define CSR_READ_1(gx, reg) \
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bus_space_read_1((gx)->gx_btag, (gx)->gx_bhandle, reg)
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#define GX_SETBIT(gx, reg, x) \
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CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) | (x)))
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#define GX_CLRBIT(gx, reg, x) \
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CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) & ~(x)))
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/*
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* In theory, these can go up to 64K each, but due to chip bugs,
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* they are limited to 256 max. Descriptor counts should be a
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* multiple of 8.
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*/
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#define GX_TX_RING_CNT 256
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#define GX_RX_RING_CNT 256
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#define GX_INC(x, y) (x) = (x + 1) % y
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#define GX_PREV(x, y) (x == 0 ? y - 1 : x - 1)
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#define GX_MAX_MTU (16 * 1024)
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struct gx_ring_data {
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struct gx_rx_desc gx_rx_ring[GX_RX_RING_CNT];
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struct gx_tx_desc gx_tx_ring[GX_TX_RING_CNT];
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};
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struct gx_chain_data {
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struct mbuf *gx_rx_chain[GX_RX_RING_CNT];
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struct mbuf *gx_tx_chain[GX_TX_RING_CNT];
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};
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struct gx_regs {
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int r_rx_base;
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int r_rx_length;
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int r_rx_head;
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int r_rx_tail;
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int r_rx_delay;
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int r_rx_dma_ctrl;
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int r_tx_base;
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int r_tx_length;
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int r_tx_head;
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int r_tx_tail;
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int r_tx_delay;
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int r_tx_dma_ctrl;
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};
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struct gx_softc {
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struct arpcom arpcom; /* interface info */
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struct ifmedia gx_media; /* media info */
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bus_space_handle_t gx_bhandle; /* bus space handle */
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bus_space_tag_t gx_btag; /* bus space tag */
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void *gx_intrhand; /* irq handler handle */
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struct resource *gx_irq; /* IRQ resource handle */
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struct resource *gx_res; /* I/O or shared mem handle */
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device_t gx_dev;
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device_t gx_miibus;
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u_int8_t gx_unit; /* controller number */
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u_int8_t gx_tbimode; /* transceiver flag */
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int gx_vflags; /* version-specific flags */
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u_int32_t gx_ipg; /* version-specific IPG */
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struct gx_ring_data *gx_rdata;
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struct gx_chain_data gx_cdata;
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int gx_if_flags;
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struct mbuf *gx_pkthdr;
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struct mbuf **gx_pktnextp;
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int gx_rx_tail_idx; /* receive ring tail index */
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int gx_tx_tail_idx; /* transmit ring tail index */
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int gx_tx_head_idx; /* transmit ring tail index */
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int gx_txcnt;
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int gx_txcontext; /* current TX context */
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struct gx_regs gx_reg;
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struct mtx gx_mtx;
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/* tunables */
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int gx_tx_intr_delay;
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int gx_rx_intr_delay;
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/* statistics */
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int gx_tx_interrupts;
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int gx_rx_interrupts;
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int gx_interrupts;
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};
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/*
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* flags to compensate for differing chip variants
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*/
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#define GXF_FORCE_TBI 0x0001 /* force TBI mode on */
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#define GXF_DMA 0x0002 /* has DMA control registers */
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#define GXF_ENABLE_MWI 0x0004 /* supports MWI burst mode */
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#define GXF_OLD_REGS 0x0008 /* use old register mapping */
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#define GXF_CSUM 0x0010 /* hardware checksum offload */
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/*
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* TX Context definitions.
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*/
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#define GX_TXCONTEXT_NONE 0
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#define GX_TXCONTEXT_TCPIP 1
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#define GX_TXCONTEXT_UDPIP 2
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