112 lines
3.4 KiB
C
112 lines
3.4 KiB
C
/*-
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* Copyright (c) 2001 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#define PTE_PRESENT 0x0000000000000001
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#define PTE__RV1_ 0x0000000000000002
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#define PTE_MA_MASK 0x000000000000001C
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#define PTE_MA_WB 0x0000000000000000
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#define PTE_MA_UC 0x0000000000000010
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#define PTE_MA_UCE 0x0000000000000014
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#define PTE_MA_WC 0x0000000000000018
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#define PTE_MA_NATPAGE 0x000000000000001C
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#define PTE_ACCESSED 0x0000000000000020
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#define PTE_DIRTY 0x0000000000000040
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#define PTE_PL_MASK 0x0000000000000180
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#define PTE_PL_KERN 0x0000000000000000
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#define PTE_PL_USER 0x0000000000000180
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#define PTE_AR_MASK 0x0000000000000E00
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#define PTE_AR_R 0x0000000000000000
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#define PTE_AR_RX 0x0000000000000200
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#define PTE_AR_RW 0x0000000000000400
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#define PTE_AR_RWX 0x0000000000000600
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#define PTE_AR_R_RW 0x0000000000000800
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#define PTE_AR_RX_RWX 0x0000000000000A00
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#define PTE_AR_RWX_RW 0x0000000000000C00
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#define PTE_AR_X_RX 0x0000000000000E00
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#define PTE_PPN_MASK 0x0003FFFFFFFFF000
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#define PTE__RV2_ 0x000C000000000000
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#define PTE_ED 0x0010000000000000
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#define PTE_IG_MASK 0xFFE0000000000000
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#define PTE_WIRED 0x0020000000000000
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#define PTE_MANAGED 0x0040000000000000
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#define PTE_PROT_MASK 0x0700000000000000
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#ifndef LOCORE
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typedef uint64_t pt_entry_t;
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static __inline pt_entry_t
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pte_atomic_clear(pt_entry_t *ptep, uint64_t val)
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{
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return (atomic_clear_64(ptep, val));
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}
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static __inline pt_entry_t
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pte_atomic_set(pt_entry_t *ptep, uint64_t val)
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{
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return (atomic_set_64(ptep, val));
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}
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/*
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* Layout of cr.itir.
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*/
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struct ia64_itir {
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uint64_t __rv1__ :2; /* bits 0..1 */
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uint64_t ps :6; /* bits 2..7 */
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uint64_t key :24; /* bits 8..31 */
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uint64_t __rv2__ :32; /* bits 32..63 */
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};
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/*
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* A long-format VHPT entry.
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*/
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struct ia64_lpte {
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pt_entry_t pte;
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struct ia64_itir itir;
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uint64_t tag; /* includes ti */
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uint64_t chain; /* pa of collision chain */
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};
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/*
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* Layout of rr[x].
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*/
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struct ia64_rr {
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uint64_t rr_ve :1; /* bit 0 */
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uint64_t __rv1__ :1; /* bit 1 */
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uint64_t rr_ps :6; /* bits 2..7 */
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uint64_t rr_rid :24; /* bits 8..31 */
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uint64_t __rv2__ :32; /* bits 32..63 */
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};
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PTE_H_ */
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