df180be1a1
ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
416 lines
10 KiB
C
416 lines
10 KiB
C
/*
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* Product specific probe and attach routines for:
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* 27/284X and aic7770 motherboard SCSI controllers
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*
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* Copyright (c) 1994-1998, 2000, 2001 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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* $Id: //depot/aic7xxx/aic7xxx/aic7770.c#34 $
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*/
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#ifdef __linux__
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#include "aic7xxx_osm.h"
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#include "aic7xxx_inline.h"
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#include "aic7xxx_93cx6.h"
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#else
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <dev/aic7xxx/aic7xxx_osm.h>
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#include <dev/aic7xxx/aic7xxx_inline.h>
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#include <dev/aic7xxx/aic7xxx_93cx6.h>
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#endif
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#define ID_AIC7770 0x04907770
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#define ID_AHA_274x 0x04907771
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#define ID_AHA_284xB 0x04907756 /* BIOS enabled */
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#define ID_AHA_284x 0x04907757 /* BIOS disabled*/
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#define ID_OLV_274x 0x04907782 /* Olivetti OEM */
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#define ID_OLV_274xD 0x04907783 /* Olivetti OEM (Differential) */
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static int aic7770_chip_init(struct ahc_softc *ahc);
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static int aic7770_suspend(struct ahc_softc *ahc);
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static int aic7770_resume(struct ahc_softc *ahc);
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static int aha2840_load_seeprom(struct ahc_softc *ahc);
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static ahc_device_setup_t ahc_aic7770_VL_setup;
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static ahc_device_setup_t ahc_aic7770_EISA_setup;;
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static ahc_device_setup_t ahc_aic7770_setup;
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struct aic7770_identity aic7770_ident_table[] =
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{
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{
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ID_AHA_274x,
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0xFFFFFFFF,
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"Adaptec 274X SCSI adapter",
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ahc_aic7770_EISA_setup
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},
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{
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ID_AHA_284xB,
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0xFFFFFFFE,
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"Adaptec 284X SCSI adapter",
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ahc_aic7770_VL_setup
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},
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{
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ID_AHA_284x,
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0xFFFFFFFE,
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"Adaptec 284X SCSI adapter (BIOS Disabled)",
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ahc_aic7770_VL_setup
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},
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{
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ID_OLV_274x,
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0xFFFFFFFF,
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"Adaptec (Olivetti OEM) 274X SCSI adapter",
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ahc_aic7770_EISA_setup
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},
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{
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ID_OLV_274xD,
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0xFFFFFFFF,
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"Adaptec (Olivetti OEM) 274X Differential SCSI adapter",
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ahc_aic7770_EISA_setup
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},
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/* Generic chip probes for devices we don't know 'exactly' */
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{
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ID_AIC7770,
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0xFFFFFFFF,
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"Adaptec aic7770 SCSI adapter",
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ahc_aic7770_EISA_setup
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}
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};
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const int ahc_num_aic7770_devs = NUM_ELEMENTS(aic7770_ident_table);
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struct aic7770_identity *
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aic7770_find_device(uint32_t id)
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{
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struct aic7770_identity *entry;
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int i;
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for (i = 0; i < ahc_num_aic7770_devs; i++) {
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entry = &aic7770_ident_table[i];
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if (entry->full_id == (id & entry->id_mask))
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return (entry);
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}
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return (NULL);
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}
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int
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aic7770_config(struct ahc_softc *ahc, struct aic7770_identity *entry, u_int io)
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{
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u_long l;
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int error;
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int have_seeprom;
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u_int hostconf;
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u_int irq;
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u_int intdef;
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error = entry->setup(ahc);
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have_seeprom = 0;
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if (error != 0)
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return (error);
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error = aic7770_map_registers(ahc, io);
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if (error != 0)
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return (error);
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/*
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* Before we continue probing the card, ensure that
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* its interrupts are *disabled*. We don't want
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* a misstep to hang the machine in an interrupt
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* storm.
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*/
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ahc_intr_enable(ahc, FALSE);
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ahc->description = entry->name;
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error = ahc_softc_init(ahc);
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if (error != 0)
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return (error);
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ahc->bus_chip_init = aic7770_chip_init;
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ahc->bus_suspend = aic7770_suspend;
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ahc->bus_resume = aic7770_resume;
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error = ahc_reset(ahc, /*reinit*/FALSE);
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if (error != 0)
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return (error);
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/* Make sure we have a valid interrupt vector */
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intdef = ahc_inb(ahc, INTDEF);
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irq = intdef & VECTOR;
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switch (irq) {
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case 9:
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case 10:
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case 11:
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case 12:
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case 14:
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case 15:
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break;
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default:
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printf("aic7770_config: invalid irq setting %d\n", intdef);
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return (ENXIO);
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}
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if ((intdef & EDGE_TRIG) != 0)
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ahc->flags |= AHC_EDGE_INTERRUPT;
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switch (ahc->chip & (AHC_EISA|AHC_VL)) {
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case AHC_EISA:
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{
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u_int biosctrl;
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u_int scsiconf;
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u_int scsiconf1;
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biosctrl = ahc_inb(ahc, HA_274_BIOSCTRL);
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scsiconf = ahc_inb(ahc, SCSICONF);
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scsiconf1 = ahc_inb(ahc, SCSICONF + 1);
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/* Get the primary channel information */
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if ((biosctrl & CHANNEL_B_PRIMARY) != 0)
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ahc->flags |= 1;
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if ((biosctrl & BIOSMODE) == BIOSDISABLED) {
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ahc->flags |= AHC_USEDEFAULTS;
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} else {
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if ((ahc->features & AHC_WIDE) != 0) {
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ahc->our_id = scsiconf1 & HWSCSIID;
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if (scsiconf & TERM_ENB)
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ahc->flags |= AHC_TERM_ENB_A;
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} else {
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ahc->our_id = scsiconf & HSCSIID;
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ahc->our_id_b = scsiconf1 & HSCSIID;
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if (scsiconf & TERM_ENB)
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ahc->flags |= AHC_TERM_ENB_A;
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if (scsiconf1 & TERM_ENB)
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ahc->flags |= AHC_TERM_ENB_B;
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}
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}
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if ((ahc_inb(ahc, HA_274_BIOSGLOBAL) & HA_274_EXTENDED_TRANS))
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ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B;
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break;
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}
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case AHC_VL:
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{
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have_seeprom = aha2840_load_seeprom(ahc);
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break;
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}
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default:
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break;
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}
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if (have_seeprom == 0) {
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free(ahc->seep_config, M_DEVBUF);
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ahc->seep_config = NULL;
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}
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/*
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* Ensure autoflush is enabled
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*/
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ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
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/* Setup the FIFO threshold and the bus off time */
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hostconf = ahc_inb(ahc, HOSTCONF);
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ahc_outb(ahc, BUSSPD, hostconf & DFTHRSH);
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ahc_outb(ahc, BUSTIME, (hostconf << 2) & BOFF);
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ahc->bus_softc.aic7770_softc.busspd = hostconf & DFTHRSH;
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ahc->bus_softc.aic7770_softc.bustime = (hostconf << 2) & BOFF;
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/*
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* Generic aic7xxx initialization.
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*/
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error = ahc_init(ahc);
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if (error != 0)
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return (error);
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error = aic7770_map_int(ahc, irq);
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if (error != 0)
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return (error);
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ahc_list_lock(&l);
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/*
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* Link this softc in with all other ahc instances.
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*/
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ahc_softc_insert(ahc);
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/*
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* Enable the board's BUS drivers
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*/
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ahc_outb(ahc, BCTL, ENABLE);
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ahc_list_unlock(&l);
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return (0);
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}
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static int
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aic7770_chip_init(struct ahc_softc *ahc)
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{
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ahc_outb(ahc, BUSSPD, ahc->bus_softc.aic7770_softc.busspd);
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ahc_outb(ahc, BUSTIME, ahc->bus_softc.aic7770_softc.bustime);
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ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~AUTOFLUSHDIS);
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ahc_outb(ahc, BCTL, ENABLE);
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return (ahc_chip_init(ahc));
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}
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static int
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aic7770_suspend(struct ahc_softc *ahc)
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{
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return (ahc_suspend(ahc));
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}
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static int
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aic7770_resume(struct ahc_softc *ahc)
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{
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return (ahc_resume(ahc));
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}
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/*
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* Read the 284x SEEPROM.
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*/
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static int
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aha2840_load_seeprom(struct ahc_softc *ahc)
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{
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struct seeprom_descriptor sd;
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struct seeprom_config *sc;
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int have_seeprom;
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uint8_t scsi_conf;
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sd.sd_ahc = ahc;
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sd.sd_control_offset = SEECTL_2840;
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sd.sd_status_offset = STATUS_2840;
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sd.sd_dataout_offset = STATUS_2840;
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sd.sd_chip = C46;
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sd.sd_MS = 0;
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sd.sd_RDY = EEPROM_TF;
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sd.sd_CS = CS_2840;
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sd.sd_CK = CK_2840;
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sd.sd_DO = DO_2840;
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sd.sd_DI = DI_2840;
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sc = ahc->seep_config;
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if (bootverbose)
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printf("%s: Reading SEEPROM...", ahc_name(ahc));
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have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
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/*start_addr*/0, sizeof(*sc)/2);
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if (have_seeprom) {
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if (ahc_verify_cksum(sc) == 0) {
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if(bootverbose)
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printf ("checksum error\n");
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have_seeprom = 0;
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} else if (bootverbose) {
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printf("done.\n");
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}
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}
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if (!have_seeprom) {
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if (bootverbose)
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printf("%s: No SEEPROM available\n", ahc_name(ahc));
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ahc->flags |= AHC_USEDEFAULTS;
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} else {
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/*
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* Put the data we've collected down into SRAM
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* where ahc_init will find it.
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*/
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int i;
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int max_targ;
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uint16_t discenable;
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max_targ = (ahc->features & AHC_WIDE) != 0 ? 16 : 8;
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discenable = 0;
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for (i = 0; i < max_targ; i++){
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uint8_t target_settings;
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target_settings = (sc->device_flags[i] & CFXFER) << 4;
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if (sc->device_flags[i] & CFSYNCH)
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target_settings |= SOFS;
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if (sc->device_flags[i] & CFWIDEB)
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target_settings |= WIDEXFER;
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if (sc->device_flags[i] & CFDISC)
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discenable |= (0x01 << i);
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ahc_outb(ahc, TARG_SCSIRATE + i, target_settings);
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}
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ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
|
|
ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
|
|
|
|
ahc->our_id = sc->brtime_id & CFSCSIID;
|
|
|
|
scsi_conf = (ahc->our_id & 0x7);
|
|
if (sc->adapter_control & CFSPARITY)
|
|
scsi_conf |= ENSPCHK;
|
|
if (sc->adapter_control & CFRESETB)
|
|
scsi_conf |= RESET_SCSI;
|
|
|
|
if (sc->bios_control & CF284XEXTEND)
|
|
ahc->flags |= AHC_EXTENDED_TRANS_A;
|
|
/* Set SCSICONF info */
|
|
ahc_outb(ahc, SCSICONF, scsi_conf);
|
|
|
|
if (sc->adapter_control & CF284XSTERM)
|
|
ahc->flags |= AHC_TERM_ENB_A;
|
|
}
|
|
return (have_seeprom);
|
|
}
|
|
|
|
static int
|
|
ahc_aic7770_VL_setup(struct ahc_softc *ahc)
|
|
{
|
|
int error;
|
|
|
|
error = ahc_aic7770_setup(ahc);
|
|
ahc->chip |= AHC_VL;
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
ahc_aic7770_EISA_setup(struct ahc_softc *ahc)
|
|
{
|
|
int error;
|
|
|
|
error = ahc_aic7770_setup(ahc);
|
|
ahc->chip |= AHC_EISA;
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
ahc_aic7770_setup(struct ahc_softc *ahc)
|
|
{
|
|
ahc->channel = 'A';
|
|
ahc->channel_b = 'B';
|
|
ahc->chip = AHC_AIC7770;
|
|
ahc->features = AHC_AIC7770_FE;
|
|
ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
|
|
ahc->flags |= AHC_PAGESCBS;
|
|
ahc->instruction_ram_size = 448;
|
|
return (0);
|
|
}
|