5184251d09
Offet for the power control register was specified incorrectly (it had the same value as the prefetch control register.) This change corrects the offset value to 0xF80, per the ARM PL310 documentation. Submitted by: Steve Kiernan <stevek@juniper.net> Obtained from: Juniper Networks, Inc.
189 lines
6.5 KiB
C
189 lines
6.5 KiB
C
/*-
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* Copyright (c) 2012 Olivier Houchard. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $FreeBSD$
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*/
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#ifndef PL310_H_
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#define PL310_H_
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/**
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* PL310 - L2 Cache Controller register offsets.
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*
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*/
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#define PL310_CACHE_ID 0x000
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#define CACHE_ID_RELEASE_SHIFT 0
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#define CACHE_ID_RELEASE_MASK 0x3f
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#define CACHE_ID_RELEASE_r0p0 0x00
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#define CACHE_ID_RELEASE_r1p0 0x02
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#define CACHE_ID_RELEASE_r2p0 0x04
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#define CACHE_ID_RELEASE_r3p0 0x05
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#define CACHE_ID_RELEASE_r3p1 0x06
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#define CACHE_ID_RELEASE_r3p2 0x08
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#define CACHE_ID_RELEASE_r3p3 0x09
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#define CACHE_ID_PARTNUM_SHIFT 6
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#define CACHE_ID_PARTNUM_MASK 0xf
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#define CACHE_ID_PARTNUM_VALUE 0x3
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#define PL310_CACHE_TYPE 0x004
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#define PL310_CTRL 0x100
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#define CTRL_ENABLED 0x01
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#define CTRL_DISABLED 0x00
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#define PL310_AUX_CTRL 0x104
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#define AUX_CTRL_MASK 0xc0000fff
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#define AUX_CTRL_ASSOCIATIVITY_SHIFT 16
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#define AUX_CTRL_WAY_SIZE_SHIFT 17
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#define AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
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#define AUX_CTRL_SHARE_OVERRIDE (1 << 22)
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#define AUX_CTRL_NS_LOCKDOWN (1 << 26)
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#define AUX_CTRL_NS_INT_CTRL (1 << 27)
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#define AUX_CTRL_DATA_PREFETCH (1 << 28)
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#define AUX_CTRL_INSTR_PREFETCH (1 << 29)
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#define AUX_CTRL_EARLY_BRESP (1 << 30)
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#define PL310_TAG_RAM_CTRL 0x108
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#define PL310_DATA_RAM_CTRL 0x10C
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#define RAM_CTRL_WRITE_SHIFT 8
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#define RAM_CTRL_WRITE_MASK (0x7 << 8)
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#define RAM_CTRL_READ_SHIFT 4
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#define RAM_CTRL_READ_MASK (0x7 << 4)
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#define RAM_CTRL_SETUP_SHIFT 0
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#define RAM_CTRL_SETUP_MASK (0x7 << 0)
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#define PL310_EVENT_COUNTER_CTRL 0x200
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#define EVENT_COUNTER_CTRL_ENABLED (1 << 0)
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#define EVENT_COUNTER_CTRL_C0_RESET (1 << 1)
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#define EVENT_COUNTER_CTRL_C1_RESET (1 << 2)
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#define PL310_EVENT_COUNTER1_CONF 0x204
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#define PL310_EVENT_COUNTER0_CONF 0x208
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#define EVENT_COUNTER_CONF_NOINTR 0
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#define EVENT_COUNTER_CONF_INCR 1
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#define EVENT_COUNTER_CONF_OVFW 2
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#define EVENT_COUNTER_CONF_NOEV (0 << 2)
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#define EVENT_COUNTER_CONF_CO (1 << 2)
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#define EVENT_COUNTER_CONF_DRHIT (2 << 2)
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#define EVENT_COUNTER_CONF_DRREQ (3 << 2)
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#define EVENT_COUNTER_CONF_DWHIT (4 << 2)
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#define EVENT_COUNTER_CONF_DWREQ (5 << 2)
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#define EVENT_COUNTER_CONF_DWTREQ (6 << 2)
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#define EVENT_COUNTER_CONF_DIRHIT (7 << 2)
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#define EVENT_COUNTER_CONF_DIRREQ (8 << 2)
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#define EVENT_COUNTER_CONF_WA (9 << 2)
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#define PL310_EVENT_COUNTER1_VAL 0x20C
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#define PL310_EVENT_COUNTER0_VAL 0x210
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#define PL310_INTR_MASK 0x214
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#define PL310_MASKED_INTR_STAT 0x218
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#define PL310_RAW_INTR_STAT 0x21C
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#define PL310_INTR_CLEAR 0x220
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#define INTR_MASK_ALL ((1 << 9) - 1)
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#define INTR_MASK_ECNTR (1 << 0)
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#define INTR_MASK_PARRT (1 << 1)
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#define INTR_MASK_PARRD (1 << 2)
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#define INTR_MASK_ERRWT (1 << 3)
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#define INTR_MASK_ERRWD (1 << 4)
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#define INTR_MASK_ERRRT (1 << 5)
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#define INTR_MASK_ERRRD (1 << 6)
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#define INTR_MASK_SLVERR (1 << 7)
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#define INTR_MASK_DECERR (1 << 8)
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#define PL310_CACHE_SYNC 0x730
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#define PL310_INV_LINE_PA 0x770
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#define PL310_INV_WAY 0x77C
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#define PL310_CLEAN_LINE_PA 0x7B0
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#define PL310_CLEAN_LINE_IDX 0x7B8
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#define PL310_CLEAN_WAY 0x7BC
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#define PL310_CLEAN_INV_LINE_PA 0x7F0
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#define PL310_CLEAN_INV_LINE_IDX 0x7F8
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#define PL310_CLEAN_INV_WAY 0x7FC
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#define PL310_LOCKDOWN_D_WAY(x) (0x900 + ((x) * 8))
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#define PL310_LOCKDOWN_I_WAY(x) (0x904 + ((x) * 8))
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#define PL310_LOCKDOWN_LINE_ENABLE 0x950
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#define PL310_UNLOCK_ALL_LINES_WAY 0x954
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#define PL310_ADDR_FILTER_STAR 0xC00
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#define PL310_ADDR_FILTER_END 0xC04
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#define PL310_DEBUG_CTRL 0xF40
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#define DEBUG_CTRL_DISABLE_LINEFILL (1 << 0)
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#define DEBUG_CTRL_DISABLE_WRITEBACK (1 << 1)
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#define DEBUG_CTRL_SPNIDEN (1 << 2)
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#define PL310_PREFETCH_CTRL 0xF60
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#define PREFETCH_CTRL_OFFSET_MASK (0x1f)
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#define PREFETCH_CTRL_NOTSAMEID (1 << 21)
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#define PREFETCH_CTRL_INCR_DL (1 << 23)
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#define PREFETCH_CTRL_PREFETCH_DROP (1 << 24)
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#define PREFETCH_CTRL_DL_ON_WRAP (1 << 27)
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#define PREFETCH_CTRL_DATA_PREFETCH (1 << 28)
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#define PREFETCH_CTRL_INSTR_PREFETCH (1 << 29)
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#define PREFETCH_CTRL_DL (1 << 30)
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#define PL310_POWER_CTRL 0xF80
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#define POWER_CTRL_ENABLE_GATING (1 << 0)
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#define POWER_CTRL_ENABLE_STANDBY (1 << 1)
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struct intr_config_hook;
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struct pl310_softc {
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device_t sc_dev;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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void* sc_irq_h;
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int sc_enabled;
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struct mtx sc_mtx;
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u_int sc_rtl_revision;
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struct intr_config_hook *sc_ich;
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};
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/**
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* pl310_read4 - read a 32-bit value from the PL310 registers
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* pl310_write4 - write a 32-bit value from the PL310 registers
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* @off: byte offset within the register set to read from
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* @val: the value to write into the register
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*
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*
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* LOCKING:
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* None
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*
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* RETURNS:
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* nothing in case of write function, if read function returns the value read.
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*/
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static __inline uint32_t
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pl310_read4(struct pl310_softc *sc, bus_size_t off)
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{
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return bus_read_4(sc->sc_mem_res, off);
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}
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static __inline void
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pl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->sc_mem_res, off, val);
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}
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void pl310_print_config(struct pl310_softc *sc);
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void pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg,
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uint32_t read, uint32_t write, uint32_t setup);
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void platform_pl310_init(struct pl310_softc *);
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void platform_pl310_write_ctrl(struct pl310_softc *, uint32_t);
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void platform_pl310_write_debug(struct pl310_softc *, uint32_t);
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#endif /* PL310_H_ */
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