9ed346bab0
mtx_enter(lock, type) becomes:
mtx_lock(lock) for sleep locks (MTX_DEF-initialized locks)
mtx_lock_spin(lock) for spin locks (MTX_SPIN-initialized)
similarily, for releasing a lock, we now have:
mtx_unlock(lock) for MTX_DEF and mtx_unlock_spin(lock) for MTX_SPIN.
We change the caller interface for the two different types of locks
because the semantics are entirely different for each case, and this
makes it explicitly clear and, at the same time, it rids us of the
extra `type' argument.
The enter->lock and exit->unlock change has been made with the idea
that we're "locking data" and not "entering locked code" in mind.
Further, remove all additional "flags" previously passed to the
lock acquire/release routines with the exception of two:
MTX_QUIET and MTX_NOSWITCH
The functionality of these flags is preserved and they can be passed
to the lock/unlock routines by calling the corresponding wrappers:
mtx_{lock, unlock}_flags(lock, flag(s)) and
mtx_{lock, unlock}_spin_flags(lock, flag(s)) for MTX_DEF and MTX_SPIN
locks, respectively.
Re-inline some lock acq/rel code; in the sleep lock case, we only
inline the _obtain_lock()s in order to ensure that the inlined code
fits into a cache line. In the spin lock case, we inline recursion and
actually only perform a function call if we need to spin. This change
has been made with the idea that we generally tend to avoid spin locks
and that also the spin locks that we do have and are heavily used
(i.e. sched_lock) do recurse, and therefore in an effort to reduce
function call overhead for some architectures (such as alpha), we
inline recursion for this case.
Create a new malloc type for the witness code and retire from using
the M_DEV type. The new type is called M_WITNESS and is only declared
if WITNESS is enabled.
Begin cleaning up some machdep/mutex.h code - specifically updated the
"optimized" inlined code in alpha/mutex.h and wrote MTX_LOCK_SPIN
and MTX_UNLOCK_SPIN asm macros for the i386/mutex.h as we presently
need those.
Finally, caught up to the interface changes in all sys code.
Contributors: jake, jhb, jasone (in no particular order)
260 lines
7.4 KiB
C
260 lines
7.4 KiB
C
/*
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Register definitions for ADMtek Pegasus AN986 USB to Ethernet
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* chip. The Pegasus uses a total of four USB endpoints: the control
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* endpoint (0), a bulk read endpoint for receiving packets (1),
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* a bulk write endpoint for sending packets (2) and an interrupt
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* endpoint for passing RX and TX status (3). Endpoint 0 is used
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* to read and write the ethernet module's registers. All registers
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* are 8 bits wide.
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*
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* Packet transfer is done in 64 byte chunks. The last chunk in a
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* transfer is denoted by having a length less that 64 bytes. For
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* the RX case, the data includes an optional RX status word.
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*/
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#define AUE_VENDORID_ADMTEK 0x07A6
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#define AUE_DEVICEID_PEGASUS 0x0986
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#define AUE_VENDORID_BILLIONTON 0x08DD
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#define AUE_DEVICEID_USB100 0x0986
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#define AUE_VENDORID_MELCO 0x0411
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#define AUE_DEVICEID_LUATX 0x0001
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#define AUE_UR_READREG 0xF0
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#define AUE_UR_WRITEREG 0xF1
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#define AUE_CONFIG_NO 1
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/*
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* Note that while the ADMtek technically has four
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* endpoints, the control endpoint (endpoint 0) is
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* regarded as special by the USB code and drivers
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* don't have direct access to it. (We access it
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* using usbd_do_request() when reading/writing
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* registers.) Consequently, our endpoint indexes
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* don't match those in the ADMtek Pegasus manual:
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* we consider the RX data endpoint to be index 0
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* and work up from there.
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*/
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#define AUE_ENDPT_RX 0x0
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#define AUE_ENDPT_TX 0x1
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#define AUE_ENDPT_INTR 0x2
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#define AUE_ENDPT_MAX 0x3
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#define AUE_INTR_PKTLEN 0x8
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#define AUE_CTL0 0x00
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#define AUE_CTL1 0x01
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#define AUE_CTL2 0x02
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#define AUE_MAR0 0x08
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#define AUE_MAR1 0x09
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#define AUE_MAR2 0x0A
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#define AUE_MAR3 0x0B
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#define AUE_MAR4 0x0C
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#define AUE_MAR5 0x0D
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#define AUE_MAR6 0x0E
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#define AUE_MAR7 0x0F
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#define AUE_MAR AUE_MAR0
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#define AUE_PAR0 0x10
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#define AUE_PAR1 0x11
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#define AUE_PAR2 0x12
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#define AUE_PAR3 0x13
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#define AUE_PAR4 0x14
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#define AUE_PAR5 0x15
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#define AUE_PAR AUE_PAR0
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#define AUE_PAUSE0 0x18
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#define AUE_PAUSE1 0x19
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#define AUE_PAUSE AUE_PAUSE0
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#define AUE_RX_FLOWCTL_CNT 0x1A
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#define AUE_RX_FLOWCTL_FIFO 0x1B
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#define AUE_EE_REG 0x20
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#define AUE_EE_DATA0 0x21
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#define AUE_EE_DATA1 0x22
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#define AUE_EE_DATA AUE_EE_DATA0
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#define AUE_EE_CTL 0x23
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#define AUE_PHY_ADDR 0x25
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#define AUE_PHY_DATA0 0x26
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#define AUE_PHY_DATA1 0x27
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#define AUE_PHY_DATA AUE_PHY_DATA0
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#define AUE_PHY_CTL 0x28
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#define AUE_USB_STS 0x2A
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#define AUE_TXSTAT0 0x2B
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#define AUE_TXSTAT1 0x2C
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#define AUE_TXSTAT AUE_TXSTAT0
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#define AUE_RXSTAT 0x2D
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#define AUE_PKTLOST0 0x2E
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#define AUE_PKTLOST1 0x2F
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#define AUE_PKTLOST AUE_PKTLOST0
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#define AUE_GPIO0 0x7E
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#define AUE_GPIO1 0x7F
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#define AUE_CTL0_INCLUDE_RXCRC 0x01
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#define AUE_CTL0_ALLMULTI 0x02
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#define AUE_CTL0_STOP_BACKOFF 0x04
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#define AUE_CTL0_RXSTAT_APPEND 0x08
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#define AUE_CTL0_WAKEON_ENB 0x10
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#define AUE_CTL0_RXPAUSE_ENB 0x20
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#define AUE_CTL0_RX_ENB 0x40
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#define AUE_CTL0_TX_ENB 0x80
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#define AUE_CTL1_HOMELAN 0x04
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#define AUE_CTL1_RESETMAC 0x08
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#define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */
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#define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */
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#define AUE_CTL1_DELAYHOME 0x40
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#define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */
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#define AUE_CTL2_RX_BADFRAMES 0x02
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#define AUE_CTL2_RX_PROMISC 0x04
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#define AUE_CTL2_LOOPBACK 0x08
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#define AUE_CTL2_EEPROMWR_ENB 0x10
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#define AUE_CTL2_EEPROM_LOAD 0x20
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#define AUE_EECTL_WRITE 0x01
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#define AUE_EECTL_READ 0x02
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#define AUE_EECTL_DONE 0x04
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#define AUE_PHYCTL_PHYREG 0x1F
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#define AUE_PHYCTL_WRITE 0x20
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#define AUE_PHYCTL_READ 0x40
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#define AUE_PHYCTL_DONE 0x80
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#define AUE_USBSTS_SUSPEND 0x01
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#define AUE_USBSTS_RESUME 0x02
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#define AUE_TXSTAT0_JABTIMO 0x04
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#define AUE_TXSTAT0_CARLOSS 0x08
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#define AUE_TXSTAT0_NOCARRIER 0x10
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#define AUE_TXSTAT0_LATECOLL 0x20
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#define AUE_TXSTAT0_EXCESSCOLL 0x40
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#define AUE_TXSTAT0_UNDERRUN 0x80
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#define AUE_TXSTAT1_PKTCNT 0x0F
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#define AUE_TXSTAT1_FIFO_EMPTY 0x40
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#define AUE_TXSTAT1_FIFO_FULL 0x80
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#define AUE_RXSTAT_OVERRUN 0x01
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#define AUE_RXSTAT_PAUSE 0x02
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#define AUE_GPIO_IN0 0x01
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#define AUE_GPIO_OUT0 0x02
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#define AUE_GPIO_SEL0 0x04
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#define AUE_GPIO_IN1 0x08
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#define AUE_GPIO_OUT1 0x10
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#define AUE_GPIO_SEL1 0x20
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struct aue_intrpkt {
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u_int8_t aue_txstat0;
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u_int8_t aue_txstat1;
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u_int8_t aue_rxstat;
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u_int8_t aue_rxlostpkt0;
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u_int8_t aue_rxlostpkt1;
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u_int8_t aue_wakeupstat;
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u_int8_t aue_rsvd;
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};
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struct aue_rxpkt {
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u_int16_t aue_pktlen;
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u_int8_t aue_rxstat;
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};
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#define AUE_RXSTAT_MCAST 0x01
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#define AUE_RXSTAT_GIANT 0x02
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#define AUE_RXSTAT_RUNT 0x04
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#define AUE_RXSTAT_CRCERR 0x08
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#define AUE_RXSTAT_DRIBBLE 0x10
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#define AUE_RXSTAT_MASK 0x1E
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struct aue_type {
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u_int16_t aue_vid;
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u_int16_t aue_did;
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};
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#define AUE_TX_LIST_CNT 1
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#define AUE_RX_LIST_CNT 1
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struct aue_softc;
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struct aue_chain {
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struct aue_softc *aue_sc;
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usbd_xfer_handle aue_xfer;
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char *aue_buf;
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struct mbuf *aue_mbuf;
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int aue_idx;
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};
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struct aue_cdata {
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struct aue_chain aue_tx_chain[AUE_TX_LIST_CNT];
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struct aue_chain aue_rx_chain[AUE_RX_LIST_CNT];
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struct aue_intrpkt *aue_ibuf;
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int aue_tx_prod;
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int aue_tx_cons;
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int aue_tx_cnt;
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int aue_rx_prod;
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};
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#define AUE_INC(x, y) (x) = (x + 1) % y
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struct aue_softc {
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struct arpcom arpcom;
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device_t aue_miibus;
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usbd_device_handle aue_udev;
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usbd_interface_handle aue_iface;
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struct aue_type *aue_info;
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int aue_ed[AUE_ENDPT_MAX];
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usbd_pipe_handle aue_ep[AUE_ENDPT_MAX];
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int aue_unit;
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u_int8_t aue_link;
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u_int8_t aue_gone;
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int aue_if_flags;
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struct aue_cdata aue_cdata;
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struct callout_handle aue_stat_ch;
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struct mtx aue_mtx;
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};
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#define AUE_LOCK(_sc) mtx_lock(&(_sc)->aue_mtx)
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#define AUE_UNLOCK(_sc) mtx_unlock(&(_sc)->aue_mtx)
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#define AUE_TIMEOUT 1000
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#define ETHER_ALIGN 2
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#define AUE_BUFSZ 1536
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#define AUE_MIN_FRAMELEN 60
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#define AUE_INTR_INTERVAL 100 /* ms */
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