154 lines
4.1 KiB
Plaintext
154 lines
4.1 KiB
Plaintext
/*-
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* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* /dts-v1/; */
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#include "socfpga_cyclone5_sockit.dts"
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/ {
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model = "Terasic SoCkit";
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */
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< 0x00001000 0x1000 >, /* virtio block */
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< 0x00002000 0x1000 >; /* virtio net */
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soc {
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/* Local timer */
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timer@fffec600 {
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clock-frequency = <200000000>;
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};
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/* Global timer */
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global_timer: timer@fffec200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xfffec200 0x20>;
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interrupts = <1 11 0xf04>;
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clock-frequency = <200000000>;
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};
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beri_mem0: mem@d0000000 {
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compatible = "sri-cambridge,beri-mem";
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reg = <0xd0000000 0x10000000>; /* 256mb */
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status = "okay";
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};
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pio0: pio@c0020000 {
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compatible = "altr,pio";
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reg = <0xc0020000 0x1000>; /* recv */
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interrupts = < 76 >;
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status = "okay";
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};
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pio1: pio@c0021000 {
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compatible = "altr,pio";
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reg = <0xc0021000 0x1000>; /* send */
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interrupts = < 82 >; /* not in use on arm side */
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status = "okay";
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};
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pio2: pio@c0022000 {
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compatible = "altr,pio";
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reg = <0xc0022000 0x1000>; /* recv */
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interrupts = < 77 >;
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status = "okay";
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};
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pio3: pio@c0023000 {
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compatible = "altr,pio";
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reg = <0xc0023000 0x1000>; /* send */
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interrupts = < 83 >; /* not in use on arm side */
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status = "okay";
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};
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beri_vtblk: vtblk@00001000 {
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compatible = "sri-cambridge,beri-vtblk";
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reg = <0x00001000 0x1000>;
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pio-recv = <&pio0>;
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pio-send = <&pio1>;
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beri-mem = <&beri_mem0>;
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status = "okay";
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};
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beri_vtnet: vtnet@00002000 {
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compatible = "sri-cambridge,beri-vtnet";
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reg = <0x00002000 0x1000>;
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pio-recv = <&pio2>;
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pio-send = <&pio3>;
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beri-mem = <&beri_mem0>;
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status = "okay";
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};
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beri_debug: ring@c0000000 {
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compatible = "sri-cambridge,beri-ring";
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reg = <0xc0000000 0x3000>;
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interrupts = < 72 73 >;
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device_name = "beri_debug";
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data_size = <0x1000>;
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data_read = <0x0>;
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data_write = <0x1000>;
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control_read = <0x2000>;
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control_write = <0x2010>;
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status = "okay";
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};
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beri_console: ring@c0004000 {
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compatible = "sri-cambridge,beri-ring";
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reg = <0xc0004000 0x3000>;
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interrupts = < 74 75 >;
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device_name = "beri_console";
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data_size = <0x1000>;
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data_read = <0x0>;
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data_write = <0x1000>;
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control_read = <0x2000>;
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control_write = <0x2010>;
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status = "okay";
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};
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};
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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};
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};
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&mmc0 {
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bus-frequency = <25000000>;
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};
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&uart0 {
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clock-frequency = <100000000>;
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};
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&uart1 {
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status = "disabled";
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};
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