af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
426 lines
12 KiB
C
426 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Oleksandr Rybalko under sponsorship
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* from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/machdep.h> /* For arm_set_delay */
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#include <arm/freescale/imx/imx_gptreg.h>
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#define WRITE4(_sc, _r, _v) \
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bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
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#define READ4(_sc, _r) \
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bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
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#define SET4(_sc, _r, _m) \
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WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
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#define CLEAR4(_sc, _r, _m) \
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WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
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static u_int imx_gpt_get_timecount(struct timecounter *);
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static int imx_gpt_timer_start(struct eventtimer *, sbintime_t,
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sbintime_t);
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static int imx_gpt_timer_stop(struct eventtimer *);
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static void imx_gpt_do_delay(int, void *);
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static int imx_gpt_intr(void *);
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static int imx_gpt_probe(device_t);
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static int imx_gpt_attach(device_t);
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static struct timecounter imx_gpt_timecounter = {
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.tc_name = "iMXGPT",
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.tc_get_timecount = imx_gpt_get_timecount,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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struct imx_gpt_softc {
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device_t sc_dev;
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struct resource * res[2];
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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void * sc_ih; /* interrupt handler */
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uint32_t sc_period;
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uint32_t sc_clksrc;
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uint32_t clkfreq;
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uint32_t ir_reg;
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struct eventtimer et;
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};
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/* Try to divide down an available fast clock to this frequency. */
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#define TARGET_FREQUENCY 1000000000
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static struct resource_spec imx_gpt_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6dl-gpt", 1},
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{"fsl,imx6q-gpt", 1},
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{"fsl,imx6ul-gpt", 1},
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{"fsl,imx53-gpt", 1},
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{"fsl,imx51-gpt", 1},
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{"fsl,imx31-gpt", 1},
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{"fsl,imx27-gpt", 1},
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{"fsl,imx25-gpt", 1},
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{NULL, 0}
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};
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static int
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imx_gpt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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/*
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* We only support a single unit, because the only thing this driver
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* does with the complex timer hardware is supply the system
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* timecounter and eventtimer. There is nothing useful we can do with
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* the additional device instances that exist in some chips.
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*/
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if (device_get_unit(dev) > 0)
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
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device_set_desc(dev, "Freescale i.MX GPT timer");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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imx_gpt_attach(device_t dev)
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{
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struct imx_gpt_softc *sc;
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int ctlreg, err;
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uint32_t basefreq, prescale, setup_ticks, t1, t2;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->sc_dev = dev;
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sc->sc_iot = rman_get_bustag(sc->res[0]);
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sc->sc_ioh = rman_get_bushandle(sc->res[0]);
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/*
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* For now, just automatically choose a good clock for the hardware
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* we're running on. Eventually we could allow selection from the fdt;
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* the code in this driver will cope with any clock frequency.
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*/
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sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
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ctlreg = 0;
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switch (sc->sc_clksrc) {
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case GPT_CR_CLKSRC_32K:
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basefreq = 32768;
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break;
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case GPT_CR_CLKSRC_IPG:
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basefreq = imx_ccm_ipg_hz();
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break;
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case GPT_CR_CLKSRC_IPG_HIGH:
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basefreq = imx_ccm_ipg_hz() * 2;
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break;
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case GPT_CR_CLKSRC_24M:
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ctlreg |= GPT_CR_24MEN;
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basefreq = 24000000;
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break;
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case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */
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case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */
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default:
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device_printf(dev, "Unsupported clock source '%d'\n",
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sc->sc_clksrc);
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return (EINVAL);
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}
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/*
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* The following setup sequence is from the I.MX6 reference manual,
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* "Selecting the clock source". First, disable the clock and
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* interrupts. This also clears input and output mode bits and in
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* general completes several of the early steps in the procedure.
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*/
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WRITE4(sc, IMX_GPT_CR, 0);
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WRITE4(sc, IMX_GPT_IR, 0);
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/* Choose the clock and the power-saving behaviors. */
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ctlreg |=
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sc->sc_clksrc | /* Use selected clock */
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GPT_CR_FRR | /* Just count (FreeRunner mode) */
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GPT_CR_STOPEN | /* Run in STOP mode */
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GPT_CR_DOZEEN | /* Run in DOZE mode */
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GPT_CR_WAITEN | /* Run in WAIT mode */
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GPT_CR_DBGEN; /* Run in DEBUG mode */
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WRITE4(sc, IMX_GPT_CR, ctlreg);
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/*
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* The datasheet says to do the software reset after choosing the clock
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* source. It says nothing about needing to wait for the reset to
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* complete, but the register description does document the fact that
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* the reset isn't complete until the SWR bit reads 0, so let's be safe.
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* The reset also clears all registers except for a few of the bits in
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* CR, but we'll rewrite all the CR bits when we start the counter.
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*/
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WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
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while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)
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continue;
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/* Set a prescaler value that gets us near the target frequency. */
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if (basefreq < TARGET_FREQUENCY) {
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prescale = 0;
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sc->clkfreq = basefreq;
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} else {
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prescale = basefreq / TARGET_FREQUENCY;
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sc->clkfreq = basefreq / prescale;
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prescale -= 1; /* 1..n range is 0..n-1 in hardware. */
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}
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WRITE4(sc, IMX_GPT_PR, prescale);
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/* Clear the status register. */
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WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
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/* Start the counter. */
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WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN);
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if (bootverbose)
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device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n",
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sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));
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/* Setup the timer interrupt. */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
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NULL, sc, &sc->sc_ih);
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if (err != 0) {
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bus_release_resources(dev, imx_gpt_spec, sc->res);
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device_printf(dev, "Unable to setup the clock irq handler, "
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"err = %d\n", err);
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return (ENXIO);
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}
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/*
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* Measure how many clock ticks it takes to setup a one-shot event (it's
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* longer than you might think, due to wait states in accessing gpt
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* registers). Scale up the result by a factor of 1.5 to be safe,
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* and use that to set the minimum eventtimer period we can schedule. In
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* the real world, the value works out to about 750ns on imx5 hardware.
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*/
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t1 = READ4(sc, IMX_GPT_CNT);
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WRITE4(sc, IMX_GPT_OCR3, 0);
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t2 = READ4(sc, IMX_GPT_CNT);
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setup_ticks = ((t2 - t1 + 1) * 3) / 2;
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/* Register as an eventtimer. */
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sc->et.et_name = "iMXGPT";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
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sc->et.et_quality = 800;
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sc->et.et_frequency = sc->clkfreq;
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sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq;
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sc->et.et_max_period = ((uint64_t)0xfffffffe << 32) / sc->clkfreq;
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sc->et.et_start = imx_gpt_timer_start;
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sc->et.et_stop = imx_gpt_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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/* Register as a timecounter. */
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imx_gpt_timecounter.tc_frequency = sc->clkfreq;
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imx_gpt_timecounter.tc_priv = sc;
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tc_init(&imx_gpt_timecounter);
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/* If this is the first unit, store the softc for use in DELAY. */
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if (device_get_unit(dev) == 0) {
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arm_set_delay(imx_gpt_do_delay, sc);
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}
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return (0);
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}
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static int
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imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct imx_gpt_softc *sc;
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uint32_t ticks;
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sc = (struct imx_gpt_softc *)et->et_priv;
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if (period != 0) {
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sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
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/* Set expected value */
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WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);
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/* Enable compare register 2 Interrupt */
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sc->ir_reg |= GPT_IR_OF2;
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WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
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return (0);
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} else if (first != 0) {
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/* Enable compare register 3 interrupt if not already on. */
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if ((sc->ir_reg & GPT_IR_OF3) == 0) {
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sc->ir_reg |= GPT_IR_OF3;
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WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
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}
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ticks = ((uint32_t)et->et_frequency * first) >> 32;
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/* Do not disturb, otherwise event will be lost */
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spinlock_enter();
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/* Set expected value */
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WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks);
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/* Now everybody can relax */
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spinlock_exit();
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return (0);
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}
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return (EINVAL);
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}
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static int
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imx_gpt_timer_stop(struct eventtimer *et)
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{
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struct imx_gpt_softc *sc;
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sc = (struct imx_gpt_softc *)et->et_priv;
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/* Disable interrupts and clear any pending status. */
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sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3);
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WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
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WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3);
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sc->sc_period = 0;
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return (0);
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}
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static int
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imx_gpt_intr(void *arg)
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{
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struct imx_gpt_softc *sc;
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uint32_t status;
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sc = (struct imx_gpt_softc *)arg;
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status = READ4(sc, IMX_GPT_SR);
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/*
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* Clear interrupt status before invoking event callbacks. The callback
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* often sets up a new one-shot timer event and if the interval is short
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* enough it can fire before we get out of this function. If we cleared
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* at the bottom we'd miss the interrupt and hang until the clock wraps.
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*/
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WRITE4(sc, IMX_GPT_SR, status);
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/* Handle one-shot timer events. */
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if (status & GPT_IR_OF3) {
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if (sc->et.et_active) {
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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}
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}
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/* Handle periodic timer events. */
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if (status & GPT_IR_OF2) {
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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if (sc->sc_period != 0)
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WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) +
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sc->sc_period);
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}
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return (FILTER_HANDLED);
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}
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static u_int
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imx_gpt_get_timecount(struct timecounter *tc)
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{
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struct imx_gpt_softc *sc;
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sc = tc->tc_priv;
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return (READ4(sc, IMX_GPT_CNT));
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}
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static device_method_t imx_gpt_methods[] = {
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DEVMETHOD(device_probe, imx_gpt_probe),
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DEVMETHOD(device_attach, imx_gpt_attach),
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DEVMETHOD_END
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};
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static driver_t imx_gpt_driver = {
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"imx_gpt",
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imx_gpt_methods,
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sizeof(struct imx_gpt_softc),
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};
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static devclass_t imx_gpt_devclass;
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EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0,
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0, BUS_PASS_TIMER);
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static void
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imx_gpt_do_delay(int usec, void *arg)
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{
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struct imx_gpt_softc *sc = arg;
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uint64_t curcnt, endcnt, startcnt, ticks;
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/*
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* Calculate the tick count with 64-bit values so that it works for any
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* clock frequency. Loop until the hardware count reaches start+ticks.
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* If the 32-bit hardware count rolls over while we're looping, just
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* manually do a carry into the high bits after each read; don't worry
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* that doing this on each loop iteration is inefficient -- we're trying
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* to waste time here.
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*/
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ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000;
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curcnt = startcnt = READ4(sc, IMX_GPT_CNT);
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endcnt = startcnt + ticks;
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while (curcnt < endcnt) {
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curcnt = READ4(sc, IMX_GPT_CNT);
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if (curcnt < startcnt)
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curcnt += 1ULL << 32;
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}
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}
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