Warner Losh 14f4e15704 Correct the CONFIG0_VI value. According to ... http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the config0 word, not bit 2. This should fix virtually indexed caches (relatively new in the MIPS world, so no current platforms used this and current code just uses it as an optimization). It was causing false positives on newer platforms that default to large values for the kseg0 cache coherency attribute. Submitted by: Stanislav Galabov PR: 205249		2015-12-11 16:51:04 +00:00
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adm5120	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
alchemy	Fix a typo introduced in r257338.	2013-10-31 02:27:16 +00:00
atheros	Add QCA9533 to the list of SoCs that require IRQ's be ACKed.	2015-11-16 06:15:01 +00:00
beri	preload_search_info: make sure mod is set	2015-08-21 15:57:57 +00:00
cavium	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
conf	Add support for the integrated wifi for the QCA953x base config and	2015-11-29 05:49:49 +00:00
gxemul	Add 32-bit support for Gxemul's oldtestmips machine emulation	2013-09-04 20:34:36 +00:00
idt	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
include	Correct the CONFIG0_VI value. According to	2015-12-11 16:51:04 +00:00
malta	[mips]: Don't hard-code PHYS_AVAIL_ENTRIES.	2015-11-22 02:40:19 +00:00
mips	Add helper functions proc_readmem() and proc_writemem().	2015-12-07 21:33:15 +00:00
nlm	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
rmi	Add domain support to PCI bus allocation	2015-09-16 23:34:51 +00:00
rt305x	Add support for the uart classes to set their default register shift value.	2015-04-11 17:16:23 +00:00
sentry5	Merge from vmobj-rwlock branch:	2013-02-26 01:00:11 +00:00
sibyte	Devices that rely on hints or identify routines for discovery need to	2013-10-29 14:07:31 +00:00