71d90c04a8
to check the status property in their probe routines. Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings. Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
732 lines
17 KiB
C
732 lines
17 KiB
C
/*
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* Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp>
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* Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include "bcm2835_dma.h"
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#include "bcm2835_vcbus.h"
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#define MAX_REG 9
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/* private flags */
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#define BCM_DMA_CH_USED 0x00000001
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#define BCM_DMA_CH_FREE 0x40000000
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#define BCM_DMA_CH_UNMAP 0x80000000
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/* Register Map (4.2.1.2) */
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#define BCM_DMA_CS(n) (0x100*(n) + 0x00)
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#define CS_ACTIVE (1 << 0)
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#define CS_END (1 << 1)
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#define CS_INT (1 << 2)
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#define CS_DREQ (1 << 3)
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#define CS_ISPAUSED (1 << 4)
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#define CS_ISHELD (1 << 5)
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#define CS_ISWAIT (1 << 6)
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#define CS_ERR (1 << 8)
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#define CS_WAITWRT (1 << 28)
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#define CS_DISDBG (1 << 29)
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#define CS_ABORT (1 << 30)
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#define CS_RESET (1U << 31)
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#define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04)
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#define BCM_DMA_INFO(n) (0x100*(n) + 0x08)
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#define INFO_INT_EN (1 << 0)
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#define INFO_TDMODE (1 << 1)
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#define INFO_WAIT_RESP (1 << 3)
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#define INFO_D_INC (1 << 4)
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#define INFO_D_WIDTH (1 << 5)
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#define INFO_D_DREQ (1 << 6)
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#define INFO_S_INC (1 << 8)
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#define INFO_S_WIDTH (1 << 9)
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#define INFO_S_DREQ (1 << 10)
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#define INFO_WAITS_SHIFT (21)
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#define INFO_PERMAP_SHIFT (16)
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#define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT)
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#define BCM_DMA_SRC(n) (0x100*(n) + 0x0C)
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#define BCM_DMA_DST(n) (0x100*(n) + 0x10)
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#define BCM_DMA_LEN(n) (0x100*(n) + 0x14)
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#define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18)
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#define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C)
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#define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20)
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#define DEBUG_ERROR_MASK (7)
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#define BCM_DMA_INT_STATUS 0xfe0
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#define BCM_DMA_ENABLE 0xff0
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/* relative offset from BCM_VC_DMA0_BASE (p.39) */
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#define BCM_DMA_CH(n) (0x100*(n))
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/* DMA Control Block - 256bit aligned (p.40) */
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struct bcm_dma_cb {
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uint32_t info; /* Transfer Information */
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uint32_t src; /* Source Address */
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uint32_t dst; /* Destination Address */
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uint32_t len; /* Transfer Length */
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uint32_t stride; /* 2D Mode Stride */
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uint32_t next; /* Next Control Block Address */
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uint32_t rsvd1; /* Reserved */
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uint32_t rsvd2; /* Reserved */
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};
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#ifdef DEBUG
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static void bcm_dma_cb_dump(struct bcm_dma_cb *cb);
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static void bcm_dma_reg_dump(int ch);
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#endif
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/* DMA channel private info */
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struct bcm_dma_ch {
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int ch;
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uint32_t flags;
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struct bcm_dma_cb * cb;
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uint32_t vc_cb;
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bus_dmamap_t dma_map;
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void (*intr_func)(int, void *);
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void * intr_arg;
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};
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struct bcm_dma_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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struct resource * sc_mem;
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struct resource * sc_irq[BCM_DMA_CH_MAX];
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void * sc_intrhand[BCM_DMA_CH_MAX];
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struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX];
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bus_dma_tag_t sc_dma_tag;
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};
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static struct bcm_dma_softc *bcm_dma_sc = NULL;
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static void
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bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
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int nseg, int err)
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{
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bus_addr_t *addr;
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if (err)
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return;
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addr = (bus_addr_t*)arg;
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*addr = PHYS_TO_VCBUS(segs[0].ds_addr);
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}
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static void
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bcm_dma_reset(device_t dev, int ch)
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{
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struct bcm_dma_softc *sc = device_get_softc(dev);
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struct bcm_dma_cb *cb;
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uint32_t cs;
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int count;
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if (ch < 0 || ch >= BCM_DMA_CH_MAX)
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return;
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cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
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if (cs & CS_ACTIVE) {
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/* pause current task */
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bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0);
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count = 1000;
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do {
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cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch));
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} while (!(cs & CS_ISPAUSED) && (count-- > 0));
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if (!(cs & CS_ISPAUSED)) {
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device_printf(dev,
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"Can't abort DMA transfer at channel %d\n", ch);
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}
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bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
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/* Complete everything, clear interrupt */
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bus_write_4(sc->sc_mem, BCM_DMA_CS(ch),
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CS_ABORT | CS_INT | CS_END| CS_ACTIVE);
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}
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/* clear control blocks */
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bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0);
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bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0);
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/* Reset control block */
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cb = sc->sc_dma_ch[ch].cb;
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bzero(cb, sizeof(*cb));
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cb->info = INFO_WAIT_RESP;
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}
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static int
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bcm_dma_init(device_t dev)
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{
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struct bcm_dma_softc *sc = device_get_softc(dev);
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uint32_t mask;
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struct bcm_dma_ch *ch;
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void *cb_virt;
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vm_paddr_t cb_phys;
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int err;
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int i;
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/* disable and clear interrupt status */
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bus_write_4(sc->sc_mem, BCM_DMA_ENABLE, 0);
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bus_write_4(sc->sc_mem, BCM_DMA_INT_STATUS, 0);
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/* Allocate DMA chunks control blocks */
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/* p.40 of spec - control block should be 32-bit aligned */
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err = bus_dma_tag_create(bus_get_dma_tag(dev),
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1, 0, BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR, NULL, NULL,
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sizeof(struct bcm_dma_cb), 1,
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sizeof(struct bcm_dma_cb),
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BUS_DMA_ALLOCNOW, NULL, NULL,
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&sc->sc_dma_tag);
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if (err) {
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device_printf(dev, "failed allocate DMA tag");
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return (err);
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}
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/* setup initial settings */
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for (i = 0; i < BCM_DMA_CH_MAX; i++) {
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ch = &sc->sc_dma_ch[i];
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err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt,
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BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
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&ch->dma_map);
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if (err) {
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device_printf(dev, "cannot allocate DMA memory\n");
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break;
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}
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/*
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* Least alignment for busdma-allocated stuff is cache
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* line size, so just make sure nothing stupid happend
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* and we got properly aligned address
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*/
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if ((uintptr_t)cb_virt & 0x1f) {
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device_printf(dev,
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"DMA address is not 32-bytes aligned: %p\n",
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(void*)cb_virt);
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break;
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}
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err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt,
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sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys,
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BUS_DMA_WAITOK);
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if (err) {
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device_printf(dev, "cannot load DMA memory\n");
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break;
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}
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bzero(ch, sizeof(struct bcm_dma_ch));
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ch->ch = i;
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ch->cb = cb_virt;
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ch->vc_cb = cb_phys;
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ch->intr_func = NULL;
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ch->intr_arg = NULL;
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ch->flags = BCM_DMA_CH_UNMAP;
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ch->cb->info = INFO_WAIT_RESP;
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/* reset DMA engine */
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bcm_dma_reset(dev, i);
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}
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/* now use DMA2/DMA3 only */
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sc->sc_dma_ch[2].flags = BCM_DMA_CH_FREE;
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sc->sc_dma_ch[3].flags = BCM_DMA_CH_FREE;
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/* enable DMAs */
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mask = 0;
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for (i = 0; i < BCM_DMA_CH_MAX; i++)
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if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE)
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mask |= (1 << i);
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bus_write_4(sc->sc_mem, BCM_DMA_ENABLE, mask);
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return (0);
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}
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/*
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* Allocate DMA channel for further use, returns channel # or
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* BCM_DMA_CH_INVALID
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*/
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int
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bcm_dma_allocate(int req_ch)
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{
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struct bcm_dma_softc *sc = bcm_dma_sc;
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int ch = BCM_DMA_CH_INVALID;
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int i;
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if (req_ch >= BCM_DMA_CH_MAX)
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return (BCM_DMA_CH_INVALID);
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/* Auto(req_ch < 0) or CH specified */
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mtx_lock(&sc->sc_mtx);
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if (req_ch < 0) {
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for (i = 0; i < BCM_DMA_CH_MAX; i++) {
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if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) {
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ch = i;
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sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
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sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
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break;
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}
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}
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}
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else {
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if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) {
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ch = req_ch;
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sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE;
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sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED;
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}
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}
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mtx_unlock(&sc->sc_mtx);
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return (ch);
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}
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/*
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* Frees allocated channel. Returns 0 on success, -1 otherwise
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*/
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int
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bcm_dma_free(int ch)
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{
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struct bcm_dma_softc *sc = bcm_dma_sc;
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if (ch < 0 || ch >= BCM_DMA_CH_MAX)
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return (-1);
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mtx_lock(&sc->sc_mtx);
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if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) {
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sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE;
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sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED;
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sc->sc_dma_ch[ch].intr_func = NULL;
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sc->sc_dma_ch[ch].intr_arg = NULL;
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/* reset DMA engine */
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bcm_dma_reset(sc->sc_dev, ch);
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}
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mtx_unlock(&sc->sc_mtx);
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return (0);
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}
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/*
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* Assign handler function for channel interrupt
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* Returns 0 on success, -1 otherwise
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*/
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int
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bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg)
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{
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struct bcm_dma_softc *sc = bcm_dma_sc;
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struct bcm_dma_cb *cb;
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if (ch < 0 || ch >= BCM_DMA_CH_MAX)
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return (-1);
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if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
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return (-1);
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sc->sc_dma_ch[ch].intr_func = func;
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sc->sc_dma_ch[ch].intr_arg = arg;
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cb = sc->sc_dma_ch[ch].cb;
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cb->info |= INFO_INT_EN;
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return (0);
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}
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/*
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* Setup DMA source parameters
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* ch - channel number
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* dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
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* source is physical memory
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* inc_addr - BCM_DMA_INC_ADDR if source address
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* should be increased after each access or
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* BCM_DMA_SAME_ADDR if address should remain
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* the same
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* width - size of read operation, BCM_DMA_32BIT
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* for 32bit bursts, BCM_DMA_128BIT for 128 bits
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*
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* Returns 0 on success, -1 otherwise
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*/
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int
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bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width)
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{
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struct bcm_dma_softc *sc = bcm_dma_sc;
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uint32_t info;
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if (ch < 0 || ch >= BCM_DMA_CH_MAX)
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return (-1);
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if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
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return (-1);
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info = sc->sc_dma_ch[ch].cb->info;
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info &= ~INFO_PERMAP_MASK;
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info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
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if (dreq)
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info |= INFO_S_DREQ;
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else
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info &= ~INFO_S_DREQ;
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if (width == BCM_DMA_128BIT)
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info |= INFO_S_WIDTH;
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else
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info &= ~INFO_S_WIDTH;
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if (inc_addr == BCM_DMA_INC_ADDR)
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info |= INFO_S_INC;
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else
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info &= ~INFO_S_INC;
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sc->sc_dma_ch[ch].cb->info = info;
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return (0);
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}
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/*
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* Setup DMA destination parameters
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* ch - channel number
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* dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if
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* destination is physical memory
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* inc_addr - BCM_DMA_INC_ADDR if source address
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* should be increased after each access or
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* BCM_DMA_SAME_ADDR if address should remain
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* the same
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* width - size of write operation, BCM_DMA_32BIT
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* for 32bit bursts, BCM_DMA_128BIT for 128 bits
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*
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* Returns 0 on success, -1 otherwise
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*/
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int
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bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width)
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{
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struct bcm_dma_softc *sc = bcm_dma_sc;
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uint32_t info;
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if (ch < 0 || ch >= BCM_DMA_CH_MAX)
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return (-1);
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if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
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return (-1);
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info = sc->sc_dma_ch[ch].cb->info;
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info &= ~INFO_PERMAP_MASK;
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info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK;
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if (dreq)
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info |= INFO_D_DREQ;
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else
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info &= ~INFO_D_DREQ;
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if (width == BCM_DMA_128BIT)
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info |= INFO_D_WIDTH;
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else
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info &= ~INFO_D_WIDTH;
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if (inc_addr == BCM_DMA_INC_ADDR)
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info |= INFO_D_INC;
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else
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info &= ~INFO_D_INC;
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sc->sc_dma_ch[ch].cb->info = info;
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return (0);
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}
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#ifdef DEBUG
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void
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bcm_dma_cb_dump(struct bcm_dma_cb *cb)
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{
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printf("DMA CB ");
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|
printf("INFO: %8.8x ", cb->info);
|
|
printf("SRC: %8.8x ", cb->src);
|
|
printf("DST: %8.8x ", cb->dst);
|
|
printf("LEN: %8.8x ", cb->len);
|
|
printf("\n");
|
|
printf("STRIDE: %8.8x ", cb->stride);
|
|
printf("NEXT: %8.8x ", cb->next);
|
|
printf("RSVD1: %8.8x ", cb->rsvd1);
|
|
printf("RSVD2: %8.8x ", cb->rsvd2);
|
|
printf("\n");
|
|
}
|
|
|
|
void
|
|
bcm_dma_reg_dump(int ch)
|
|
{
|
|
struct bcm_dma_softc *sc = bcm_dma_sc;
|
|
int i;
|
|
uint32_t reg;
|
|
|
|
if (ch < 0 || ch >= BCM_DMA_CH_MAX)
|
|
return;
|
|
|
|
printf("DMA%d: ", ch);
|
|
for (i = 0; i < MAX_REG; i++) {
|
|
reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4);
|
|
printf("%8.8x ", reg);
|
|
}
|
|
printf("\n");
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Start DMA transaction
|
|
* ch - channel number
|
|
* src, dst - source and destination address in
|
|
* ARM physical memory address space.
|
|
* len - amount of bytes to be transfered
|
|
*
|
|
* Returns 0 on success, -1 otherwise
|
|
*/
|
|
int
|
|
bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len)
|
|
{
|
|
struct bcm_dma_softc *sc = bcm_dma_sc;
|
|
struct bcm_dma_cb *cb;
|
|
|
|
if (ch < 0 || ch >= BCM_DMA_CH_MAX)
|
|
return (-1);
|
|
|
|
if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
|
|
return (-1);
|
|
|
|
cb = sc->sc_dma_ch[ch].cb;
|
|
if (BCM2835_ARM_IS_IO(src))
|
|
cb->src = IO_TO_VCBUS(src);
|
|
else
|
|
cb->src = PHYS_TO_VCBUS(src);
|
|
if (BCM2835_ARM_IS_IO(dst))
|
|
cb->dst = IO_TO_VCBUS(dst);
|
|
else
|
|
cb->dst = PHYS_TO_VCBUS(dst);
|
|
cb->len = len;
|
|
|
|
bus_dmamap_sync(sc->sc_dma_tag,
|
|
sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE);
|
|
|
|
bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch),
|
|
sc->sc_dma_ch[ch].vc_cb);
|
|
bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE);
|
|
|
|
#ifdef DEBUG
|
|
bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb);
|
|
bcm_dma_reg_dump(ch);
|
|
#endif
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Get length requested for DMA transaction
|
|
* ch - channel number
|
|
*
|
|
* Returns size of transaction, 0 if channel is invalid
|
|
*/
|
|
uint32_t
|
|
bcm_dma_length(int ch)
|
|
{
|
|
struct bcm_dma_softc *sc = bcm_dma_sc;
|
|
struct bcm_dma_cb *cb;
|
|
|
|
if (ch < 0 || ch >= BCM_DMA_CH_MAX)
|
|
return (0);
|
|
|
|
if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED))
|
|
return (0);
|
|
|
|
cb = sc->sc_dma_ch[ch].cb;
|
|
|
|
return (cb->len);
|
|
}
|
|
|
|
static void
|
|
bcm_dma_intr(void *arg)
|
|
{
|
|
struct bcm_dma_softc *sc = bcm_dma_sc;
|
|
struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg;
|
|
uint32_t cs, debug;
|
|
|
|
/* my interrupt? */
|
|
cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch));
|
|
|
|
if (!(cs & (CS_INT | CS_ERR)))
|
|
return;
|
|
|
|
/* running? */
|
|
if (!(ch->flags & BCM_DMA_CH_USED)) {
|
|
device_printf(sc->sc_dev,
|
|
"unused DMA intr CH=%d, CS=%x\n", ch->ch, cs);
|
|
return;
|
|
}
|
|
|
|
if (cs & CS_ERR) {
|
|
debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch));
|
|
device_printf(sc->sc_dev, "DMA error %d on CH%d\n",
|
|
debug & DEBUG_ERROR_MASK, ch->ch);
|
|
bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch),
|
|
debug & DEBUG_ERROR_MASK);
|
|
bcm_dma_reset(sc->sc_dev, ch->ch);
|
|
}
|
|
|
|
if (cs & CS_INT) {
|
|
/* acknowledge interrupt */
|
|
bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch),
|
|
CS_INT | CS_END);
|
|
|
|
/* Prepare for possible access to len field */
|
|
bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map,
|
|
BUS_DMASYNC_POSTWRITE);
|
|
|
|
/* save callback function and argument */
|
|
if (ch->intr_func)
|
|
ch->intr_func(ch->ch, ch->intr_arg);
|
|
}
|
|
}
|
|
|
|
static int
|
|
bcm_dma_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-dma"))
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "BCM2835 DMA Controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
bcm_dma_attach(device_t dev)
|
|
{
|
|
struct bcm_dma_softc *sc = device_get_softc(dev);
|
|
int rid, err = 0;
|
|
int i;
|
|
|
|
sc->sc_dev = dev;
|
|
|
|
if (bcm_dma_sc)
|
|
return (ENXIO);
|
|
|
|
for (i = 0; i < BCM_DMA_CH_MAX; i++) {
|
|
sc->sc_irq[i] = NULL;
|
|
sc->sc_intrhand[i] = NULL;
|
|
}
|
|
|
|
/* DMA0 - DMA14 */
|
|
rid = 0;
|
|
sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
|
|
if (sc->sc_mem == NULL) {
|
|
device_printf(dev, "could not allocate memory resource\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */
|
|
for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) {
|
|
sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->sc_irq[rid] == NULL) {
|
|
device_printf(dev, "cannot allocate interrupt\n");
|
|
err = ENXIO;
|
|
goto fail;
|
|
}
|
|
if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, bcm_dma_intr, &sc->sc_dma_ch[rid],
|
|
&sc->sc_intrhand[rid])) {
|
|
device_printf(dev, "cannot setup interrupt handler\n");
|
|
err = ENXIO;
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF);
|
|
bcm_dma_sc = sc;
|
|
|
|
err = bcm_dma_init(dev);
|
|
if (err)
|
|
goto fail;
|
|
|
|
return (err);
|
|
|
|
fail:
|
|
if (sc->sc_mem)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem);
|
|
|
|
for (i = 0; i < BCM_DMA_CH_MAX; i++) {
|
|
if (sc->sc_intrhand[i])
|
|
bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]);
|
|
if (sc->sc_irq[i])
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]);
|
|
}
|
|
|
|
return (err);
|
|
}
|
|
|
|
static device_method_t bcm_dma_methods[] = {
|
|
DEVMETHOD(device_probe, bcm_dma_probe),
|
|
DEVMETHOD(device_attach, bcm_dma_attach),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t bcm_dma_driver = {
|
|
"bcm_dma",
|
|
bcm_dma_methods,
|
|
sizeof(struct bcm_dma_softc),
|
|
};
|
|
|
|
static devclass_t bcm_dma_devclass;
|
|
|
|
DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0);
|
|
MODULE_VERSION(bcm_dma, 1);
|