90 lines
4.2 KiB
C
90 lines
4.2 KiB
C
/* $FreeBSD$ */
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/* $OpenBSD: ebusreg.h,v 1.4 2001/10/01 18:08:04 jason Exp $ */
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/* $NetBSD: ebusreg.h,v 1.8 2008/05/29 14:51:27 mrg Exp $ */
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/*-
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* Copyright (c) 1999 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* UltraSPARC `ebus'
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*
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* The `ebus' bus is designed to plug traditional PC-ISA devices into
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* an SPARC system with as few costs as possible, without sacrificing
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* to performance. Typically, it is implemented in the PCIO IC from
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* SME, which also implements a `hme-compatible' PCI network device
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* (`network'). The ebus has 4 DMA channels, similar to the DMA seen
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* in the ESP SCSI DMA.
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*
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* Typical UltraSPARC systems have a NatSemi SuperIO IC to provide
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* serial ports for the keyboard and mouse (`se'), floppy disk
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* controller (`fdthree'), parallel port controller (`bpp') connected
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* to the ebus, and a PCI-IDE controller (connected directly to the
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* PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual
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* channel serial controller (`su' providing ttya and ttyb), an MK48T59
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* EEPROM/clock controller (also where the idprom, including the
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* ethernet address, is located), the audio system (`SUNW,CS4231', same
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* as other UltraSPARC and some SPARC systems), and other various
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* internal devices found on traditional SPARC systems such as the
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* `power', `flashprom', etc., devices.
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*
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* The ebus uses an interrupt mapping scheme similar to PCI, though
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* the actual structures are different.
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*/
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/* EBUS dma registers */
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#define EBDMA_DCSR 0x0 /* control/status */
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#define EBDMA_DADDR 0x4 /* DMA address */
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#define EBDMA_DCNT 0x8 /* DMA count */
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/* EBUS DMA control/status (EBDMA_DCSR) */
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#define EBDCSR_INT 0x00000001 /* interrupt pending */
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#define EBDCSR_ERR 0x00000002 /* error pending */
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#define EBDCSR_DRAIN 0x00000004 /* drain */
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#define EBDCSR_INTEN 0x00000010 /* interrupt enable */
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#define EBDCSR_RESET 0x00000080 /* reset */
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#define EBDCSR_WRITE 0x00000100 /* write */
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#define EBDCSR_DMAEN 0x00000200 /* dma enable */
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#define EBDCSR_CYC 0x00000400 /* cyc pending */
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#define EBDCSR_DIAGRD 0x00000800 /* diagnostic read done */
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#define EBDCSR_DIAGWR 0x00001000 /* diagnostic write done */
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#define EBDCSR_CNTEN 0x00002000 /* count enable */
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#define EBDCSR_TC 0x00004000 /* terminal count */
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#define EBDCSR_CSRDRNDIS 0x00010000 /* disable csr drain */
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#define EBDCSR_BURSTMASK 0x000c0000 /* burst size mask */
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#define EBDCSR_BURST_1 0x00080000 /* burst 1 */
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#define EBDCSR_BURST_4 0x00000000 /* burst 4 */
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#define EBDCSR_BURST_8 0x00040000 /* burst 8 */
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#define EBDCSR_BURST_16 0x000c0000 /* burst 16 */
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#define EBDCSR_DIAGEN 0x00100000 /* enable diagnostics */
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#define EBDCSR_ERRDIS 0x00400000 /* disable error pending */
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#define EBDCSR_TCIDIS 0x00800000 /* disable TCI */
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#define EBDCSR_NEXTEN 0x01000000 /* enable next */
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#define EBDCSR_DMAON 0x02000000 /* dma on */
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#define EBDCSR_A_LOADED 0x04000000 /* address loaded */
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#define EBDCSR_NA_LOADED 0x08000000 /* next address loaded */
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#define EBDCSR_DEVMASK 0xf0000000 /* device id mask */
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