facdd1cd20
Add 64-bit address support to Cadence CGEM Ethernet driver for use in other SoCs such as the Zynq UltraScale+ and SiFive HighFive Unleashed. Reviewed by: philip, 0mp (manpages) Differential Revision: https://reviews.freebsd.org/D24304
248 lines
6.0 KiB
Plaintext
248 lines
6.0 KiB
Plaintext
/*-
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* Copyright (c) 2016 The FreeBSD Foundation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/ {
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compatible = "xlnx,zynq-7000";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&GIC>;
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// Reserve first half megabyte because it is not accessible to all
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// bus masters.
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memreserve = <0x00000000 0x00080000>;
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// Zynq PS System registers.
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//
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ps7sys@f8000000 {
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device_type = "soc";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xf8000000 0xf10000>;
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// SLCR block
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slcr: slcr@7000 {
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compatible = "xlnx,zy7_slcr";
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reg = <0x0 0x1000>;
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};
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// Interrupt controller
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GIC: gic {
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compatible = "arm,gic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <3>;
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reg = <0xf01000 0x1000>, // distributer registers
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<0xf00100 0x0100>; // CPU if registers
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};
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// L2 cache controller
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pl310@f02000 {
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compatible = "arm,pl310";
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reg = <0xf02000 0x1000>;
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interrupts = <0 2 4>;
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interrupt-parent = <&GIC>;
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};
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// Device Config
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devcfg: devcfg@7000 {
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compatible = "xlnx,zy7_devcfg";
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reg = <0x7000 0x1000>;
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interrupts = <0 8 4>;
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interrupt-parent = <&GIC>;
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};
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// triple timer counters0,1
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ttc0: ttc@1000 {
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compatible = "xlnx,ttc";
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reg = <0x1000 0x1000>;
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};
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ttc1: ttc@2000 {
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compatible = "xlnx,ttc";
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reg = <0x2000 0x1000>;
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};
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// ARM Cortex A9 TWD Timer
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global_timer: timer@f00600 {
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compatible = "arm,mpcore-timers";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf00200 0x100>, // Global Timer Regs
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<0xf00600 0x20>; // Private Timer Regs
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interrupts = <1 11 1>, <1 13 1>;
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interrupt-parent = <&GIC>;
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};
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// system watch-dog timer
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swdt@5000 {
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device_type = "watchdog";
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compatible = "xlnx,zy7_wdt";
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reg = <0x5000 0x1000>;
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interrupts = <0 9 1>;
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interrupt-parent = <&GIC>;
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};
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scuwdt@f00620 {
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device_type = "watchdog";
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compatible = "arm,mpcore_wdt";
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reg = <0xf00620 0x20>;
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interrupts = <1 14 1>;
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interrupt-parent = <&GIC>;
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reset = <1>;
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};
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}; // pssys@f8000000
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// Zynq PS I/O Peripheral registers.
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//
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ps7io@e0000000 {
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device_type = "soc";
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0000000 0x300000>;
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// UART controllers
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uart0: uart@0000 {
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device_type = "serial";
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compatible = "cadence,uart";
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status = "disabled";
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reg = <0x0000 0x1000>;
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interrupts = <0 27 4>;
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interrupt-parent = <&GIC>;
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clock-frequency = <50000000>;
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};
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uart1: uart@1000 {
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device_type = "serial";
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compatible = "cadence,uart";
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status = "disabled";
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reg = <0x1000 0x1000>;
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interrupts = <0 50 4>;
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interrupt-parent = <&GIC>;
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clock-frequency = <50000000>;
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};
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// USB controllers
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ehci0: ehci@2000 {
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compatible = "xlnx,zy7_ehci";
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status = "disabled";
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reg = <0x2000 0x1000>;
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interrupts = <0 21 4>;
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interrupt-parent = <&GIC>;
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};
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ehci1: ehci@3000 {
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compatible = "xlnx,zy7_ehci";
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status = "disabled";
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reg = <0x3000 0x1000>;
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interrupts = <0 44 4>;
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interrupt-parent = <&GIC>;
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};
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// GPIO controller
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gpio: gpio@a000 {
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compatible = "xlnx,zy7_gpio";
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reg = <0xa000 0x1000>;
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interrupts = <0 20 4>;
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interrupt-parent = <&GIC>;
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};
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// Gigabit Ethernet controllers
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eth0: eth@b000 {
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device_type = "network";
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compatible = "cdns,zynq-gem", "cadence,gem";
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status = "disabled";
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reg = <0xb000 0x1000>;
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interrupts = <0 22 4>;
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interrupt-parent = <&GIC>;
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ref-clock-num = <0>;
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};
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eth1: eth@c000 {
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device_type = "network";
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compatible = "cdns,zynq-gem", "cadence,gem";
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status = "disabled";
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reg = <0xc000 0x1000>;
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interrupts = <0 45 4>;
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interrupt-parent = <&GIC>;
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ref-clock-num = <1>;
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};
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// Quad-SPI controller
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qspi0: qspi@d000 {
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compatible = "xlnx,zy7_qspi";
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status = "disabled";
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reg = <0xd000 0x1000>;
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interrupts = <0 19 4>;
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interrupt-parent = <&GIC>;
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ref-clock = <200000000>; // 200 Mhz
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spi-clock = <50000000>; // 50 Mhz
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};
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// SPI controllers
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spi0: spi0@6000 {
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compatible = "xlnx,zy7_spi";
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status = "disabled";
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reg = <0x6000 0x100>;
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interrupts = <0 26 4>;
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interrupt-parent = <&GIC>;
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};
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spi1: spi0@7000 {
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compatible = "xlnx,zy7_spi";
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status = "disabled";
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reg = <0x7000 0x100>;
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interrupts = <0 49 4>;
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interrupt-parent = <&GIC>;
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};
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// SDIO controllers
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sdhci0: sdhci@100000 {
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compatible = "xlnx,zy7_sdhci";
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status = "disabled";
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reg = <0x100000 0x1000>;
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interrupts = <0 24 4>;
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interrupt-parent = <&GIC>;
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max-frequency = <50000000>;
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};
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sdhci1: sdhci@101000 {
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compatible = "xlnx,zy7_sdhci";
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status = "disabled";
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reg = <0x101000 0x1000>;
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interrupts = <0 47 4>;
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interrupt-parent = <&GIC>;
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max-frequency = <50000000>;
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};
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}; // ps7io@e0000000
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};
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