607 lines
20 KiB
C
607 lines
20 KiB
C
/*-
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********************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __AL_HAL_PCIE_REGS_H__
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#define __AL_HAL_PCIE_REGS_H__
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/* Note: Definitions before the includes so axi/wrapper regs sees them */
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/** Maximum physical functions supported */
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#define REV1_2_MAX_NUM_OF_PFS 1
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#define REV3_MAX_NUM_OF_PFS 4
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#define AL_MAX_NUM_OF_PFS 4 /* the maximum between all Revisions */
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#include "al_hal_pcie_axi_reg.h"
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#ifndef AL_PCIE_EX
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#include "al_hal_pcie_w_reg.h"
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#else
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#include "al_hal_pcie_w_reg_ex.h"
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#endif
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#define AL_PCIE_AXI_REGS_OFFSET 0x0
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#define AL_PCIE_REV_1_2_APP_REGS_OFFSET 0x1000
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#define AL_PCIE_REV_3_APP_REGS_OFFSET 0x2000
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#define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET 0x2000
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#define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET 0x10000
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/** Maximum number of lanes supported */
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#define REV1_2_MAX_NUM_LANES 4
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#define REV3_MAX_NUM_LANES 8
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#define AL_MAX_NUM_OF_LANES 8 /* the maximum between all Revisions */
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/** Number of outbound atu regions - rev 1/2 */
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#define AL_PCIE_REV_1_2_ATU_NUM_OUTBOUND_REGIONS 12
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/** Number of outbound atu regions - rev 3 */
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#define AL_PCIE_REV_3_ATU_NUM_OUTBOUND_REGIONS 16
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struct al_pcie_core_iatu_regs {
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uint32_t index;
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uint32_t cr1;
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uint32_t cr2;
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uint32_t lower_base_addr;
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uint32_t upper_base_addr;
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uint32_t limit_addr;
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uint32_t lower_target_addr;
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uint32_t upper_target_addr;
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uint32_t cr3;
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uint32_t rsrvd[(0x270 - 0x224) >> 2];
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};
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struct al_pcie_core_port_regs {
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uint32_t ack_lat_rply_timer;
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uint32_t reserved1[(0x10 - 0x4) >> 2];
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uint32_t port_link_ctrl;
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uint32_t reserved2[(0x18 - 0x14) >> 2];
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uint32_t timer_ctrl_max_func_num;
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uint32_t filter_mask_reg_1;
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uint32_t reserved3[(0x48 - 0x20) >> 2];
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uint32_t vc0_posted_rcv_q_ctrl;
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uint32_t vc0_non_posted_rcv_q_ctrl;
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uint32_t vc0_comp_rcv_q_ctrl;
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uint32_t reserved4[(0x10C - 0x54) >> 2];
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uint32_t gen2_ctrl;
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uint32_t reserved5[(0x190 - 0x110) >> 2];
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uint32_t gen3_ctrl;
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uint32_t gen3_eq_fs_lf;
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uint32_t gen3_eq_preset_to_coef_map;
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uint32_t gen3_eq_preset_idx;
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uint32_t reserved6;
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uint32_t gen3_eq_status;
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uint32_t gen3_eq_ctrl;
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uint32_t reserved7[(0x1B8 - 0x1AC) >> 2];
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uint32_t pipe_loopback_ctrl;
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uint32_t rd_only_wr_en;
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uint32_t reserved8[(0x1D0 - 0x1C0) >> 2];
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uint32_t axi_slave_err_resp;
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uint32_t reserved9[(0x200 - 0x1D4) >> 2];
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struct al_pcie_core_iatu_regs iatu;
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uint32_t reserved10[(0x448 - 0x270) >> 2];
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};
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struct al_pcie_core_aer_regs {
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/* 0x0 - PCI Express Extended Capability Header */
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uint32_t header;
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/* 0x4 - Uncorrectable Error Status Register */
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uint32_t uncorr_err_stat;
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/* 0x8 - Uncorrectable Error Mask Register */
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uint32_t uncorr_err_mask;
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/* 0xc - Uncorrectable Error Severity Register */
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uint32_t uncorr_err_severity;
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/* 0x10 - Correctable Error Status Register */
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uint32_t corr_err_stat;
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/* 0x14 - Correctable Error Mask Register */
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uint32_t corr_err_mask;
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/* 0x18 - Advanced Error Capabilities and Control Register */
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uint32_t cap_and_ctrl;
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/* 0x1c - Header Log Registers */
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uint32_t header_log[4];
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/* 0x2c - Root Error Command Register */
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uint32_t root_err_cmd;
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/* 0x30 - Root Error Status Register */
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uint32_t root_err_stat;
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/* 0x34 - Error Source Identification Register */
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uint32_t err_src_id;
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};
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struct al_pcie_core_reg_space_rev_1_2 {
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uint32_t config_header[0x40 >> 2];
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uint32_t pcie_pm_cap_base;
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uint32_t reserved1[(0x70 - 0x44) >> 2];
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uint32_t pcie_cap_base;
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uint32_t pcie_dev_cap_base;
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uint32_t pcie_dev_ctrl_status;
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uint32_t pcie_link_cap_base;
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uint32_t reserved2[(0xB0 - 0x80) >> 2];
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uint32_t msix_cap_base;
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uint32_t reserved3[(0x100 - 0xB4) >> 2];
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struct al_pcie_core_aer_regs aer;
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uint32_t reserved4[(0x150 -
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(0x100 +
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sizeof(struct al_pcie_core_aer_regs))) >> 2];
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uint32_t pcie_sec_ext_cap_base;
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uint32_t reserved5[(0x700 - 0x154) >> 2];
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struct al_pcie_core_port_regs port_regs;
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uint32_t reserved6[(0x1000 -
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(0x700 +
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sizeof(struct al_pcie_core_port_regs))) >> 2];
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};
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struct al_pcie_core_reg_space_rev_3 {
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uint32_t config_header[0x40 >> 2];
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uint32_t pcie_pm_cap_base;
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uint32_t reserved1[(0x70 - 0x44) >> 2];
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uint32_t pcie_cap_base;
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uint32_t pcie_dev_cap_base;
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uint32_t pcie_dev_ctrl_status;
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uint32_t pcie_link_cap_base;
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uint32_t reserved2[(0xB0 - 0x80) >> 2];
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uint32_t msix_cap_base;
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uint32_t reserved3[(0x100 - 0xB4) >> 2];
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struct al_pcie_core_aer_regs aer;
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uint32_t reserved4[(0x158 -
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(0x100 +
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sizeof(struct al_pcie_core_aer_regs))) >> 2];
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/* pcie_sec_cap is only applicable for function 0 */
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uint32_t pcie_sec_ext_cap_base;
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uint32_t reserved5[(0x178 - 0x15C) >> 2];
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/* tph capability is only applicable for rev3 */
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uint32_t tph_cap_base;
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uint32_t reserved6[(0x700 - 0x17C) >> 2];
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/* port_regs is only applicable for function 0 */
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struct al_pcie_core_port_regs port_regs;
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uint32_t reserved7[(0x1000 -
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(0x700 +
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sizeof(struct al_pcie_core_port_regs))) >> 2];
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};
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struct al_pcie_rev3_core_reg_space {
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struct al_pcie_core_reg_space_rev_3 func[REV3_MAX_NUM_OF_PFS];
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};
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struct al_pcie_core_reg_space {
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uint32_t *config_header;
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uint32_t *pcie_pm_cap_base;
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uint32_t *pcie_cap_base;
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uint32_t *pcie_dev_cap_base;
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uint32_t *pcie_dev_ctrl_status;
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uint32_t *pcie_link_cap_base;
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uint32_t *msix_cap_base;
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struct al_pcie_core_aer_regs *aer;
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uint32_t *pcie_sec_ext_cap_base;
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uint32_t *tph_cap_base;
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};
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struct al_pcie_revx_regs {
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struct al_pcie_revx_axi_regs __iomem axi;
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};
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struct al_pcie_rev1_regs {
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struct al_pcie_rev1_axi_regs __iomem axi;
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uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
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(AL_PCIE_AXI_REGS_OFFSET +
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sizeof(struct al_pcie_rev1_axi_regs))) >> 2];
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struct al_pcie_rev1_w_regs __iomem app;
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uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
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(AL_PCIE_REV_1_2_APP_REGS_OFFSET +
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sizeof(struct al_pcie_rev1_w_regs))) >> 2];
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struct al_pcie_core_reg_space_rev_1_2 core_space;
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};
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struct al_pcie_rev2_regs {
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struct al_pcie_rev2_axi_regs __iomem axi;
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uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
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(AL_PCIE_AXI_REGS_OFFSET +
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sizeof(struct al_pcie_rev2_axi_regs))) >> 2];
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struct al_pcie_rev2_w_regs __iomem app;
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uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
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(AL_PCIE_REV_1_2_APP_REGS_OFFSET +
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sizeof(struct al_pcie_rev2_w_regs))) >> 2];
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struct al_pcie_core_reg_space_rev_1_2 core_space;
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};
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struct al_pcie_rev3_regs {
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struct al_pcie_rev3_axi_regs __iomem axi;
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uint32_t reserved1[(AL_PCIE_REV_3_APP_REGS_OFFSET -
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(AL_PCIE_AXI_REGS_OFFSET +
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sizeof(struct al_pcie_rev3_axi_regs))) >> 2];
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struct al_pcie_rev3_w_regs __iomem app;
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uint32_t reserved2[(AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET -
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(AL_PCIE_REV_3_APP_REGS_OFFSET +
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sizeof(struct al_pcie_rev3_w_regs))) >> 2];
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struct al_pcie_rev3_core_reg_space core_space;
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};
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struct al_pcie_axi_ctrl {
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uint32_t *global;
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uint32_t *master_rctl;
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uint32_t *master_arctl;
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uint32_t *master_awctl;
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uint32_t *master_ctl;
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uint32_t *slv_ctl;
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};
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struct al_pcie_axi_ob_ctrl {
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uint32_t *cfg_target_bus;
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uint32_t *cfg_control;
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uint32_t *io_start_l;
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uint32_t *io_start_h;
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uint32_t *io_limit_l;
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uint32_t *io_limit_h;
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uint32_t *io_addr_mask_h; /* Rev 3 only */
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uint32_t *ar_msg_addr_mask_h; /* Rev 3 only */
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uint32_t *aw_msg_addr_mask_h; /* Rev 3 only */
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uint32_t *tgtid_reg_ovrd; /* Rev 2/3 only */
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uint32_t *addr_high_reg_ovrd_value; /* Rev 2/3 only */
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uint32_t *addr_high_reg_ovrd_sel; /* Rev 2/3 only */
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uint32_t *addr_size_replace; /* Rev 2/3 only */
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};
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struct al_pcie_axi_pcie_global {
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uint32_t *conf;
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};
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struct al_pcie_axi_conf {
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uint32_t *zero_lane0;
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uint32_t *zero_lane1;
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uint32_t *zero_lane2;
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uint32_t *zero_lane3;
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uint32_t *zero_lane4;
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uint32_t *zero_lane5;
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uint32_t *zero_lane6;
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uint32_t *zero_lane7;
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};
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struct al_pcie_axi_status {
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uint32_t *lane[AL_MAX_NUM_OF_LANES];
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};
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struct al_pcie_axi_parity {
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uint32_t *en_axi;
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};
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struct al_pcie_axi_ordering {
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uint32_t *pos_cntl;
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};
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struct al_pcie_axi_pre_configuration {
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uint32_t *pcie_core_setup;
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};
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struct al_pcie_axi_init_fc {
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uint32_t *cfg;
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};
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struct al_pcie_axi_attr_ovrd {
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uint32_t *write_msg_ctrl_0;
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uint32_t *write_msg_ctrl_1;
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uint32_t *pf_sel;
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};
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struct al_pcie_axi_pf_axi_attr_ovrd {
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uint32_t *func_ctrl_0;
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uint32_t *func_ctrl_1;
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uint32_t *func_ctrl_2;
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uint32_t *func_ctrl_3;
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uint32_t *func_ctrl_4;
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uint32_t *func_ctrl_5;
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uint32_t *func_ctrl_6;
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uint32_t *func_ctrl_7;
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uint32_t *func_ctrl_8;
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uint32_t *func_ctrl_9;
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};
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struct al_pcie_axi_msg_attr_axuser_table {
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uint32_t *entry_vec;
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};
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struct al_pcie_axi_regs {
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struct al_pcie_axi_ctrl ctrl;
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struct al_pcie_axi_ob_ctrl ob_ctrl;
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struct al_pcie_axi_pcie_global pcie_global;
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struct al_pcie_axi_conf conf;
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struct al_pcie_axi_status status;
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struct al_pcie_axi_parity parity;
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struct al_pcie_axi_ordering ordering;
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struct al_pcie_axi_pre_configuration pre_configuration;
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struct al_pcie_axi_init_fc init_fc;
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struct al_pcie_revx_axi_int_grp_a_axi *int_grp_a;
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/* Rev3 only */
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struct al_pcie_axi_attr_ovrd axi_attr_ovrd;
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struct al_pcie_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];
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struct al_pcie_axi_msg_attr_axuser_table msg_attr_axuser_table;
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};
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struct al_pcie_w_global_ctrl {
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uint32_t *port_init;
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uint32_t *pm_control;
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uint32_t *events_gen[REV3_MAX_NUM_OF_PFS];
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uint32_t *corr_err_sts_int;
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uint32_t *uncorr_err_sts_int;
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uint32_t *sris_kp_counter;
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};
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struct al_pcie_w_soc_int {
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uint32_t *status_0;
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uint32_t *status_1;
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uint32_t *status_2;
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uint32_t *status_3; /* Rev 2/3 only */
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uint32_t *mask_inta_leg_0;
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uint32_t *mask_inta_leg_1;
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uint32_t *mask_inta_leg_2;
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uint32_t *mask_inta_leg_3; /* Rev 2/3 only */
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uint32_t *mask_msi_leg_0;
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uint32_t *mask_msi_leg_1;
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uint32_t *mask_msi_leg_2;
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uint32_t *mask_msi_leg_3; /* Rev 2/3 only */
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};
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struct al_pcie_w_atu {
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uint32_t *in_mask_pair;
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uint32_t *out_mask_pair;
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uint32_t *reg_out_mask; /* Rev 3 only */
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};
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struct al_pcie_w_regs {
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struct al_pcie_w_global_ctrl global_ctrl;
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struct al_pcie_revx_w_debug *debug;
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struct al_pcie_revx_w_ap_user_send_msg *ap_user_send_msg;
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struct al_pcie_w_soc_int soc_int[REV3_MAX_NUM_OF_PFS];
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struct al_pcie_revx_w_cntl_gen *ctrl_gen;
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struct al_pcie_revx_w_parity *parity;
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struct al_pcie_w_atu atu;
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struct al_pcie_revx_w_status_per_func *status_per_func[REV3_MAX_NUM_OF_PFS];
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struct al_pcie_revx_w_int_grp *int_grp_a;
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struct al_pcie_revx_w_int_grp *int_grp_b;
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struct al_pcie_revx_w_int_grp *int_grp_c;
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struct al_pcie_revx_w_int_grp *int_grp_d;
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struct al_pcie_rev3_w_cfg_func_ext *cfg_func_ext; /* Rev 3 only */
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};
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struct al_pcie_regs {
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struct al_pcie_axi_regs axi;
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struct al_pcie_w_regs app;
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struct al_pcie_core_port_regs *port_regs;
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struct al_pcie_core_reg_space core_space[REV3_MAX_NUM_OF_PFS];
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};
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#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP 0
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#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC 4
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#define PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE AL_BIT(17)
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#define PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT 18
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#define PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT 19
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#define PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT 20
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#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK AL_FIELD_MASK(12, 8)
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#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT 8
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#define PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT 9
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#define PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT 16
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#define PCIE_PORT_GEN3_EQ_LF_SHIFT 0
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#define PCIE_PORT_GEN3_EQ_LF_MASK 0x3f
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#define PCIE_PORT_GEN3_EQ_FS_SHIFT 6
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#define PCIE_PORT_GEN3_EQ_FS_MASK (0x3f << PCIE_PORT_GEN3_EQ_FS_SHIFT)
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#define PCIE_PORT_LINK_CTRL_LB_EN_SHIFT 2
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#define PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT 7
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#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK AL_FIELD_MASK(21, 16)
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#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT 16
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#define PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT 31
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#define PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT 0
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/** timer_ctrl_max_func_num register
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* Max physical function number (for example: 0 for 1PF, 3 for 4PFs)
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*/
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#define PCIE_PORT_GEN3_MAX_FUNC_NUM AL_FIELD_MASK(7, 0)
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/* filter_mask_reg_1 register */
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/**
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* SKP Interval Value.
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* The number of symbol times to wait between transmitting SKP ordered sets
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*/
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#define PCIE_FLT_MASK_SKP_INT_VAL_MASK AL_FIELD_MASK(10, 0)
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/*
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* 0: Treat Function MisMatched TLPs as UR
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* 1: Treat Function MisMatched TLPs as Supported
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*/
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#define CX_FLT_MASK_UR_FUNC_MISMATCH AL_BIT(16)
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/*
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* 0: Treat CFG type1 TLPs as UR for EP; Supported for RC
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* 1: Treat CFG type1 TLPs as Supported for EP; UR for RC
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*/
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#define CX_FLT_MASK_CFG_TYPE1_RE_AS_UR AL_BIT(19)
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/*
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* 0: Enforce requester id match for received CPL TLPs.
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* A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
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* cpl_rcvd_ur, cpl_rcvd_ca
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* 1: Mask requester id match for received CPL TLPs
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*/
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#define CX_FLT_MASK_CPL_REQID_MATCH AL_BIT(22)
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/*
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* 0: Enforce function match for received CPL TLPs.
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* A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
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* cpl_rcvd_ur, cpl_rcvd_ca
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* 1: Mask function match for received CPL TLPs
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*/
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#define CX_FLT_MASK_CPL_FUNC_MATCH AL_BIT(23)
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/* vc0_posted_rcv_q_ctrl register */
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#define RADM_PQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
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#define RADM_PQ_HCRD_VC0_SHIFT 12
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/* vc0_non_posted_rcv_q_ctrl register */
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#define RADM_NPQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
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#define RADM_NPQ_HCRD_VC0_SHIFT 12
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/* vc0_comp_rcv_q_ctrl register */
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#define RADM_CPLQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
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#define RADM_CPLQ_HCRD_VC0_SHIFT 12
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/**** iATU, Control Register 1 ****/
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/**
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* When the Address and BAR matching logic in the core indicate that a MEM-I/O
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* transaction matches a BAR in the function corresponding to this value, then
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* address translation proceeds. This check is only performed if the "Function
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* Number Match Enable" bit of the "iATU Control 2 Register" is set
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*/
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#define PCIE_IATU_CR1_FUNC_NUM_MASK AL_FIELD_MASK(24, 20)
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#define PCIE_IATU_CR1_FUNC_NUM_SHIFT 20
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/**** iATU, Control Register 2 ****/
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/** For outbound regions, the Function Number Translation Bypass mode enables
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* taking the function number of the translated TLP from the PCIe core
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* interface and not from the "Function Number" field of CR1.
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* For inbound regions, this bit should be asserted when physical function
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* match mode needs to be enabled
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*/
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#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK AL_BIT(19)
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#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT 19
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/* pcie_dev_ctrl_status register */
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#define PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN AL_BIT(0)
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#define PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN AL_BIT(1)
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#define PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN AL_BIT(2)
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#define PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN AL_BIT(3)
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#define PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK AL_FIELD_MASK(7, 5)
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#define PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT 5
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#define PCIE_PORT_DEV_CTRL_STATUS_MPS_VAL_256 (1 << PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT)
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#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK AL_FIELD_MASK(14, 12)
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#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT 12
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#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256 (1 << PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT)
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/******************************************************************************
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* AER registers
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******************************************************************************/
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/* PCI Express Extended Capability ID */
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#define PCIE_AER_CAP_ID_MASK AL_FIELD_MASK(15, 0)
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#define PCIE_AER_CAP_ID_SHIFT 0
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#define PCIE_AER_CAP_ID_VAL 1
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/* Capability Version */
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#define PCIE_AER_CAP_VER_MASK AL_FIELD_MASK(19, 16)
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#define PCIE_AER_CAP_VER_SHIFT 16
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#define PCIE_AER_CAP_VER_VAL 2
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/* First Error Pointer */
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#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_MASK AL_FIELD_MASK(4, 0)
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#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_SHIFT 0
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/* ECRC Generation Capability */
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#define PCIE_AER_CTRL_STAT_ECRC_GEN_SUPPORTED AL_BIT(5)
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/* ECRC Generation Enable */
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#define PCIE_AER_CTRL_STAT_ECRC_GEN_EN AL_BIT(6)
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/* ECRC Check Capable */
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#define PCIE_AER_CTRL_STAT_ECRC_CHK_SUPPORTED AL_BIT(7)
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/* ECRC Check Enable */
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#define PCIE_AER_CTRL_STAT_ECRC_CHK_EN AL_BIT(8)
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/* Correctable Error Reporting Enable */
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#define PCIE_AER_ROOT_ERR_CMD_CORR_ERR_RPRT_EN AL_BIT(0)
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/* Non-Fatal Error Reporting Enable */
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#define PCIE_AER_ROOT_ERR_CMD_NON_FTL_ERR_RPRT_EN AL_BIT(1)
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/* Fatal Error Reporting Enable */
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#define PCIE_AER_ROOT_ERR_CMD_FTL_ERR_RPRT_EN AL_BIT(2)
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/* ERR_COR Received */
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#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR AL_BIT(0)
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/* Multiple ERR_COR Received */
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#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR_MULTI AL_BIT(1)
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/* ERR_FATAL/NONFATAL Received */
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#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR AL_BIT(2)
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/* Multiple ERR_FATAL/NONFATAL Received */
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#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR_MULTI AL_BIT(3)
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/* First Uncorrectable Fatal */
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#define PCIE_AER_ROOT_ERR_STAT_FIRST_UNCORR_FTL AL_BIT(4)
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/* Non-Fatal Error Messages Received */
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#define PCIE_AER_ROOT_ERR_STAT_NON_FTL_RCVD AL_BIT(5)
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/* Fatal Error Messages Received */
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#define PCIE_AER_ROOT_ERR_STAT_FTL_RCVD AL_BIT(6)
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/* Advanced Error Interrupt Message Number */
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#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_MASK AL_FIELD_MASK(31, 27)
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#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_SHIFT 27
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/* ERR_COR Source Identification */
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#define PCIE_AER_SRC_ID_CORR_ERR_MASK AL_FIELD_MASK(15, 0)
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#define PCIE_AER_SRC_ID_CORR_ERR_SHIFT 0
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/* ERR_FATAL/NONFATAL Source Identification */
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#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_MASK AL_FIELD_MASK(31, 16)
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#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_SHIFT 16
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/* AER message */
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#define PCIE_AER_MSG_REQID_MASK AL_FIELD_MASK(31, 16)
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#define PCIE_AER_MSG_REQID_SHIFT 16
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#define PCIE_AER_MSG_TYPE_MASK AL_FIELD_MASK(15, 8)
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#define PCIE_AER_MSG_TYPE_SHIFT 8
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#define PCIE_AER_MSG_RESERVED AL_FIELD_MASK(7, 1)
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#define PCIE_AER_MSG_VALID AL_BIT(0)
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/* AER message ack */
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#define PCIE_AER_MSG_ACK AL_BIT(0)
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/* AER errors definitions */
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#define AL_PCIE_AER_TYPE_CORR (0x30)
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#define AL_PCIE_AER_TYPE_NON_FATAL (0x31)
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#define AL_PCIE_AER_TYPE_FATAL (0x33)
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/* Requester ID Bus */
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#define AL_PCIE_REQID_BUS_NUM_SHIFT (8)
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/******************************************************************************
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* TPH registers
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******************************************************************************/
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#define PCIE_TPH_NEXT_POINTER AL_FIELD_MASK(31, 20)
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/******************************************************************************
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* Config Header registers
|
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******************************************************************************/
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/**
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* see BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG in core spec
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* Note: valid only for EP mode
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*/
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#define PCIE_BIST_HEADER_TYPE_BASE 0xc
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#define PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK AL_BIT(23)
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/******************************************************************************
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* SRIS KP counters default values
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******************************************************************************/
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#define PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL (0x24)
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#define PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL (0x4B)
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#endif
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