17f3c8f1e3
drift in order to achieve a more stable clock as the tick intervals may vary in the first place. In fact I haven't seen this code kick in when in oneshot-mode so just skip it in that case. - There's no need to explicitly stop the (S)TICK counter in oneshot-mode with every tick as it just won't trigger again with the (S)TICK compare register set to a value in the past (with a wrap-around once every ~195 years of uptime at 1.5 GHz this isn't something we have to worry about in practice). - Given that we'll disable interrupts completely anyway there's no need to enter critical sections. |
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ebus | ||
fhc | ||
include | ||
isa | ||
pci | ||
sbus | ||
sparc64 |