b1ade6ab46
drmcommand-0-0-1-branch of DRI CVS, more return code cleanup, and remove some gratuitous ifdefs. Approved by: des
353 lines
9.7 KiB
C
353 lines
9.7 KiB
C
/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
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*
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* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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*
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* $FreeBSD$
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*/
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#ifndef __RADEON_DRM_H__
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#define __RADEON_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the X server file (radeon_sarea.h)
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*/
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#ifndef __RADEON_SAREA_DEFINES__
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#define __RADEON_SAREA_DEFINES__
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/* What needs to be changed for the current vertex buffer?
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*/
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#define RADEON_UPLOAD_CONTEXT 0x00000001
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#define RADEON_UPLOAD_VERTFMT 0x00000002
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#define RADEON_UPLOAD_LINE 0x00000004
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#define RADEON_UPLOAD_BUMPMAP 0x00000008
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#define RADEON_UPLOAD_MASKS 0x00000010
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#define RADEON_UPLOAD_VIEWPORT 0x00000020
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#define RADEON_UPLOAD_SETUP 0x00000040
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#define RADEON_UPLOAD_TCL 0x00000080
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#define RADEON_UPLOAD_MISC 0x00000100
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#define RADEON_UPLOAD_TEX0 0x00000200
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#define RADEON_UPLOAD_TEX1 0x00000400
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#define RADEON_UPLOAD_TEX2 0x00000800
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#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
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#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
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#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
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#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
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#define RADEON_REQUIRE_QUIESCENCE 0x00010000
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#define RADEON_UPLOAD_ALL 0x0001ffff
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#define RADEON_FRONT 0x1
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#define RADEON_BACK 0x2
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#define RADEON_DEPTH 0x4
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/* Primitive types
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*/
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#define RADEON_POINTS 0x1
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#define RADEON_LINES 0x2
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#define RADEON_LINE_STRIP 0x3
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#define RADEON_TRIANGLES 0x4
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#define RADEON_TRIANGLE_FAN 0x5
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#define RADEON_TRIANGLE_STRIP 0x6
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/* Vertex/indirect buffer size
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*/
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#define RADEON_BUFFER_SIZE 65536
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/* Byte offsets for indirect buffer data
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*/
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#define RADEON_INDEX_PRIM_OFFSET 20
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#define RADEON_HOSTDATA_BLIT_OFFSET 32
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#define RADEON_SCRATCH_REG_OFFSET 32
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/* Keep these small for testing
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*/
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#define RADEON_NR_SAREA_CLIPRECTS 12
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/* There are 2 heaps (local/AGP). Each region within a heap is a
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* minimum of 64k, and there are at most 64 of them per heap.
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*/
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#define RADEON_LOCAL_TEX_HEAP 0
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#define RADEON_AGP_TEX_HEAP 1
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#define RADEON_NR_TEX_HEAPS 2
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#define RADEON_NR_TEX_REGIONS 64
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#define RADEON_LOG_TEX_GRANULARITY 16
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#define RADEON_MAX_TEXTURE_LEVELS 11
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#define RADEON_MAX_TEXTURE_UNITS 3
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#endif /* __RADEON_SAREA_DEFINES__ */
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typedef struct {
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unsigned int red;
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unsigned int green;
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unsigned int blue;
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unsigned int alpha;
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} radeon_color_regs_t;
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typedef struct {
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/* Context state */
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unsigned int pp_misc; /* 0x1c14 */
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unsigned int pp_fog_color;
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unsigned int re_solid_color;
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unsigned int rb3d_blendcntl;
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unsigned int rb3d_depthoffset;
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unsigned int rb3d_depthpitch;
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unsigned int rb3d_zstencilcntl;
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unsigned int pp_cntl; /* 0x1c38 */
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unsigned int rb3d_cntl;
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unsigned int rb3d_coloroffset;
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unsigned int re_width_height;
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unsigned int rb3d_colorpitch;
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unsigned int se_cntl;
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/* Vertex format state */
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unsigned int se_coord_fmt; /* 0x1c50 */
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/* Line state */
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unsigned int re_line_pattern; /* 0x1cd0 */
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unsigned int re_line_state;
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unsigned int se_line_width; /* 0x1db8 */
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/* Bumpmap state */
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unsigned int pp_lum_matrix; /* 0x1d00 */
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unsigned int pp_rot_matrix_0; /* 0x1d58 */
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unsigned int pp_rot_matrix_1;
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/* Mask state */
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unsigned int rb3d_stencilrefmask; /* 0x1d7c */
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unsigned int rb3d_ropcntl;
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unsigned int rb3d_planemask;
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/* Viewport state */
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unsigned int se_vport_xscale; /* 0x1d98 */
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unsigned int se_vport_xoffset;
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unsigned int se_vport_yscale;
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unsigned int se_vport_yoffset;
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unsigned int se_vport_zscale;
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unsigned int se_vport_zoffset;
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/* Setup state */
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unsigned int se_cntl_status; /* 0x2140 */
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#ifdef TCL_ENABLE
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/* TCL state */
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radeon_color_regs_t se_tcl_material_emmissive; /* 0x2210 */
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radeon_color_regs_t se_tcl_material_ambient;
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radeon_color_regs_t se_tcl_material_diffuse;
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radeon_color_regs_t se_tcl_material_specular;
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unsigned int se_tcl_shininess;
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unsigned int se_tcl_output_vtx_fmt;
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unsigned int se_tcl_output_vtx_sel;
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unsigned int se_tcl_matrix_select_0;
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unsigned int se_tcl_matrix_select_1;
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unsigned int se_tcl_ucp_vert_blend_ctl;
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unsigned int se_tcl_texture_proc_ctl;
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unsigned int se_tcl_light_model_ctl;
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unsigned int se_tcl_per_light_ctl[4];
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#endif
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/* Misc state */
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unsigned int re_top_left; /* 0x26c0 */
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unsigned int re_misc;
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} drm_radeon_context_regs_t;
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/* Setup registers for each texture unit
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*/
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typedef struct {
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unsigned int pp_txfilter;
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unsigned int pp_txformat;
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unsigned int pp_txoffset;
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unsigned int pp_txcblend;
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unsigned int pp_txablend;
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unsigned int pp_tfactor;
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unsigned int pp_border_color;
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#ifdef CUBIC_ENABLE
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unsigned int pp_cubic_faces;
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unsigned int pp_cubic_offset[5];
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#endif
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} drm_radeon_texture_regs_t;
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typedef struct {
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unsigned char next, prev;
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unsigned char in_use;
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int age;
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} drm_radeon_tex_region_t;
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typedef struct {
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/* The channel for communication of state information to the kernel
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* on firing a vertex buffer.
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*/
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drm_radeon_context_regs_t context_state;
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drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
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unsigned int dirty;
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unsigned int vertsize;
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unsigned int vc_format;
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/* The current cliprects, or a subset thereof.
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*/
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drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
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unsigned int nbox;
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/* Counters for client-side throttling of rendering clients.
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*/
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unsigned int last_frame;
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unsigned int last_dispatch;
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unsigned int last_clear;
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drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
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int tex_age[RADEON_NR_TEX_HEAPS];
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int ctx_owner;
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} drm_radeon_sarea_t;
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (xf86drmRadeon.h)
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*/
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/* Radeon specific ioctls */
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#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
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#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
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#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
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#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
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#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
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#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
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#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
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#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
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#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
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#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
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#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
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#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
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#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
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#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
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typedef struct drm_radeon_init {
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enum {
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RADEON_INIT_CP = 0x01,
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RADEON_CLEANUP_CP = 0x02
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} func;
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unsigned long sarea_priv_offset;
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int is_pci;
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int cp_mode;
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int agp_size;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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unsigned long fb_offset;
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unsigned long mmio_offset;
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unsigned long ring_offset;
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unsigned long ring_rptr_offset;
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unsigned long buffers_offset;
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unsigned long agp_textures_offset;
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} drm_radeon_init_t;
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typedef struct drm_radeon_cp_stop {
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int flush;
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int idle;
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} drm_radeon_cp_stop_t;
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typedef struct drm_radeon_fullscreen {
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enum {
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RADEON_INIT_FULLSCREEN = 0x01,
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RADEON_CLEANUP_FULLSCREEN = 0x02
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} func;
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} drm_radeon_fullscreen_t;
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#define CLEAR_X1 0
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#define CLEAR_Y1 1
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#define CLEAR_X2 2
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#define CLEAR_Y2 3
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#define CLEAR_DEPTH 4
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typedef union drm_radeon_clear_rect {
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float f[5];
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unsigned int ui[5];
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} drm_radeon_clear_rect_t;
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typedef struct drm_radeon_clear {
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unsigned int flags;
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unsigned int clear_color;
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unsigned int clear_depth;
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unsigned int color_mask;
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unsigned int depth_mask;
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drm_radeon_clear_rect_t *depth_boxes;
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} drm_radeon_clear_t;
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typedef struct drm_radeon_vertex {
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int prim;
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int idx; /* Index of vertex buffer */
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int count; /* Number of vertices in buffer */
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int discard; /* Client finished with buffer? */
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} drm_radeon_vertex_t;
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typedef struct drm_radeon_indices {
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int prim;
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int idx;
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int start;
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int end;
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int discard; /* Client finished with buffer? */
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} drm_radeon_indices_t;
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typedef struct drm_radeon_tex_image {
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unsigned int x, y; /* Blit coordinates */
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unsigned int width, height;
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const void *data;
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} drm_radeon_tex_image_t;
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typedef struct drm_radeon_texture {
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int offset;
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int pitch;
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int format;
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int width; /* Texture image coordinates */
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int height;
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drm_radeon_tex_image_t *image;
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} drm_radeon_texture_t;
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typedef struct drm_radeon_stipple {
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unsigned int *mask;
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} drm_radeon_stipple_t;
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typedef struct drm_radeon_indirect {
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int idx;
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int start;
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int end;
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int discard;
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} drm_radeon_indirect_t;
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#endif
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