b624ef0a8e
These controllers seem to have the same feature of AR813x/AR815x and improved RSS support(4 TX queues and 8 RX queues). alc(4) supports all hardware features except RSS. I didn't implement RX checksum offloading for AR816x/AR817x just because I couldn't get confirmation from the Vendor whether AR816x/AR817x corrected its predecessor's RX checksum offloading bug on fragmented packets. This change adds supports for the following controllers. o AR8161 PCIe Gigabit Ethernet controller o AR8162 PCIe Fast Ethernet controller o AR8171 PCIe Gigabit Ethernet controller o AR8172 PCIe Fast Ethernet controller o Killer E2200 Gigabit Ethernet controller Tested by: Many Relnotes: yes MFC after: 2 weeks HW donated by: Qualcomm Atheros Communications, Inc.
287 lines
8.0 KiB
C
287 lines
8.0 KiB
C
/*-
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* Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_ALCVAR_H
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#define _IF_ALCVAR_H
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#define ALC_TX_RING_CNT 256
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#define ALC_TX_RING_ALIGN sizeof(struct tx_desc)
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#define ALC_RX_RING_CNT 256
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#define ALC_RX_RING_ALIGN sizeof(struct rx_desc)
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#define ALC_RX_BUF_ALIGN 4
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#define ALC_RR_RING_CNT ALC_RX_RING_CNT
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#define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc)
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#define ALC_CMB_ALIGN 8
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#define ALC_SMB_ALIGN 8
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#define ALC_TSO_MAXSEGSIZE 4096
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#define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
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#define ALC_MAXTXSEGS 35
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#define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
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#define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32)
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#define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
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/* Water mark to kick reclaiming Tx buffers. */
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#define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10)
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/*
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* AR816x controllers support up to 16 messages but this driver
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* uses single message.
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*/
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#define ALC_MSI_MESSAGES 1
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#define ALC_MSIX_MESSAGES 1
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#define ALC_TX_RING_SZ \
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(sizeof(struct tx_desc) * ALC_TX_RING_CNT)
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#define ALC_RX_RING_SZ \
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(sizeof(struct rx_desc) * ALC_RX_RING_CNT)
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#define ALC_RR_RING_SZ \
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(sizeof(struct rx_rdesc) * ALC_RR_RING_CNT)
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#define ALC_CMB_SZ (sizeof(struct cmb))
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#define ALC_SMB_SZ (sizeof(struct smb))
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#define ALC_PROC_MIN 16
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#define ALC_PROC_MAX (ALC_RX_RING_CNT - 1)
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#define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4)
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/*
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* The number of bits reserved for MSS in AR813x/AR815x controllers
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* are 13 bits. This limits the maximum interface MTU size in TSO
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* case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper
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* stack should not generate TCP segments with MSS greater than the
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* limit. Also Atheros says that maximum MTU for TSO is 6KB.
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*/
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#define ALC_TSO_MTU (6 * 1024)
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struct alc_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct rx_desc *rx_desc;
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};
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struct alc_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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};
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struct alc_ring_data {
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struct tx_desc *alc_tx_ring;
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bus_addr_t alc_tx_ring_paddr;
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struct rx_desc *alc_rx_ring;
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bus_addr_t alc_rx_ring_paddr;
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struct rx_rdesc *alc_rr_ring;
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bus_addr_t alc_rr_ring_paddr;
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struct cmb *alc_cmb;
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bus_addr_t alc_cmb_paddr;
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struct smb *alc_smb;
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bus_addr_t alc_smb_paddr;
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};
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struct alc_chain_data {
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bus_dma_tag_t alc_parent_tag;
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bus_dma_tag_t alc_buffer_tag;
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bus_dma_tag_t alc_tx_tag;
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struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT];
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bus_dma_tag_t alc_rx_tag;
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struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT];
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bus_dma_tag_t alc_tx_ring_tag;
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bus_dmamap_t alc_tx_ring_map;
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bus_dma_tag_t alc_rx_ring_tag;
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bus_dmamap_t alc_rx_ring_map;
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bus_dma_tag_t alc_rr_ring_tag;
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bus_dmamap_t alc_rr_ring_map;
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bus_dmamap_t alc_rx_sparemap;
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bus_dma_tag_t alc_cmb_tag;
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bus_dmamap_t alc_cmb_map;
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bus_dma_tag_t alc_smb_tag;
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bus_dmamap_t alc_smb_map;
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int alc_tx_prod;
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int alc_tx_cons;
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int alc_tx_cnt;
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int alc_rx_cons;
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int alc_rr_cons;
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int alc_rxlen;
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struct mbuf *alc_rxhead;
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struct mbuf *alc_rxtail;
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struct mbuf *alc_rxprev_tail;
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};
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struct alc_hw_stats {
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/* Rx stats. */
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uint32_t rx_frames;
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uint32_t rx_bcast_frames;
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uint32_t rx_mcast_frames;
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uint32_t rx_pause_frames;
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uint32_t rx_control_frames;
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uint32_t rx_crcerrs;
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uint32_t rx_lenerrs;
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uint64_t rx_bytes;
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uint32_t rx_runts;
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uint32_t rx_fragments;
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uint32_t rx_pkts_64;
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uint32_t rx_pkts_65_127;
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uint32_t rx_pkts_128_255;
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uint32_t rx_pkts_256_511;
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uint32_t rx_pkts_512_1023;
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uint32_t rx_pkts_1024_1518;
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uint32_t rx_pkts_1519_max;
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uint32_t rx_pkts_truncated;
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uint32_t rx_fifo_oflows;
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uint32_t rx_rrs_errs;
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uint32_t rx_alignerrs;
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uint64_t rx_bcast_bytes;
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uint64_t rx_mcast_bytes;
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uint32_t rx_pkts_filtered;
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/* Tx stats. */
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uint32_t tx_frames;
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uint32_t tx_bcast_frames;
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uint32_t tx_mcast_frames;
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uint32_t tx_pause_frames;
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uint32_t tx_excess_defer;
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uint32_t tx_control_frames;
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uint32_t tx_deferred;
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uint64_t tx_bytes;
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uint32_t tx_pkts_64;
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uint32_t tx_pkts_65_127;
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uint32_t tx_pkts_128_255;
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uint32_t tx_pkts_256_511;
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uint32_t tx_pkts_512_1023;
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uint32_t tx_pkts_1024_1518;
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uint32_t tx_pkts_1519_max;
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uint32_t tx_single_colls;
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uint32_t tx_multi_colls;
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uint32_t tx_late_colls;
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uint32_t tx_excess_colls;
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uint32_t tx_abort;
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uint32_t tx_underrun;
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uint32_t tx_desc_underrun;
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uint32_t tx_lenerrs;
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uint32_t tx_pkts_truncated;
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uint64_t tx_bcast_bytes;
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uint64_t tx_mcast_bytes;
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};
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struct alc_ident {
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uint16_t vendorid;
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uint16_t deviceid;
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uint32_t max_framelen;
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const char *name;
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};
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/*
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* Software state per device.
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*/
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struct alc_softc {
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struct ifnet *alc_ifp;
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device_t alc_dev;
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device_t alc_miibus;
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struct resource *alc_res[1];
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struct resource_spec *alc_res_spec;
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struct resource *alc_irq[ALC_MSI_MESSAGES];
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struct resource_spec *alc_irq_spec;
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void *alc_intrhand[ALC_MSI_MESSAGES];
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struct alc_ident *alc_ident;
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int alc_rev;
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int alc_chip_rev;
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int alc_phyaddr;
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uint8_t alc_eaddr[ETHER_ADDR_LEN];
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uint32_t alc_dma_rd_burst;
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uint32_t alc_dma_wr_burst;
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uint32_t alc_rcb;
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int alc_expcap;
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int alc_pmcap;
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int alc_flags;
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#define ALC_FLAG_PCIE 0x0001
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#define ALC_FLAG_PCIX 0x0002
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#define ALC_FLAG_MSI 0x0004
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#define ALC_FLAG_MSIX 0x0008
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#define ALC_FLAG_PM 0x0010
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#define ALC_FLAG_FASTETHER 0x0020
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#define ALC_FLAG_JUMBO 0x0040
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#define ALC_FLAG_CMB_BUG 0x0100
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#define ALC_FLAG_SMB_BUG 0x0200
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#define ALC_FLAG_L0S 0x0400
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#define ALC_FLAG_L1S 0x0800
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#define ALC_FLAG_APS 0x1000
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#define ALC_FLAG_AR816X_FAMILY 0x2000
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#define ALC_FLAG_LINK_WAR 0x4000
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#define ALC_FLAG_LINK 0x8000
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struct callout alc_tick_ch;
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struct alc_hw_stats alc_stats;
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struct alc_chain_data alc_cdata;
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struct alc_ring_data alc_rdata;
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int alc_if_flags;
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int alc_watchdog_timer;
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int alc_process_limit;
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volatile int alc_morework;
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int alc_int_rx_mod;
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int alc_int_tx_mod;
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int alc_buf_size;
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struct task alc_int_task;
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struct taskqueue *alc_tq;
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struct mtx alc_mtx;
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};
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/* Register access macros. */
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#define CSR_WRITE_4(_sc, reg, val) \
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bus_write_4((_sc)->alc_res[0], (reg), (val))
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#define CSR_WRITE_2(_sc, reg, val) \
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bus_write_2((_sc)->alc_res[0], (reg), (val))
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#define CSR_WRITE_1(_sc, reg, val) \
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bus_write_1((_sc)->alc_res[0], (reg), (val))
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#define CSR_READ_2(_sc, reg) \
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bus_read_2((_sc)->alc_res[0], (reg))
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#define CSR_READ_4(_sc, reg) \
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bus_read_4((_sc)->alc_res[0], (reg))
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#define ALC_RXCHAIN_RESET(_sc) \
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do { \
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(_sc)->alc_cdata.alc_rxhead = NULL; \
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(_sc)->alc_cdata.alc_rxtail = NULL; \
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(_sc)->alc_cdata.alc_rxprev_tail = NULL; \
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(_sc)->alc_cdata.alc_rxlen = 0; \
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} while (0)
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#define ALC_LOCK(_sc) mtx_lock(&(_sc)->alc_mtx)
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#define ALC_UNLOCK(_sc) mtx_unlock(&(_sc)->alc_mtx)
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#define ALC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->alc_mtx, MA_OWNED)
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#define ALC_TX_TIMEOUT 5
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#define ALC_RESET_TIMEOUT 100
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#define ALC_TIMEOUT 1000
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#define ALC_PHY_TIMEOUT 1000
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#endif /* _IF_ALCVAR_H */
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