93ef7ecb75
check which variant we are on, and if it is a VFPv3 or v4, and has 32 double registers we save these. This fixes VFP support on Raspberry Pi. While here clean fmrx and fmxr up to use the register names from vfp.h as opposed to the raw register names.
132 lines
5.3 KiB
C
132 lines
5.3 KiB
C
/*
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* Copyright (c) 2012 Mark Tinguely
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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* $FreeBSD$
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*/
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#ifndef _MACHINE__VFP_H_
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#define _MACHINE__VFP_H_
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/* fpsid, fpscr, fpexc are defined in the newer gas */
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#define VFPSID cr0
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#define VFPSCR cr1
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#define VMVFR1 cr6
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#define VMVFR0 cr7
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#define VFPEXC cr8
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#define VFPINST cr9 /* vfp 1 and 2 except instruction */
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#define VFPINST2 cr10 /* vfp 2? */
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/* VFPSID */
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#define VFPSID_IMPLEMENTOR_OFF 24
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#define VFPSID_IMPLEMENTOR_MASK (0xff000000)
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#define VFPSID_HARDSOFT_IMP (0x00800000)
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#define VFPSID_SINGLE_PREC 20 /* version 1 and 2 */
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#define VFPSID_SUBVERSION_OFF 16
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#define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
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#define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
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#define VFP_ARCH1 0x0
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#define VFP_ARCH2 0x1
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#define VFP_ARCH3 0x2
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#define VFPSID_PARTNUMBER_OFF 8
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#define VFPSID_PARTNUMBER_MASK (0x0000ff00)
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#define VFPSID_VARIANT_OFF 4
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#define VFPSID_VARIANT_MASK (0x000000f0)
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#define VFPSID_REVISION_MASK 0x0f
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/* VFPSCR */
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#define VFPSCR_CC_N (0x80000000) /* comparison less than */
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#define VFPSCR_CC_Z (0x40000000) /* comparison equal */
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#define VFPSCR_CC_C (0x20000000) /* comparison = > unordered */
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#define VFPSCR_CC_V (0x10000000) /* comparison unordered */
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#define VFPSCR_QC (0x08000000) /* saturation cululative */
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#define VFPSCR_DN (0x02000000) /* default NaN enable */
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#define VFPSCR_FZ (0x01000000) /* flush to zero enabled */
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#define VFPSCR_RMODE_OFF 22 /* rounding mode offset */
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#define VFPSCR_RMODE_MASK (0x00c00000) /* rounding mode mask */
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#define VFPSCR_RMODE_RN (0x00000000) /* round nearest */
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#define VFPSCR_RMODE_RPI (0x00400000) /* round to plus infinity */
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#define VFPSCR_RMODE_RNI (0x00800000) /* round to neg infinity */
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#define VFPSCR_RMODE_RM (0x00c00000) /* round to zero */
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#define VFPSCR_STRIDE_OFF 20 /* vector stride -1 */
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#define VFPSCR_STRIDE_MASK (0x00300000)
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#define VFPSCR_LEN_OFF 16 /* vector length -1 */
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#define VFPSCR_LEN_MASK (0x00070000)
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#define VFPSCR_IDE (0x00008000) /* input subnormal exc enable */
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#define VFPSCR_IXE (0x00001000) /* inexact exception enable */
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#define VFPSCR_UFE (0x00000800) /* underflow exception enable */
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#define VFPSCR_OFE (0x00000400) /* overflow exception enable */
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#define VFPSCR_DNZ (0x00000200) /* div by zero exception en */
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#define VFPSCR_IOE (0x00000100) /* invalid op exec enable */
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#define VFPSCR_IDC (0x00000080) /* input subnormal cumul */
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#define VFPSCR_IXC (0x00000010) /* Inexact cumulative flag */
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#define VFPSCR_UFC (0x00000008) /* underflow cumulative flag */
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#define VFPSCR_OFC (0x00000004) /* overflow cumulative flag */
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#define VFPSCR_DZC (0x00000002) /* division by zero flag */
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#define VFPSCR_IOC (0x00000001) /* invalid operation cumul */
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/* VFPEXC */
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#define VFPEXC_EX (0x80000000) /* exception v1 v2 */
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#define VFPEXC_EN (0x40000000) /* vfp enable */
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/* version 3 registers */
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/* VMVFR0 */
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#define VMVFR0_RM_OFF 28
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#define VMVFR0_RM_MASK (0xf0000000) /* VFP rounding modes */
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#define VMVFR0_SV_OFF 24
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#define VMVFR0_SV_MASK (0x0f000000) /* VFP short vector supp */
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#define VMVFR0_SR_OFF 20
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#define VMVFR0_SR (0x00f00000) /* VFP hw sqrt supp */
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#define VMVFR0_D_OFF 16
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#define VMVFR0_D_MASK (0x000f0000) /* VFP divide supp */
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#define VMVFR0_TE_OFF 12
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#define VMVFR0_TE_MASK (0x0000f000) /* VFP trap exception supp */
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#define VMVFR0_DP_OFF 8
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#define VMVFR0_DP_MASK (0x00000f00) /* VFP double prec support */
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#define VMVFR0_SP_OFF 4
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#define VMVFR0_SP_MASK (0x000000f0) /* VFP single prec support */
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#define VMVFR0_RB_MASK (0x0000000f) /* VFP 64 bit media support */
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/* VMVFR1 */
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#define VMVFR1_SP_OFF 16
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#define VMVFR1_SP_MASK (0x000f0000) /* Neon single prec support */
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#define VMVFR1_I_OFF 12
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#define VMVFR1_I_MASK (0x0000f000) /* Neon integer support */
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#define VMVFR1_LS_OFF 8
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#define VMVFR1_LS_MASK (0x00000f00) /* Neon ld/st instr support */
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#define VMVFR1_DN_OFF 4
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#define VMVFR1_DN_MASK (0x000000f0) /* Neon prop NaN support */
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#define VMVFR1_FZ_MASK (0x0000000f) /* Neon denormal arith supp */
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#define COPROC10 (0x3 << 20)
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#define COPROC11 (0x3 << 22)
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void vfp_init(void);
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#endif
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