2744a0b69b
The actual cache line size has always been 64 bytes. The 128 number arose as an optimization for Core 2 era Intel processors. By default (configurable in BIOS), these CPUs would prefetch adjacent cache lines unintelligently. Newer CPUs prefetch more intelligently. The latest Core 2 era CPU was introduced in September 2008 (Xeon 7400 series, "Dunnington"). If you are still using one of these CPUs, especially in a multi-socket configuration, consider locating the "adjacent cache line prefetch" option in BIOS and disabling it. Reported by: mjg Reviewed by: np Discussed with: jhb Sponsored by: Dell EMC Isilon |
||
---|---|---|
.. | ||
pc | ||
xen | ||
_align.h | ||
_bus.h | ||
_inttypes.h | ||
_limits.h | ||
_stdint.h | ||
_types.h | ||
acpica_machdep.h | ||
apm_bios.h | ||
apm_segments.h | ||
asm.h | ||
asmacros.h | ||
atomic.h | ||
bootinfo.h | ||
bus_dma.h | ||
bus.h | ||
clock.h | ||
counter.h | ||
cpu.h | ||
cpufunc.h | ||
cputypes.h | ||
cserial.h | ||
db_machdep.h | ||
dump.h | ||
efi.h | ||
elan_mmcr.h | ||
elf.h | ||
endian.h | ||
exec.h | ||
fdt.h | ||
float.h | ||
floatingpoint.h | ||
frame.h | ||
gdb_machdep.h | ||
ieeefp.h | ||
if_wl_wavelan.h | ||
in_cksum.h | ||
intr_machdep.h | ||
ioctl_bt848.h | ||
ioctl_meteor.h | ||
iodev.h | ||
kdb.h | ||
limits.h | ||
md_var.h | ||
memdev.h | ||
metadata.h | ||
minidump.h | ||
mp_watchdog.h | ||
nexusvar.h | ||
npx.h | ||
ofw_machdep.h | ||
param.h | ||
pcaudioio.h | ||
pcb_ext.h | ||
pcb.h | ||
pci_cfgreg.h | ||
pcpu.h | ||
perfmon.h | ||
pmap.h | ||
pmc_mdep.h | ||
ppireg.h | ||
proc.h | ||
profile.h | ||
psl.h | ||
ptrace.h | ||
pvclock.h | ||
reg.h | ||
reloc.h | ||
resource.h | ||
runq.h | ||
segments.h | ||
setjmp.h | ||
sf_buf.h | ||
sigframe.h | ||
signal.h | ||
smapi.h | ||
smp.h | ||
speaker.h | ||
specialreg.h | ||
stack.h | ||
stdarg.h | ||
sysarch.h | ||
timerreg.h | ||
trap.h | ||
tss.h | ||
ucontext.h | ||
varargs.h | ||
vdso.h | ||
vm86.h | ||
vm.h | ||
vmparam.h | ||
xbox.h |