20f0285d8c
PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers
hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)
hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
normally they're enabled either by FSBL or after programming
FPGA through devcfg(4)
319 lines
14 KiB
C
319 lines
14 KiB
C
/*-
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* Copyright (c) 2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Defines for Zynq-7000 SLCR registers.
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*
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* Most of these registers are initialized by the First Stage Boot
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* Loader and are not modified by the kernel.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585. SLCR register definitions
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* are in appendix B.28.
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*/
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#ifndef _ZY7_SLCR_H_
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#define _ZY7_SLCR_H_
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#define ZY7_SCLR_SCL 0x0000
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#define ZY7_SLCR_LOCK 0x0004
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#define ZY7_SLCR_LOCK_MAGIC 0x767b
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#define ZY7_SLCR_UNLOCK 0x0008
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#define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
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#define ZY7_SLCR_LOCKSTA 0x000c
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/* PLL controls. */
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#define ZY7_SLCR_ARM_PLL_CTRL 0x0100
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#define ZY7_SLCR_DDR_PLL_CTRL 0x0104
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#define ZY7_SLCR_IO_PLL_CTRL 0x0108
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#define ZY7_SLCR_PLL_CTRL_RESET (1<<0)
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#define ZY7_SLCR_PLL_CTRL_PWRDWN (1<<1)
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#define ZY7_SLCR_PLL_CTRL_BYPASS_QUAL (1<<3)
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#define ZY7_SLCR_PLL_CTRL_BYPASS_FORCE (1<<4)
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#define ZY7_SLCR_PLL_CTRL_FDIV_SHIFT 12
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#define ZY7_SLCR_PLL_CTRL_FDIV_MASK (0x7f<<12)
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#define ZY7_SLCR_PLL_STATUS 0x010c
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#define ZY7_SLCR_PLL_STAT_ARM_PLL_LOCK (1<<0)
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#define ZY7_SLCR_PLL_STAT_DDR_PLL_LOCK (1<<1)
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#define ZY7_SLCR_PLL_STAT_IO_PLL_LOCK (1<<2)
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#define ZY7_SLCR_PLL_STAT_ARM_PLL_STABLE (1<<3)
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#define ZY7_SLCR_PLL_STAT_DDR_PLL_STABLE (1<<4)
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#define ZY7_SLCR_PLL_STAT_IO_PLL_STABLE (1<<5)
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#define ZY7_SLCR_ARM_PLL_CFG 0x0110
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#define ZY7_SLCR_DDR_PLL_CFG 0x0114
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#define ZY7_SLCR_IO_PLL_CFG 0x0118
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#define ZY7_SLCR_PLL_CFG_RES_SHIFT 4
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#define ZY7_SLCR_PLL_CFG_RES_MASK (0xf<<4)
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#define ZY7_SLCR_PLL_CFG_PLL_CP_SHIFT 8
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#define ZY7_SLCR_PLL_CFG_PLL_CP_MASK (0xf<<8)
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#define ZY7_SLCR_PLL_CFG_LOCK_CNT_SHIFT 12
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#define ZY7_SLCR_PLL_CFG_LOCK_CNT_MASK (0x3ff<<12)
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/* Clock controls. */
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#define ZY7_SLCR_ARM_CLK_CTRL 0x0120
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#define ZY7_SLCR_ARM_CLK_CTRL_CPU_PERI_CLKACT (1<<28)
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#define ZY7_SLCR_ARM_CLK_CTRL_CPU_1XCLKACT (1<<27)
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#define ZY7_SLCR_ARM_CLK_CTRL_CPU_2XCLKACT (1<<26)
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#define ZY7_SLCR_ARM_CLK_CTRL_CPU_3OR2XCLKACT (1<<25)
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#define ZY7_SLCR_ARM_CLK_CTRL_CPU_6OR4XCLKACT (1<<24)
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#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_MASK (3<<4)
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#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_ARM_PLL (0<<4)
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#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_DDR_PLL (2<<4)
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#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_IO_PLL (3<<4)
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#define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_SHIFT 8
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#define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_MASK (0x3f<<8)
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#define ZY7_SLCR_DDR_CLK_CTRL 0x0124
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#define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_SHIFT 26
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#define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_MASK (0x3f<<26)
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#define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_SHIFT 20
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#define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_MASK (0x3f<<20)
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#define ZY7_SLCR_DDR_CLK_CTRL_2XCLKACT (1<<1)
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#define ZY7_SLCR_DDR_CLK_CTRL_3XCLKACT (1<<0)
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#define ZY7_SLCR_DCI_CLK_CTRL 0x0128
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#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_SHIFT 20
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#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_MASK (0x3f<<20)
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#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_SHIFT 8
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#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_MASK (0x3f<<8)
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#define ZY7_SLCR_DCI_CLK_CTRL_CLKACT (1<<0)
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#define ZY7_SLCR_APER_CLK_CTRL 0x012c /* amba periph clk ctrl */
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#define ZY7_SLCR_APER_CLK_CTRL_SMC_CPU_1XCLKACT (1<<24)
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#define ZY7_SLCR_APER_CLK_CTRL_LQSPI_CPU_1XCLKACT (1<<23)
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#define ZY7_SLCR_APER_CLK_CTRL_GPIO_CPU_1XCLKACT (1<<22)
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#define ZY7_SLCR_APER_CLK_CTRL_UART1_CPU_1XCLKACT (1<<21)
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#define ZY7_SLCR_APER_CLK_CTRL_UART0_CPU_1XCLKACT (1<<20)
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#define ZY7_SLCR_APER_CLK_CTRL_I2C1_CPU_1XCLKACT (1<<19)
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#define ZY7_SLCR_APER_CLK_CTRL_I2C0_CPU_1XCLKACT (1<<18)
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#define ZY7_SLCR_APER_CLK_CTRL_CAN1_CPU_1XCLKACT (1<<17)
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#define ZY7_SLCR_APER_CLK_CTRL_CAN0_CPU_1XCLKACT (1<<16)
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#define ZY7_SLCR_APER_CLK_CTRL_SPI1_CPU_1XCLKACT (1<<15)
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#define ZY7_SLCR_APER_CLK_CTRL_SPI0_CPU_1XCLKACT (1<<14)
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#define ZY7_SLCR_APER_CLK_CTRL_SDI1_CPU_1XCLKACT (1<<11)
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#define ZY7_SLCR_APER_CLK_CTRL_SDI0_CPU_1XCLKACT (1<<10)
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#define ZY7_SLCR_APER_CLK_CTRL_GEM1_CPU_1XCLKACT (1<<7)
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#define ZY7_SLCR_APER_CLK_CTRL_GEM0_CPU_1XCLKACT (1<<6)
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#define ZY7_SLCR_APER_CLK_CTRL_USB1_CPU_1XCLKACT (1<<3)
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#define ZY7_SLCR_APER_CLK_CTRL_USB0_CPU_1XCLKACT (1<<2)
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#define ZY7_SLCR_APER_CLK_CTRL_DMA_CPU_1XCLKACT (1<<0)
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#define ZY7_SLCR_USB0_CLK_CTRL 0x0130
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#define ZY7_SLCR_USB1_CLK_CTRL 0x0134
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#define ZY7_SLCR_GEM0_RCLK_CTRL 0x0138
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#define ZY7_SLCR_GEM1_RCLK_CTRL 0x013c
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#define ZY7_SLCR_GEM0_CLK_CTRL 0x0140
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#define ZY7_SLCR_GEM1_CLK_CTRL 0x0144
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#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK (0x3f<<20)
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#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT 20
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#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX 0x3f
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#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (0x3f<<8)
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#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT 8
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#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX 0x3f
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#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<4)
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#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL (0<<4)
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#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_ARM_PLL (2<<4)
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#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_DDR_PLL (3<<4)
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#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_EMIO_CLK (4<<4)
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#define ZY7_SLCR_GEM_CLK_CTRL_CLKACT 1
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#define ZY7_SLCR_SMC_CLK_CTRL 0x0148
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#define ZY7_SLCR_LQSPI_CLK_CTRL 0x014c
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#define ZY7_SLCR_SDIO_CLK_CTRL 0x0150
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#define ZY7_SLCR_UART_CLK_CTRL 0x0154
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#define ZY7_SLCR_SPI_CLK_CTRL 0x0158
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#define ZY7_SLCR_CAN_CLK_CTRL 0x015c
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#define ZY7_SLCR_CAN_MIOCLK_CTRL 0x0160
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#define ZY7_SLCR_DBG_CLK_CTRL 0x0164
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#define ZY7_SLCR_PCAP_CLK_CTRL 0x0168
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#define ZY7_SLCR_TOPSW_CLK_CTRL 0x016c /* central intercnn clk ctrl */
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#define ZY7_SLCR_FPGA_CLK_CTRL(unit) (0x0170 + 0x10*(unit))
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#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT 20
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#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK (0x3f << 20)
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#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT 8
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#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (0x3f << 8)
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#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX 0x3f
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#define ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT 4
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#define ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK (3 << 4)
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#define ZY7_SLCR_FPGA_THR_CTRL(unit) (0x0174 + 0x10*(unit))
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#define ZY7_SLCR_FPGA_THR_CTRL_CNT_RST (1 << 1)
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#define ZY7_SLCR_FPGA_THR_CTRL_CPU_START (1 << 0)
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#define ZY7_SLCR_FPGA_THR_CNT(unit) (0x0178 + 0x10*(unit))
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#define ZY7_SLCR_FPGA_THR_STA(unit) (0x017c + 0x10*(unit))
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#define ZY7_SLCR_CLK_621_TRUE 0x01c4 /* cpu clock ratio mode */
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/* Reset controls. */
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#define ZY7_SLCR_PSS_RST_CTRL 0x0200
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#define ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET (1<<0)
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#define ZY7_SLCR_DDR_RST_CTRL 0x0204
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#define ZY7_SLCR_TOPSW_RST_CTRL 0x0208
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#define ZY7_SLCR_DMAC_RST_CTRL 0x020c
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#define ZY7_SLCR_USB_RST_CTRL 0x0210
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#define ZY7_SLCR_GEM_RST_CTRL 0x0214
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#define ZY7_SLCR_SDIO_RST_CTRL 0x0218
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#define ZY7_SLCR_SPI_RST_CTRL 0x021c
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#define ZY7_SLCR_CAN_RST_CTRL 0x0220
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#define ZY7_SLCR_I2C_RST_CTRL 0x0224
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#define ZY7_SLCR_UART_RST_CTRL 0x0228
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#define ZY7_SLCR_GPIO_RST_CTRL 0x022c
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#define ZY7_SLCR_LQSPI_RST_CTRL 0x0230
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#define ZY7_SLCR_SMC_RST_CTRL 0x0234
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#define ZY7_SLCR_OCM_RST_CTRL 0x0238
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#define ZY7_SLCR_DEVCI_RST_CTRL 0x023c
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#define ZY7_SLCR_FPGA_RST_CTRL 0x0240
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#define ZY7_SLCR_FPGA_RST_CTRL_FPGA3_OUT_RST (1<<3)
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#define ZY7_SLCR_FPGA_RST_CTRL_FPGA2_OUT_RST (1<<2)
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#define ZY7_SLCR_FPGA_RST_CTRL_FPGA1_OUT_RST (1<<1)
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#define ZY7_SLCR_FPGA_RST_CTRL_FPGA0_OUT_RST (1<<0)
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#define ZY7_SLCR_FPGA_RST_CTRL_RST_ALL 0xf
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#define ZY7_SLCR_A9_CPU_RST_CTRL 0x0244
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#define ZY7_SLCR_RS_AWDT_CTRL 0x024c
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#define ZY7_SLCR_REBOOT_STAT 0x0258
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#define ZY7_SLCR_REBOOT_STAT_STATE_MASK (0xff<<24)
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#define ZY7_SLCR_REBOOT_STAT_POR (1<<22)
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#define ZY7_SLCR_REBOOT_STAT_SRST_B (1<<21)
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#define ZY7_SLCR_REBOOT_STAT_DBG_RST (1<<20)
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#define ZY7_SLCR_REBOOT_STAT_SLC_RST (1<<19)
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#define ZY7_SLCR_REBOOT_STAT_AWDT1_RST (1<<18)
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#define ZY7_SLCR_REBOOT_STAT_AWDT0_RST (1<<17)
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#define ZY7_SLCR_REBOOT_STAT_SWDT_RST (1<<16)
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#define ZY7_SLCR_REBOOT_STAT_BOOTROM_ERR_CODE_MASK (0xffff)
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#define ZY7_SLCR_BOOT_MODE 0x025c
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#define ZY7_SLCR_BOOT_MODE_PLL_BYPASS (1<<4)
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#define ZY7_SLCR_BOOT_MODE_JTAG_INDEP (1<<3)
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#define ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK 7
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#define ZY7_SLCR_BOOT_MODE_BOOTDEV_JTAG 0
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#define ZY7_SLCR_BOOT_MODE_BOOTDEV_QUAD_SPI 1
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#define ZY7_SLCR_BOOT_MODE_BOOTDEV_NOR 2
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#define ZY7_SLCR_BOOT_MODE_BOOTDEV_NAND 4
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#define ZY7_SLCR_BOOT_MODE_BOOTDEV_SD_CARD 5
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#define ZY7_SLCR_APU_CTRL 0x0300
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#define ZY7_SLCR_WDT_CLK_SEL 0x0304
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#define ZY7_SLCR_PSS_IDCODE 0x0530
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#define ZY7_SLCR_PSS_IDCODE_REVISION_MASK (0xf<<28)
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#define ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT 28
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#define ZY7_SLCR_PSS_IDCODE_FAMILY_MASK (0x7f<<21)
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#define ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT 21
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#define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK (0xf<<17)
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#define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT 17
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#define ZY7_SLCR_PSS_IDCODE_DEVICE_MASK (0x1f<<12)
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#define ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT 12
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#define ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK (0x7ff<<1)
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#define ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT 1
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#define ZY7_SLCR_DDR_URGENT 0x0600
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#define ZY7_SLCR_DDR_CAL_START 0x060c
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#define ZY7_SLCR_DDR_REF_START 0x0614
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#define ZY7_SLCR_DDR_CMD_STA 0x0618
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#define ZY7_SLCR_DDR_URGENT_SEL 0x061c
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#define ZY7_SLCR_DDR_DFI_STATUS 0x0620
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/* MIO Pin controls */
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#define ZY7_SLCR_MIO_PIN(n) (0x0700+(n)*4) /* 0-53 */
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#define ZY7_SLCR_MIO_PIN_RCVR_DIS (1<<13)
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#define ZY7_SLCR_MIO_PIN_PULLUP_EN (1<<12)
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#define ZY7_SLCR_MIO_PIN_IO_TYPE_MASK (7<<9)
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#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVTTL (0<<9)
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#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS18 (1<<9)
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#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS25 (2<<9)
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#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS33 (3<<9)
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#define ZY7_SLCR_MIO_PIN_IO_TYPE_HSTL (4<<9)
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#define ZY7_SLCR_MIO_PIN_L2_SEL_MASK (3<<3)
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#define ZY7_SLCR_MIO_PIN_L2_SEL_L3_MUX (0<<3)
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#define ZY7_SLCR_MIO_PIN_L2_SEL_SRAM_NOR_CS0 (1<<3)
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#define ZY7_SLCR_MIO_PIN_L2_SEL_NAND_CS (2<<3)
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#define ZY7_SLCR_MIO_PIN_L2_SEL_SDIO0_PC (3<<3)
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#define ZY7_SLCR_MIO_PIN_L1_SEL (1<<2)
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#define ZY7_SLCR_MIO_PIN_L0_SEL (1<<1)
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#define ZY7_SLCR_MIO_PIN_TRI_EN (1<<0)
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#define ZY7_SLCR_MIO_LOOPBACK 0x0804
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#define ZY7_SLCR_MIO_LOOPBACK_I2C0_I2C1 (1<<3)
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#define ZY7_SLCR_MIO_LOOPBACK_CAN0_CAN1 (1<<2)
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#define ZY7_SLCR_MIO_LOOPBACK_UA0_UA1 (1<<1)
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#define ZY7_SLCR_MIO_LOOPBACK_SPI0_SPI1 (1<<0)
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#define ZY7_SLCR_MIO_MST_TRI0 0x080c
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#define ZY7_SLCR_MIO_MST_TRI1 0x0810
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#define ZY7_SLCR_SD0_WP_CD_SEL 0x0830
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#define ZY7_SLCR_SD1_WP_CD_SEL 0x0834
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/* PS-PL level shifter control. */
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#define ZY7_SLCR_LVL_SHFTR_EN 0x900
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_0 (1<<3) /* PL to PS */
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_0 (1<<2) /* PS to PL */
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_1 (1<<1) /* PL to PS */
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_1 (1<<0) /* PS to PL */
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#define ZY7_SLCR_LVL_SHFTR_EN_ALL 0xf
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#define ZY7_SLCR_OCM_CFG 0x0910
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#define ZY7_SLCR_GPIOB_CTRL 0x0b00
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#define ZY7_SLCR_GPIOB_CFG_CMOS18 0x0b04
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#define ZY7_SLCR_GPIOB_CFG_CMOS25 0x0b08
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#define ZY7_SLCR_GPIOB_CFG_CMOS33 0x0b0c
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#define ZY7_SLCR_GPIOB_CFG_LVTTL 0x0b10
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#define ZY7_SLCR_GPIOB_CFG_HSTL 0x0b14
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#define ZY7_SLCR_GPIOB_DRVR_BIAS_CTRL 0x0b18
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#define ZY7_SLCR_DDRIOB_ADDR0 0x0b40
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#define ZY7_SLCR_DDRIOB_ADDR1 0x0b44
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#define ZY7_SLCR_DDRIOB_DATA0 0x0b48
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#define ZY7_SLCR_DDRIOB_DATA1 0x0b4c
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#define ZY7_SLCR_DDRIOB_DIFF0 0x0b50
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#define ZY7_SLCR_DDRIOB_DIFF1 0x0b54
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#define ZY7_SLCR_DDRIOB_CLK 0x0b58
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_ADDR 0x0b5c
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DATA 0x0b60
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DIFF 0x0b64
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_CLK 0x0b68
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#define ZY7_SLCR_DDRIOB_DDR_CTRL 0x0b6c
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#define ZY7_SLCR_DDRIOB_DCI_CTRL 0x0b70
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#define ZY7_SLCR_DDRIOB_DCI_STATUS 0x0b74
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#ifdef _KERNEL
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extern void zy7_slcr_preload_pl(void);
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extern void zy7_slcr_postload_pl(int en_level_shifters);
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extern int cgem_set_ref_clk(int unit, int frequency);
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/* Should be consistent with SRCSEL field of FPGAx_CLK_CTRL */
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#define ZY7_PL_FCLK_SRC_IO 0
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#define ZY7_PL_FCLK_SRC_IO_ALT 1 /* ZY7_PL_FCLK_SRC_IO is b0x */
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#define ZY7_PL_FCLK_SRC_ARM 2
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#define ZY7_PL_FCLK_SRC_DDR 3
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int zy7_pl_fclk_set_source(int unit, int source);
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int zy7_pl_fclk_get_source(int unit);
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int zy7_pl_fclk_set_freq(int unit, int freq);
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int zy7_pl_fclk_get_freq(int unit);
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int zy7_pl_fclk_enable(int unit);
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int zy7_pl_fclk_disable(int unit);
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int zy7_pl_fclk_enabled(int unit);
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int zy7_pl_level_shifters_enabled(void);
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void zy7_pl_level_shifters_enable(void);
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void zy7_pl_level_shifters_disable(void);
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#endif
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#endif /* _ZY7_SLCR_H_ */
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