515d0c1d29
having the CPU device that's a child of atmelarm that does stuff. o Create a linker_set for the support fucntions for the SoCs. o Rename soc_data to soc_info. o Move the delay and reset function pointers to new soc_data struct o Create elements for all known SoCs o Add lookup of the SoC we found, and print a warning if it isn't one we know about.
314 lines
7.5 KiB
C
314 lines
7.5 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91_streg.h>
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#include <arm/at91/at91rm92reg.h>
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static struct at91_st_softc {
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struct resource * sc_irq_res;
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struct resource * sc_mem_res;
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void * sc_intrhand;
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eventhandler_tag sc_wet; /* watchdog event handler tag */
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} *timer_softc;
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static inline uint32_t
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RD4(bus_size_t off)
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{
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if (timer_softc == NULL) {
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uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
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return *p;
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}
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return (bus_read_4(timer_softc->sc_mem_res, off));
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}
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static inline void
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WR4(bus_size_t off, uint32_t val)
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{
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if (timer_softc == NULL) {
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uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
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*p = val;
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}
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else
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bus_write_4(timer_softc->sc_mem_res, off, val);
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}
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static void at91_st_watchdog(void *, u_int, int *);
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static void at91_st_initclocks(device_t , struct at91_st_softc *);
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static inline int
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st_crtr(void)
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{
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int cur1, cur2;
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do {
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cur1 = RD4(ST_CRTR);
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cur2 = RD4(ST_CRTR);
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} while (cur1 != cur2);
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return (cur1);
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}
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static unsigned at91_st_get_timecount(struct timecounter *tc);
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static struct timecounter at91_st_timecounter = {
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at91_st_get_timecount, /* get_timecount */
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NULL, /* no poll_pps */
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0xfffffu, /* counter_mask */
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32768, /* frequency */
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"AT91RM9200 timer", /* name */
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1000 /* quality */
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};
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static int
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clock_intr(void *arg)
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{
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struct trapframe *fp = arg;
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/* The interrupt is shared, so we have to make sure it's for us. */
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if (RD4(ST_SR) & ST_SR_PITS) {
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hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
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return (FILTER_HANDLED);
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}
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return (FILTER_STRAY);
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}
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void
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at91_st_delay(int n)
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{
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uint32_t start, end, cur;
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start = st_crtr();
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n = (n * 1000) / 32768;
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if (n <= 0)
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n = 1;
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end = (start + n) & ST_CRTR_MASK;
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cur = start;
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if (start > end) {
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while (cur >= start || cur < end)
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cur = st_crtr();
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} else {
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while (cur < end)
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cur = st_crtr();
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}
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}
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void
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at91_st_cpu_reset(void)
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{
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/*
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* Reset the CPU by programmig the watchdog timer to reset the
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* CPU after 128 'slow' clocks, or about ~4ms. Loop until
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* the reset happens for safety.
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*/
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WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
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WR4(ST_CR, ST_CR_WDRST);
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while (1)
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continue;
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}
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static int
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at91_st_probe(device_t dev)
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{
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device_set_desc(dev, "ST");
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return (0);
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}
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static void
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at91_st_deactivate(device_t dev)
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{
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struct at91_st_softc *sc = timer_softc;
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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sc->sc_intrhand = NULL;
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
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sc->sc_irq_res = NULL;
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
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sc->sc_mem_res = NULL;
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}
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static int
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at91_st_activate(device_t dev)
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{
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int rid;
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int err;
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struct at91_st_softc *sc = timer_softc;
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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err = ENOMEM;
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if (sc->sc_mem_res == NULL)
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goto out;
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/* Disable all interrupts */
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WR4(ST_IDR, 0xffffffff);
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/* The system timer shares the system irq (1) */
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->sc_irq_res == NULL) {
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printf("Unable to allocate irq for the system timer");
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goto out;
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}
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err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_CLK, clock_intr,
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NULL, NULL, &sc->sc_intrhand);
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out:
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if (err != 0)
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at91_st_deactivate(dev);
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return (err);
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}
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static int
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at91_st_attach(device_t dev)
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{
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int err;
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timer_softc = device_get_softc(dev);
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err = at91_st_activate(dev);
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if (err)
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return err;
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timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
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at91_st_watchdog, dev, 0);
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device_printf(dev,
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"watchdog registered, timeout intervall max. 64 sec\n");
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at91_st_initclocks(dev, timer_softc);
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return (0);
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}
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static device_method_t at91_st_methods[] = {
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DEVMETHOD(device_probe, at91_st_probe),
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DEVMETHOD(device_attach, at91_st_attach),
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{0, 0},
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};
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static driver_t at91_st_driver = {
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"at91_st",
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at91_st_methods,
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sizeof(struct at91_st_softc),
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};
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static devclass_t at91_st_devclass;
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DRIVER_MODULE(at91_st, atmelarm, at91_st_driver, at91_st_devclass, 0, 0);
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static unsigned
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at91_st_get_timecount(struct timecounter *tc)
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{
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return (st_crtr());
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}
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/*
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* t below is in a weird unit. The watchdog is set to 2^t
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* nanoseconds. Since our watchdog timer can't really do that too
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* well, we approximate it by assuming that the timeout interval for
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* the lsb is 2^22 ns, which is 4.194ms. This is an overestimation of
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* the actual time (3.906ms), but close enough for watchdogging.
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* These approximations, though a violation of the spec, improve the
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* performance of the application which typically specifies things as
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* WD_TO_32SEC. In that last case, we'd wait 32s before the wdog
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* reset. The spec says we should wait closer to 34s, but given how
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* it is likely to be used, and the extremely coarse nature time
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* interval, I think this is the best solution.
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*/
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static void
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at91_st_watchdog(void *argp, u_int cmd, int *error)
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{
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uint32_t wdog;
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int t;
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t = cmd & WD_INTERVAL;
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if (t >= 22 && t <= 37) {
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wdog = (1 << (t - 22)) | ST_WDMR_RSTEN;
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*error = 0;
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} else {
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wdog = 0;
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}
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WR4(ST_WDMR, wdog);
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WR4(ST_CR, ST_CR_WDRST);
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}
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static void
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at91_st_initclocks(device_t dev, struct at91_st_softc *sc)
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{
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int rel_value;
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/*
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* Real time counter increments every clock cycle, need to set before
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* initializing clocks so that DELAY works.
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*/
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WR4(ST_RTMR, 1);
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/* disable watchdog timer */
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WR4(ST_WDMR, 0);
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rel_value = 32768 / hz;
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if (rel_value < 1)
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rel_value = 1;
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if (32768 % hz) {
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device_printf(dev, "Cannot get %d Hz clock; using %dHz\n", hz,
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32768 / rel_value);
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hz = 32768 / rel_value;
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tick = 1000000 / hz;
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}
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WR4(ST_PIMR, rel_value);
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/* Enable PITS interrupts. */
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WR4(ST_IER, ST_SR_PITS);
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tc_init(&at91_st_timecounter);
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}
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