76640cb48b
skeleton (maybe we should kobj-tize this one day). Note the PPC4xx bit is not connected to the build yet. Obtained from: AppliedMicro, Semihalf.
159 lines
4.1 KiB
C
159 lines
4.1 KiB
C
/*-
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/reboot.h>
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#include <machine/machdep.h>
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#include <dev/fdt/fdt_common.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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extern void dcache_enable(void);
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extern void dcache_inval(void);
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extern void icache_enable(void);
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extern void icache_inval(void);
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extern void l2cache_enable(void);
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extern void l2cache_inval(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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{
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/* Initialize TLB1 handling */
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tlb1_init(fdt_immr_pa);
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}
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void
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booke_enable_l1_cache(void)
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{
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uint32_t csr;
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/* Enable D-cache if applicable */
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csr = mfspr(SPR_L1CSR0);
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if ((csr & L1CSR0_DCE) == 0) {
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dcache_inval();
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dcache_enable();
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}
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csr = mfspr(SPR_L1CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
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printf("L1 D-cache %sabled\n",
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(csr & L1CSR0_DCE) ? "en" : "dis");
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/* Enable L1 I-cache if applicable. */
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csr = mfspr(SPR_L1CSR1);
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if ((csr & L1CSR1_ICE) == 0) {
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icache_inval();
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icache_enable();
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}
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csr = mfspr(SPR_L1CSR1);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
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printf("L1 I-cache %sabled\n",
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(csr & L1CSR1_ICE) ? "en" : "dis");
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}
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#if 0
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void
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booke_enable_l2_cache(void)
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{
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uint32_t csr;
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/* Enable L2 cache on E500mc */
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if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
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(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
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csr = mfspr(SPR_L2CSR0);
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if ((csr & L2CSR0_L2E) == 0) {
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l2cache_inval();
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l2cache_enable();
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}
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csr = mfspr(SPR_L2CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
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printf("L2 cache %sabled\n",
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(csr & L2CSR0_L2E) ? "en" : "dis");
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}
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}
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void
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booke_enable_l3_cache(void)
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{
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uint32_t csr, size, ver;
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/* Enable L3 CoreNet Platform Cache (CPC) */
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
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ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
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l3cache_inval();
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l3cache_enable();
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}
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csr = ccsr_read4(OCP85XX_CPC_CSR0);
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if ((boothowto & RB_VERBOSE) != 0 ||
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(csr & OCP85XX_CPC_CSR0_CE) == 0) {
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size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
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printf("L3 Corenet Platform Cache: %d KB %sabled\n",
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size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
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"dis" : "en");
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}
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}
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}
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void
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booke_disable_l2_cache(void)
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{
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}
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static void
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l3cache_inval(void)
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{
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/* Flash invalidate the CPC and clear all the locks */
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC);
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while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
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OCP85XX_CPC_CSR0_LFC))
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;
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}
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static void
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l3cache_enable(void)
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{
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ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
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OCP85XX_CPC_CSR0_PE);
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/* Read back to sync write */
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ccsr_read4(OCP85XX_CPC_CSR0);
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}
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#endif
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