Warner Losh 1cc75127dc The UART device infrasturcture wants these defined. Define them just
like we do in Malta.  We may want to look at consolidating things
because *ALL* mips will *ALWAYS* be memory mapped.  The only wrinkle
is that the tag may need to be a custom one (see endian issues with
the Atheros port for one example).
2009-08-15 19:48:14 +00:00
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