c15f698fb4
a new firmware command. NVMe controllers may support up to 7 firmware slots for storing of different firmware revisions. This new firmware command supports firmware replacement (i.e. firmware download) with or without immediate activation, or activation of a previously stored firmware image. It also supports selection of the firmware slot during replacement operations, using IDENTIFY information from the controller to check that the specified slot is valid. Newly activated firmware does not take effect until the new controller reset, either via a reboot or separate 'nvmecontrol reset' command to the same controller. Submitted by: Joe Golio <joseph.golio@emc.com> Obtained from: EMC / Isilon Storage Division MFC after: 3 days
871 lines
21 KiB
C
871 lines
21 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __NVME_H__
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#define __NVME_H__
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#ifdef _KERNEL
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#include <sys/types.h>
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#endif
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#include <sys/param.h>
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#define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
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#define NVME_RESET_CONTROLLER _IO('n', 1)
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#define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
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#define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
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/*
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* Use to mark a command to apply to all namespaces, or to retrieve global
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* log pages.
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*/
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#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
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#define NVME_MAX_XFER_SIZE MAXPHYS
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union cap_lo_register {
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uint32_t raw;
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struct {
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/** maximum queue entries supported */
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uint32_t mqes : 16;
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/** contiguous queues required */
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uint32_t cqr : 1;
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/** arbitration mechanism supported */
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uint32_t ams : 2;
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uint32_t reserved1 : 5;
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/** timeout */
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uint32_t to : 8;
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} bits __packed;
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} __packed;
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union cap_hi_register {
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uint32_t raw;
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struct {
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/** doorbell stride */
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uint32_t dstrd : 4;
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uint32_t reserved3 : 1;
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/** command sets supported */
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uint32_t css_nvm : 1;
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uint32_t css_reserved : 3;
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uint32_t reserved2 : 7;
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/** memory page size minimum */
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uint32_t mpsmin : 4;
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/** memory page size maximum */
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uint32_t mpsmax : 4;
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uint32_t reserved1 : 8;
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} bits __packed;
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} __packed;
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union cc_register {
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uint32_t raw;
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struct {
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/** enable */
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uint32_t en : 1;
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uint32_t reserved1 : 3;
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/** i/o command set selected */
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uint32_t css : 3;
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/** memory page size */
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uint32_t mps : 4;
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/** arbitration mechanism selected */
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uint32_t ams : 3;
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/** shutdown notification */
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uint32_t shn : 2;
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/** i/o submission queue entry size */
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uint32_t iosqes : 4;
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/** i/o completion queue entry size */
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uint32_t iocqes : 4;
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uint32_t reserved2 : 8;
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} bits __packed;
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} __packed;
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enum shn_value {
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NVME_SHN_NORMAL = 0x1,
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NVME_SHN_ABRUPT = 0x2,
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};
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union csts_register {
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uint32_t raw;
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struct {
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/** ready */
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uint32_t rdy : 1;
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/** controller fatal status */
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uint32_t cfs : 1;
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/** shutdown status */
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uint32_t shst : 2;
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uint32_t reserved1 : 28;
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} bits __packed;
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} __packed;
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enum shst_value {
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NVME_SHST_NORMAL = 0x0,
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NVME_SHST_OCCURRING = 0x1,
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NVME_SHST_COMPLETE = 0x2,
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};
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union aqa_register {
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uint32_t raw;
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struct {
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/** admin submission queue size */
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uint32_t asqs : 12;
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uint32_t reserved1 : 4;
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/** admin completion queue size */
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uint32_t acqs : 12;
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uint32_t reserved2 : 4;
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} bits __packed;
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} __packed;
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struct nvme_registers
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{
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/** controller capabilities */
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union cap_lo_register cap_lo;
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union cap_hi_register cap_hi;
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uint32_t vs; /* version */
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uint32_t intms; /* interrupt mask set */
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uint32_t intmc; /* interrupt mask clear */
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/** controller configuration */
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union cc_register cc;
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uint32_t reserved1;
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uint32_t csts; /* controller status */
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uint32_t reserved2;
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/** admin queue attributes */
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union aqa_register aqa;
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uint64_t asq; /* admin submission queue base addr */
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uint64_t acq; /* admin completion queue base addr */
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uint32_t reserved3[0x3f2];
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struct {
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uint32_t sq_tdbl; /* submission queue tail doorbell */
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uint32_t cq_hdbl; /* completion queue head doorbell */
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} doorbell[1] __packed;
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} __packed;
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struct nvme_command
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{
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/* dword 0 */
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uint16_t opc : 8; /* opcode */
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uint16_t fuse : 2; /* fused operation */
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uint16_t rsvd1 : 6;
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uint16_t cid; /* command identifier */
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/* dword 1 */
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uint32_t nsid; /* namespace identifier */
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/* dword 2-3 */
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uint32_t rsvd2;
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uint32_t rsvd3;
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/* dword 4-5 */
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uint64_t mptr; /* metadata pointer */
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/* dword 6-7 */
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uint64_t prp1; /* prp entry 1 */
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/* dword 8-9 */
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uint64_t prp2; /* prp entry 2 */
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/* dword 10-15 */
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uint32_t cdw10; /* command-specific */
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uint32_t cdw11; /* command-specific */
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uint32_t cdw12; /* command-specific */
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uint32_t cdw13; /* command-specific */
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uint32_t cdw14; /* command-specific */
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uint32_t cdw15; /* command-specific */
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} __packed;
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struct nvme_status {
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uint16_t p : 1; /* phase tag */
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uint16_t sc : 8; /* status code */
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uint16_t sct : 3; /* status code type */
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uint16_t rsvd2 : 2;
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uint16_t m : 1; /* more */
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uint16_t dnr : 1; /* do not retry */
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} __packed;
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struct nvme_completion {
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/* dword 0 */
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uint32_t cdw0; /* command-specific */
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/* dword 1 */
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uint32_t rsvd1;
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/* dword 2 */
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uint16_t sqhd; /* submission queue head pointer */
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uint16_t sqid; /* submission queue identifier */
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/* dword 3 */
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uint16_t cid; /* command identifier */
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struct nvme_status status;
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} __packed;
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struct nvme_dsm_range {
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uint32_t attributes;
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uint32_t length;
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uint64_t starting_lba;
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} __packed;
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/* status code types */
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enum nvme_status_code_type {
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NVME_SCT_GENERIC = 0x0,
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NVME_SCT_COMMAND_SPECIFIC = 0x1,
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NVME_SCT_MEDIA_ERROR = 0x2,
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/* 0x3-0x6 - reserved */
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NVME_SCT_VENDOR_SPECIFIC = 0x7,
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};
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/* generic command status codes */
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enum nvme_generic_command_status_code {
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NVME_SC_SUCCESS = 0x00,
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NVME_SC_INVALID_OPCODE = 0x01,
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NVME_SC_INVALID_FIELD = 0x02,
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NVME_SC_COMMAND_ID_CONFLICT = 0x03,
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NVME_SC_DATA_TRANSFER_ERROR = 0x04,
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NVME_SC_ABORTED_POWER_LOSS = 0x05,
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NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
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NVME_SC_ABORTED_BY_REQUEST = 0x07,
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NVME_SC_ABORTED_SQ_DELETION = 0x08,
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NVME_SC_ABORTED_FAILED_FUSED = 0x09,
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NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
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NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
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NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
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NVME_SC_LBA_OUT_OF_RANGE = 0x80,
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NVME_SC_CAPACITY_EXCEEDED = 0x81,
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NVME_SC_NAMESPACE_NOT_READY = 0x82,
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};
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/* command specific status codes */
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enum nvme_command_specific_status_code {
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NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
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NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
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NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
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NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
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/* 0x04 - reserved */
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NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
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NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
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NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
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NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
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NVME_SC_INVALID_LOG_PAGE = 0x09,
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NVME_SC_INVALID_FORMAT = 0x0a,
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NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
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NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
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NVME_SC_INVALID_PROTECTION_INFO = 0x81,
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NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
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};
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/* media error status codes */
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enum nvme_media_error_status_code {
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NVME_SC_WRITE_FAULTS = 0x80,
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NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
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NVME_SC_GUARD_CHECK_ERROR = 0x82,
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NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
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NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
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NVME_SC_COMPARE_FAILURE = 0x85,
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NVME_SC_ACCESS_DENIED = 0x86,
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};
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/* admin opcodes */
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enum nvme_admin_opcode {
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NVME_OPC_DELETE_IO_SQ = 0x00,
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NVME_OPC_CREATE_IO_SQ = 0x01,
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NVME_OPC_GET_LOG_PAGE = 0x02,
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/* 0x03 - reserved */
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NVME_OPC_DELETE_IO_CQ = 0x04,
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NVME_OPC_CREATE_IO_CQ = 0x05,
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NVME_OPC_IDENTIFY = 0x06,
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/* 0x07 - reserved */
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NVME_OPC_ABORT = 0x08,
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NVME_OPC_SET_FEATURES = 0x09,
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NVME_OPC_GET_FEATURES = 0x0a,
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/* 0x0b - reserved */
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NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
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/* 0x0d-0x0f - reserved */
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NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
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NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
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NVME_OPC_FORMAT_NVM = 0x80,
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NVME_OPC_SECURITY_SEND = 0x81,
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NVME_OPC_SECURITY_RECEIVE = 0x82,
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};
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/* nvme nvm opcodes */
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enum nvme_nvm_opcode {
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NVME_OPC_FLUSH = 0x00,
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NVME_OPC_WRITE = 0x01,
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NVME_OPC_READ = 0x02,
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/* 0x03 - reserved */
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NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
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NVME_OPC_COMPARE = 0x05,
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/* 0x06-0x07 - reserved */
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NVME_OPC_DATASET_MANAGEMENT = 0x09,
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};
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enum nvme_feature {
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/* 0x00 - reserved */
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NVME_FEAT_ARBITRATION = 0x01,
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NVME_FEAT_POWER_MANAGEMENT = 0x02,
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NVME_FEAT_LBA_RANGE_TYPE = 0x03,
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NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
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NVME_FEAT_ERROR_RECOVERY = 0x05,
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NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
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NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
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NVME_FEAT_INTERRUPT_COALESCING = 0x08,
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NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
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NVME_FEAT_WRITE_ATOMICITY = 0x0A,
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NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
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/* 0x0C-0x7F - reserved */
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NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
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/* 0x81-0xBF - command set specific (reserved) */
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/* 0xC0-0xFF - vendor specific */
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};
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enum nvme_dsm_attribute {
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NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
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NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
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NVME_DSM_ATTR_DEALLOCATE = 0x4,
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};
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enum nvme_activate_action {
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NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
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NVME_AA_REPLACE_ACTIVATE = 0x1,
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NVME_AA_ACTIVATE = 0x2,
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};
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struct nvme_controller_data {
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/* bytes 0-255: controller capabilities and features */
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/** pci vendor id */
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uint16_t vid;
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/** pci subsystem vendor id */
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uint16_t ssvid;
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/** serial number */
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int8_t sn[20];
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/** model number */
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int8_t mn[40];
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/** firmware revision */
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uint8_t fr[8];
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/** recommended arbitration burst */
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uint8_t rab;
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/** ieee oui identifier */
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uint8_t ieee[3];
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/** multi-interface capabilities */
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uint8_t mic;
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/** maximum data transfer size */
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uint8_t mdts;
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uint8_t reserved1[178];
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/* bytes 256-511: admin command set attributes */
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/** optional admin command support */
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struct {
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/* supports security send/receive commands */
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uint16_t security : 1;
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/* supports format nvm command */
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uint16_t format : 1;
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/* supports firmware activate/download commands */
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uint16_t firmware : 1;
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uint16_t oacs_rsvd : 13;
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} __packed oacs;
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/** abort command limit */
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uint8_t acl;
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/** asynchronous event request limit */
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uint8_t aerl;
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/** firmware updates */
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struct {
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/* first slot is read-only */
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uint8_t slot1_ro : 1;
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/* number of firmware slots */
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uint8_t num_slots : 3;
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uint8_t frmw_rsvd : 4;
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} __packed frmw;
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/** log page attributes */
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struct {
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/* per namespace smart/health log page */
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uint8_t ns_smart : 1;
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uint8_t lpa_rsvd : 7;
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} __packed lpa;
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/** error log page entries */
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uint8_t elpe;
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/** number of power states supported */
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uint8_t npss;
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/** admin vendor specific command configuration */
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struct {
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/* admin vendor specific commands use spec format */
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uint8_t spec_format : 1;
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uint8_t avscc_rsvd : 7;
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} __packed avscc;
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uint8_t reserved2[247];
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/* bytes 512-703: nvm command set attributes */
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/** submission queue entry size */
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struct {
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uint8_t min : 4;
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uint8_t max : 4;
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} __packed sqes;
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/** completion queue entry size */
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struct {
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uint8_t min : 4;
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uint8_t max : 4;
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} __packed cqes;
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uint8_t reserved3[2];
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/** number of namespaces */
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uint32_t nn;
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/** optional nvm command support */
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struct {
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uint16_t compare : 1;
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uint16_t write_unc : 1;
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uint16_t dsm: 1;
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uint16_t reserved: 13;
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} __packed oncs;
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/** fused operation support */
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uint16_t fuses;
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/** format nvm attributes */
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uint8_t fna;
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/** volatile write cache */
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struct {
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uint8_t present : 1;
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uint8_t reserved : 7;
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} __packed vwc;
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/* TODO: flesh out remaining nvm command set attributes */
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uint8_t reserved4[178];
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/* bytes 704-2047: i/o command set attributes */
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uint8_t reserved5[1344];
|
|
|
|
/* bytes 2048-3071: power state descriptors */
|
|
uint8_t reserved6[1024];
|
|
|
|
/* bytes 3072-4095: vendor specific */
|
|
uint8_t reserved7[1024];
|
|
} __packed __aligned(4);
|
|
|
|
struct nvme_namespace_data {
|
|
|
|
/** namespace size */
|
|
uint64_t nsze;
|
|
|
|
/** namespace capacity */
|
|
uint64_t ncap;
|
|
|
|
/** namespace utilization */
|
|
uint64_t nuse;
|
|
|
|
/** namespace features */
|
|
struct {
|
|
/** thin provisioning */
|
|
uint8_t thin_prov : 1;
|
|
uint8_t reserved1 : 7;
|
|
} __packed nsfeat;
|
|
|
|
/** number of lba formats */
|
|
uint8_t nlbaf;
|
|
|
|
/** formatted lba size */
|
|
struct {
|
|
uint8_t format : 4;
|
|
uint8_t extended : 1;
|
|
uint8_t reserved2 : 3;
|
|
} __packed flbas;
|
|
|
|
/** metadata capabilities */
|
|
struct {
|
|
/* metadata can be transferred as part of data prp list */
|
|
uint8_t extended : 1;
|
|
|
|
/* metadata can be transferred with separate metadata pointer */
|
|
uint8_t pointer : 1;
|
|
|
|
uint8_t reserved3 : 6;
|
|
} __packed mc;
|
|
|
|
/** end-to-end data protection capabilities */
|
|
struct {
|
|
/* protection information type 1 */
|
|
uint8_t pit1 : 1;
|
|
|
|
/* protection information type 2 */
|
|
uint8_t pit2 : 1;
|
|
|
|
/* protection information type 3 */
|
|
uint8_t pit3 : 1;
|
|
|
|
/* first eight bytes of metadata */
|
|
uint8_t md_start : 1;
|
|
|
|
/* last eight bytes of metadata */
|
|
uint8_t md_end : 1;
|
|
} __packed dpc;
|
|
|
|
/** end-to-end data protection type settings */
|
|
struct {
|
|
/* protection information type */
|
|
uint8_t pit : 3;
|
|
|
|
/* 1 == protection info transferred at start of metadata */
|
|
/* 0 == protection info transferred at end of metadata */
|
|
uint8_t md_start : 1;
|
|
|
|
uint8_t reserved4 : 4;
|
|
} __packed dps;
|
|
|
|
uint8_t reserved5[98];
|
|
|
|
/** lba format support */
|
|
struct {
|
|
/** metadata size */
|
|
uint32_t ms : 16;
|
|
|
|
/** lba data size */
|
|
uint32_t lbads : 8;
|
|
|
|
/** relative performance */
|
|
uint32_t rp : 2;
|
|
|
|
uint32_t reserved6 : 6;
|
|
} __packed lbaf[16];
|
|
|
|
uint8_t reserved6[192];
|
|
|
|
uint8_t vendor_specific[3712];
|
|
} __packed __aligned(4);
|
|
|
|
enum nvme_log_page {
|
|
|
|
/* 0x00 - reserved */
|
|
NVME_LOG_ERROR = 0x01,
|
|
NVME_LOG_HEALTH_INFORMATION = 0x02,
|
|
NVME_LOG_FIRMWARE_SLOT = 0x03,
|
|
/* 0x04-0x7F - reserved */
|
|
/* 0x80-0xBF - I/O command set specific */
|
|
/* 0xC0-0xFF - vendor specific */
|
|
};
|
|
|
|
struct nvme_error_information_entry {
|
|
|
|
uint64_t error_count;
|
|
uint16_t sqid;
|
|
uint16_t cid;
|
|
struct nvme_status status;
|
|
uint16_t error_location;
|
|
uint64_t lba;
|
|
uint32_t nsid;
|
|
uint8_t vendor_specific;
|
|
uint8_t reserved[35];
|
|
} __packed __aligned(4);
|
|
|
|
union nvme_critical_warning_state {
|
|
|
|
uint8_t raw;
|
|
|
|
struct {
|
|
uint8_t available_spare : 1;
|
|
uint8_t temperature : 1;
|
|
uint8_t device_reliability : 1;
|
|
uint8_t read_only : 1;
|
|
uint8_t volatile_memory_backup : 1;
|
|
uint8_t reserved : 3;
|
|
} __packed bits;
|
|
} __packed;
|
|
|
|
struct nvme_health_information_page {
|
|
|
|
union nvme_critical_warning_state critical_warning;
|
|
|
|
uint16_t temperature;
|
|
uint8_t available_spare;
|
|
uint8_t available_spare_threshold;
|
|
uint8_t percentage_used;
|
|
|
|
uint8_t reserved[26];
|
|
|
|
/*
|
|
* Note that the following are 128-bit values, but are
|
|
* defined as an array of 2 64-bit values.
|
|
*/
|
|
/* Data Units Read is always in 512-byte units. */
|
|
uint64_t data_units_read[2];
|
|
/* Data Units Written is always in 512-byte units. */
|
|
uint64_t data_units_written[2];
|
|
/* For NVM command set, this includes Compare commands. */
|
|
uint64_t host_read_commands[2];
|
|
uint64_t host_write_commands[2];
|
|
/* Controller Busy Time is reported in minutes. */
|
|
uint64_t controller_busy_time[2];
|
|
uint64_t power_cycles[2];
|
|
uint64_t power_on_hours[2];
|
|
uint64_t unsafe_shutdowns[2];
|
|
uint64_t media_errors[2];
|
|
uint64_t num_error_info_log_entries[2];
|
|
|
|
uint8_t reserved2[320];
|
|
} __packed __aligned(4);
|
|
|
|
struct nvme_firmware_page {
|
|
|
|
struct {
|
|
uint8_t slot : 3; /* slot for current FW */
|
|
uint8_t reserved : 5;
|
|
} __packed afi;
|
|
|
|
uint8_t reserved[7];
|
|
uint64_t revision[7]; /* revisions for 7 slots */
|
|
uint8_t reserved2[448];
|
|
} __packed __aligned(4);
|
|
|
|
#define NVME_TEST_MAX_THREADS 128
|
|
|
|
struct nvme_io_test {
|
|
|
|
enum nvme_nvm_opcode opc;
|
|
uint32_t size;
|
|
uint32_t time; /* in seconds */
|
|
uint32_t num_threads;
|
|
uint32_t flags;
|
|
uint32_t io_completed[NVME_TEST_MAX_THREADS];
|
|
};
|
|
|
|
enum nvme_io_test_flags {
|
|
|
|
/*
|
|
* Specifies whether dev_refthread/dev_relthread should be
|
|
* called during NVME_BIO_TEST. Ignored for other test
|
|
* types.
|
|
*/
|
|
NVME_TEST_FLAG_REFTHREAD = 0x1,
|
|
};
|
|
|
|
struct nvme_pt_command {
|
|
|
|
/*
|
|
* cmd is used to specify a passthrough command to a controller or
|
|
* namespace.
|
|
*
|
|
* The following fields from cmd may be specified by the caller:
|
|
* * opc (opcode)
|
|
* * nsid (namespace id) - for admin commands only
|
|
* * cdw10-cdw15
|
|
*
|
|
* Remaining fields must be set to 0 by the caller.
|
|
*/
|
|
struct nvme_command cmd;
|
|
|
|
/*
|
|
* cpl returns completion status for the passthrough command
|
|
* specified by cmd.
|
|
*
|
|
* The following fields will be filled out by the driver, for
|
|
* consumption by the caller:
|
|
* * cdw0
|
|
* * status (except for phase)
|
|
*
|
|
* Remaining fields will be set to 0 by the driver.
|
|
*/
|
|
struct nvme_completion cpl;
|
|
|
|
/* buf is the data buffer associated with this passthrough command. */
|
|
void * buf;
|
|
|
|
/*
|
|
* len is the length of the data buffer associated with this
|
|
* passthrough command.
|
|
*/
|
|
uint32_t len;
|
|
|
|
/*
|
|
* is_read = 1 if the passthrough command will read data into the
|
|
* supplied buffer.
|
|
*
|
|
* is_read = 0 if the passthrough command will write data into the
|
|
* supplied buffer.
|
|
*/
|
|
uint32_t is_read;
|
|
|
|
/*
|
|
* driver_lock is used by the driver only. It must be set to 0
|
|
* by the caller.
|
|
*/
|
|
struct mtx * driver_lock;
|
|
};
|
|
|
|
#define nvme_completion_is_error(cpl) \
|
|
((cpl)->status.sc != 0 || (cpl)->status.sct != 0)
|
|
|
|
#ifdef _KERNEL
|
|
|
|
struct bio;
|
|
|
|
struct nvme_namespace;
|
|
struct nvme_controller;
|
|
struct nvme_consumer;
|
|
|
|
typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
|
|
|
|
typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
|
|
typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
|
|
typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
|
|
uint32_t, void *, uint32_t);
|
|
typedef void (*nvme_cons_fail_fn_t)(void *);
|
|
|
|
enum nvme_namespace_flags {
|
|
NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
|
|
NVME_NS_FLUSH_SUPPORTED = 0x2,
|
|
};
|
|
|
|
int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
|
|
struct nvme_pt_command *pt,
|
|
uint32_t nsid, int is_user_buffer,
|
|
int is_admin_cmd);
|
|
|
|
/* Admin functions */
|
|
void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
|
|
uint8_t feature, uint32_t cdw11,
|
|
void *payload, uint32_t payload_size,
|
|
nvme_cb_fn_t cb_fn, void *cb_arg);
|
|
void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
|
|
uint8_t feature, uint32_t cdw11,
|
|
void *payload, uint32_t payload_size,
|
|
nvme_cb_fn_t cb_fn, void *cb_arg);
|
|
void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
|
|
uint8_t log_page, uint32_t nsid,
|
|
void *payload, uint32_t payload_size,
|
|
nvme_cb_fn_t cb_fn, void *cb_arg);
|
|
|
|
/* NVM I/O functions */
|
|
int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
|
|
uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
|
|
void *cb_arg);
|
|
int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
|
|
nvme_cb_fn_t cb_fn, void *cb_arg);
|
|
int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
|
|
uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
|
|
void *cb_arg);
|
|
int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
|
|
nvme_cb_fn_t cb_fn, void *cb_arg);
|
|
int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
|
|
uint8_t num_ranges, nvme_cb_fn_t cb_fn,
|
|
void *cb_arg);
|
|
int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
|
|
void *cb_arg);
|
|
|
|
/* Registration functions */
|
|
struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
|
|
nvme_cons_ctrlr_fn_t ctrlr_fn,
|
|
nvme_cons_async_fn_t async_fn,
|
|
nvme_cons_fail_fn_t fail_fn);
|
|
void nvme_unregister_consumer(struct nvme_consumer *consumer);
|
|
|
|
/* Controller helper functions */
|
|
device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
|
|
const struct nvme_controller_data *
|
|
nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
|
|
|
|
/* Namespace helper functions */
|
|
uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
|
|
uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
|
|
uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
|
|
uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
|
|
uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
|
|
const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
|
|
const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
|
|
const struct nvme_namespace_data *
|
|
nvme_ns_get_data(struct nvme_namespace *ns);
|
|
|
|
int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
|
|
nvme_cb_fn_t cb_fn);
|
|
|
|
#endif /* _KERNEL */
|
|
|
|
#endif /* __NVME_H__ */
|