de7f32ad05
All devices: - add support for rate adaptation via ieee80211_amrr(9); - use short preamble for transmitted frames when needed; - multi-bss support: * for RTL8821AU: 2 VAPs at the same time; * other: 1 any VAP + 1 sta VAP. RTL8188CE: - fix IQ calibration bug (reason of significant speed degradation); - add h/w crypto acceleration support. USB: - A-MPDU Tx support; - short GI support; Other: - add support for RTL8812AU / RTL8821AU chipsets (a/b/g/n only; no ac yet); - split merged code into subparts: * bus glue (usb/*, pci/*, rtl*/usb/*, rtl*/pci/*) * common (if_rtwn*) * chip-specific (rtl*/*) - various other bugfixes. Due to code reorganization, module names / requirements were changed too: urtwn urtwnfw -> rtwn rtwn_usb rtwnfw rtwn rtwnfw -> rtwn rtwn_pci rtwnfw Tested with RTL8188CE, RTL8188CUS, RTL8188EU and RTL8821AU. Tested by: kevlo, garga, Peter Garshtja <peter.garshtja@ambient-md.com>, Kevin McAleavey <kevin.mcaleavey@knosproject.com>, Ilias-Dimitrios Vrachnis <id@vrachnis.com>, <otacilio.neto@bsd.com.br> Relnotes: yes
159 lines
4.3 KiB
C
159 lines
4.3 KiB
C
/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
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/*-
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* Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
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* Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/rtl8192c/r92c.h>
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#include <dev/rtwn/rtl8192c/r92c_var.h>
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#include <dev/rtwn/rtl8188e/r88e.h>
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#include <dev/rtwn/rtl8188e/r88e_reg.h>
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static void
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r88e_crystalcap_write(struct rtwn_softc *sc)
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{
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struct r92c_softc *rs = sc->sc_priv;
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uint32_t reg;
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uint8_t val;
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val = rs->crystalcap & 0x3f;
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reg = rtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
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rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
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RW(reg, R92C_AFE_XTAL_CTRL_ADDR, val | val << 6));
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}
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void
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r88e_init_bb(struct rtwn_softc *sc)
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{
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/* Enable BB and RF. */
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rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
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R92C_SYS_FUNC_EN_DIO_RF);
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rtwn_write_1(sc, R92C_RF_CTRL,
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R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
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rtwn_write_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
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R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
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r92c_init_bb_common(sc);
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rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
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rtwn_delay(sc, 1);
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rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
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rtwn_delay(sc, 1);
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r88e_crystalcap_write(sc);
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}
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int
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r88e_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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int ntries;
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip power up\n");
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return (ETIMEDOUT);
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}
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/* Reset BB. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
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R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
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RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
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/* Disable HWPDN. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APDM_HPDN, 0, 1));
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/* Disable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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0, R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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/* Enable LDO normal mode. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
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R92C_LPLDO_CTRL_SLEEP, 0));
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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return (0);
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#undef RTWN_CHK
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}
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