a544afcdc9
This adds the current thread ID to each logged register and mark entry, allowing for easier debugging of concurrent/overlapping NIC operations.
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AH_DECODE_H_
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#define _ATH_AH_DECODE_H_
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/*
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* Register tracing support.
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*
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* Setting hw.ath.hal.alq=1 enables tracing of all register reads and
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* writes to the file /tmp/ath_hal.log. The file format is a simple
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* fixed-size array of records. When done logging set hw.ath.hal.alq=0
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* and then decode the file with the arcode program (that is part of the
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* HAL). If you start+stop tracing the data will be appended to an
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* existing file.
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*/
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struct athregrec {
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uint32_t threadid;
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uint32_t op : 8,
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reg : 24;
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uint32_t val;
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};
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enum {
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OP_READ = 0, /* register read */
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OP_WRITE = 1, /* register write */
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OP_DEVICE = 2, /* device identification */
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OP_MARK = 3, /* application marker */
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};
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enum {
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AH_MARK_RESET, /* ar*Reset entry, bChannelChange */
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AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */
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AH_MARK_RESET_DONE, /* ar*Reset exit, error code */
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AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */
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AH_MARK_PERCAL, /* ar*PerCalibration, channel num */
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AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */
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AH_MARK_ANI_RESET, /* ar*AniReset, opmode */
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AH_MARK_ANI_POLL, /* ar*AniReset, listen time */
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AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */
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AH_MARK_RX_CTL, /* RX DMA control */
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};
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enum {
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AH_MARK_RX_CTL_PCU_START,
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AH_MARK_RX_CTL_PCU_STOP,
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AH_MARK_RX_CTL_DMA_START,
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AH_MARK_RX_CTL_DMA_STOP,
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AH_MARK_RX_CTL_DMA_STOP_ERR,
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};
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#endif /* _ATH_AH_DECODE_H_ */
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