5ee171d264
Also, while here, run up to 32 interrupt sources on APIC systems. Normalize INTREN/INTRDIS so they are the same on both UP and SMP systems rather than sometimes a macro, and sometimes a function. Reviewed by: jhb, jakeb
169 lines
4.9 KiB
ArmAsm
169 lines
4.9 KiB
ArmAsm
/*-
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* Copyright (c) 1997, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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.data
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ALIGN_DATA
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/*
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* Note:
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* This is the UP equivilant of _imen.
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* It is OPAQUE, and must NOT be accessed directly.
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* It MUST be accessed along with the IO APIC as a 'critical region'.
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* Accessed by:
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* INTREN()
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* INTRDIS()
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* imen_dump()
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*/
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.p2align 2 /* MUST be 32bit aligned */
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.globl _apic_imen
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_apic_imen:
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.long HWI_MASK
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.text
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SUPERALIGN_TEXT
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/******************************************************************************
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* XXX FIXME: figure out where these belong.
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*/
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/* this nonsense is to verify that masks ALWAYS have 1 and only 1 bit set */
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#define QUALIFY_MASKS_NOT
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#ifdef QUALIFY_MASKS
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#define QUALIFY_MASK \
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btrl %ecx, %eax ; \
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andl %eax, %eax ; \
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jz 1f ; \
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pushl $bad_mask ; \
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call _panic ; \
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1:
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bad_mask: .asciz "bad mask"
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#else
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#define QUALIFY_MASK
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#endif
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/*
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* (soon to be) MP-safe function to clear ONE INT mask bit.
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* The passed arg is a 32bit u_int MASK.
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* It sets the associated bit in _apic_imen.
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* It sets the mask bit of the associated IO APIC register.
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*/
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ENTRY(INTREN)
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pushfl /* save state of EI flag */
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cli /* prevent recursion */
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IMASK_LOCK /* enter critical reg */
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movl 8(%esp), %eax /* mask into %eax */
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bsfl %eax, %ecx /* get pin index */
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btrl %ecx, _apic_imen /* update _apic_imen */
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QUALIFY_MASK
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shll $4, %ecx
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movl CNAME(int_to_apicintpin) + 8(%ecx), %edx
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movl CNAME(int_to_apicintpin) + 12(%ecx), %ecx
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testl %edx, %edx
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jz 1f
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movl %ecx, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the target register data */
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andl $~IOART_INTMASK, %eax /* clear mask bit */
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movl %eax, 16(%edx) /* write the APIC register data */
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1:
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IMASK_UNLOCK /* exit critical reg */
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popfl /* restore old state of EI flag */
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ret
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/*
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* (soon to be) MP-safe function to set ONE INT mask bit.
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* The passed arg is a 32bit u_int MASK.
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* It clears the associated bit in _apic_imen.
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* It clears the mask bit of the associated IO APIC register.
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*/
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ENTRY(INTRDIS)
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pushfl /* save state of EI flag */
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cli /* prevent recursion */
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IMASK_LOCK /* enter critical reg */
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movl 8(%esp), %eax /* mask into %eax */
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bsfl %eax, %ecx /* get pin index */
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btsl %ecx, _apic_imen /* update _apic_imen */
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QUALIFY_MASK
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shll $4, %ecx
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movl CNAME(int_to_apicintpin) + 8(%ecx), %edx
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movl CNAME(int_to_apicintpin) + 12(%ecx), %ecx
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testl %edx, %edx
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jz 1f
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movl %ecx, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the target register data */
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orl $IOART_INTMASK, %eax /* set mask bit */
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movl %eax, 16(%edx) /* write the APIC register data */
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1:
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IMASK_UNLOCK /* exit critical reg */
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popfl /* restore old state of EI flag */
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ret
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/******************************************************************************
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*
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*/
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/*
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* u_int io_apic_write(int apic, int select);
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*/
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ENTRY(io_apic_read)
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movl 4(%esp), %ecx /* APIC # */
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movl _ioapic, %eax
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movl (%eax,%ecx,4), %edx /* APIC base register address */
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movl 8(%esp), %eax /* target register index */
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movl %eax, (%edx) /* write the target register index */
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movl 16(%edx), %eax /* read the APIC register data */
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ret /* %eax = register value */
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/*
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* void io_apic_write(int apic, int select, int value);
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*/
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ENTRY(io_apic_write)
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movl 4(%esp), %ecx /* APIC # */
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movl _ioapic, %eax
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movl (%eax,%ecx,4), %edx /* APIC base register address */
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movl 8(%esp), %eax /* target register index */
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movl %eax, (%edx) /* write the target register index */
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movl 12(%esp), %eax /* target register value */
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movl %eax, 16(%edx) /* write the APIC register data */
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ret /* %eax = void */
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/*
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* Send an EOI to the local APIC.
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*/
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ENTRY(apic_eoi)
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movl $0, _lapic+0xb0
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ret
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