312 lines
10 KiB
C
312 lines
10 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcivar.h,v 1.31 1999/05/11 07:55:32 peter Exp $
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*
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*/
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#ifndef _PCIVAR_H_
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#define _PCIVAR_H_
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#ifndef PCI_COMPAT
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#define PCI_COMPAT
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#endif
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#include <pci/pci_ioctl.h> /* XXX KDM */
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#include <sys/queue.h>
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/* some PCI bus constants */
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#define PCI_BUSMAX 255 /* highest supported bus number */
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#define PCI_SLOTMAX 31 /* highest supported slot number */
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#define PCI_FUNCMAX 7 /* highest supported function number */
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#define PCI_REGMAX 255 /* highest supported config register addr. */
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#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
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#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
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#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
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/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
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#ifdef PCI_A64
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typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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#else
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typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
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#endif
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/* map register information */
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typedef struct {
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u_int32_t base;
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u_int8_t type;
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#define PCI_MAPMEM 0x01 /* memory map */
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#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
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#define PCI_MAPPORT 0x04 /* port map */
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int8_t reg; /* offset of map register in config space */
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/* u_int8_t dummy;*/
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struct resource *res; /* handle from resource manager */
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} pcimap;
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/* config header information common to all header types */
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typedef struct pcicfg {
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struct device *dev; /* device which owns this */
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pcimap *map; /* pointer to array of PCI maps */
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void *hdrspec; /* pointer to header type specific data */
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struct resource *irqres; /* resource descriptor for interrupt mapping */
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u_int16_t subvendor; /* card vendor ID */
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u_int16_t subdevice; /* card device ID, assigned by card vendor */
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u_int16_t vendor; /* chip vendor ID */
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u_int16_t device; /* chip device ID, assigned by chip vendor */
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u_int16_t cmdreg; /* disable/enable chip and PCI options */
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u_int16_t statreg; /* supported PCI features and error state */
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u_int8_t baseclass; /* chip PCI class */
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u_int8_t subclass; /* chip PCI subclass */
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u_int8_t progif; /* chip PCI programming interface */
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u_int8_t revid; /* chip revision ID */
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u_int8_t hdrtype; /* chip config header type */
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u_int8_t cachelnsz; /* cache line size in 4byte units */
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u_int8_t intpin; /* PCI interrupt pin */
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u_int8_t intline; /* interrupt line (IRQ for PC arch) */
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u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
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u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
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u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
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u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
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u_int8_t nummaps; /* actual number of PCI maps used */
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u_int8_t bus; /* config space bus address */
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u_int8_t slot; /* config space slot address */
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u_int8_t func; /* config space function number */
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u_int8_t secondarybus; /* bus on secondary side of bridge, if any */
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u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */
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} pcicfgregs;
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/* additional type 1 device config header information (PCI to PCI bridge) */
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#ifdef PCI_A64
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#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
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#else
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#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
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#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
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#endif /* PCI_A64 */
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#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
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#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
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typedef struct {
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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u_int32_t membase; /* base address of memory window */
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u_int32_t memlimit; /* topmost address of memory window */
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u_int32_t iobase; /* base address of port window */
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u_int32_t iolimit; /* topmost address of port window */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* CardBus latency timer */
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} pcih1cfgregs;
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/* additional type 2 device config header information (CardBus bridge) */
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typedef struct {
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u_int32_t membase0; /* base address of memory window */
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u_int32_t memlimit0; /* topmost address of memory window */
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u_int32_t membase1; /* base address of memory window */
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u_int32_t memlimit1; /* topmost address of memory window */
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u_int32_t iobase0; /* base address of port window */
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u_int32_t iolimit0; /* topmost address of port window */
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u_int32_t iobase1; /* base address of port window */
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u_int32_t iolimit1; /* topmost address of port window */
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u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
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u_int16_t secstat; /* secondary bus status register */
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u_int16_t bridgectl; /* bridge control register */
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u_int8_t seclat; /* CardBus latency timer */
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} pcih2cfgregs;
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/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */
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typedef struct pciattach {
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int unit;
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int pcibushigh;
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struct pciattach *next;
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} pciattach;
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struct pci_devinfo {
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STAILQ_ENTRY(pci_devinfo) pci_links;
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pcicfgregs cfg;
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struct pci_conf conf;
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};
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extern u_int32_t pci_numdevs;
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/* externally visible functions */
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const char *ide_pci_match(struct device *dev);
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/* low level PCI config register functions provided by pcibus.c */
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int pci_cfgread (pcicfgregs *cfg, int reg, int bytes);
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void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
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#ifdef __alpha__
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vm_offset_t pci_cvt_to_dense (vm_offset_t);
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vm_offset_t pci_cvt_to_bwx (vm_offset_t);
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#endif /* __alpha__ */
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#ifdef _SYS_BUS_H_
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#include "pci_if.h"
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enum pci_device_ivars {
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PCI_IVAR_SUBVENDOR,
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PCI_IVAR_SUBDEVICE,
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PCI_IVAR_VENDOR,
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PCI_IVAR_DEVICE,
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PCI_IVAR_DEVID,
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PCI_IVAR_CLASS,
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PCI_IVAR_SUBCLASS,
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PCI_IVAR_PROGIF,
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PCI_IVAR_REVID,
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PCI_IVAR_INTPIN,
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PCI_IVAR_IRQ,
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PCI_IVAR_BUS,
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PCI_IVAR_SLOT,
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PCI_IVAR_FUNCTION,
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PCI_IVAR_SECONDARYBUS,
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PCI_IVAR_SUBORDINATEBUS,
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};
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/*
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* Simplified accessors for pci devices
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*/
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#define PCI_ACCESSOR(A, B, T) \
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\
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static __inline T pci_get_ ## A(device_t dev) \
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{ \
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uintptr_t v; \
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BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \
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return (T) v; \
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} \
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\
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static __inline void pci_set_ ## A(device_t dev, T t) \
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{ \
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u_long v = (u_long) t; \
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BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \
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}
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PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
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PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
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PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
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PCI_ACCESSOR(device, DEVICE, u_int16_t)
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PCI_ACCESSOR(devid, DEVID, u_int32_t)
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PCI_ACCESSOR(class, CLASS, u_int8_t)
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PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
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PCI_ACCESSOR(progif, PROGIF, u_int8_t)
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PCI_ACCESSOR(revid, REVID, u_int8_t)
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PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
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PCI_ACCESSOR(irq, IRQ, u_int8_t)
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PCI_ACCESSOR(bus, BUS, u_int8_t)
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PCI_ACCESSOR(slot, SLOT, u_int8_t)
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PCI_ACCESSOR(function, FUNCTION, u_int8_t)
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PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t)
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PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t)
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static __inline u_int32_t
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pci_read_config(device_t dev, int reg, int width)
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{
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return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
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}
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static __inline void
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pci_write_config(device_t dev, int reg, u_int32_t val, int width)
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{
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PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
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}
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#endif
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/* for compatibility to FreeBSD-2.2 version of PCI code */
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#ifdef PCI_COMPAT
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typedef pcicfgregs *pcici_t;
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typedef unsigned pcidi_t;
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typedef void pci_inthand_t(void *arg);
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#define pci_max_burst_len (3)
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/* just copied from old PCI code for now ... */
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extern int pci_mechanism;
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struct pci_device {
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char* pd_name;
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const char* (*pd_probe ) (pcici_t tag, pcidi_t type);
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void (*pd_attach) (pcici_t tag, int unit);
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u_long *pd_count;
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int (*pd_shutdown) (int, int);
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};
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#ifdef __i386__
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typedef u_short pci_port_t;
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#else
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typedef u_int pci_port_t;
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#endif
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u_long pci_conf_read (pcici_t tag, u_long reg);
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void pci_conf_write (pcici_t tag, u_long reg, u_long data);
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int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
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int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
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int pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
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int pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
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int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg,
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intrmask_t *maskptr);
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int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg,
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intrmask_t *maskptr, u_int flags);
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int pci_unmap_int (pcici_t tag);
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struct module;
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int compat_pci_handler (struct module *, int, void *);
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#define COMPAT_PCI_DRIVER(name, pcidata) \
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static moduledata_t name##_mod = { \
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#name, \
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compat_pci_handler, \
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&pcidata \
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}; \
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DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)
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#endif /* PCI_COMPAT */
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#endif /* _PCIVAR_H_ */
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