3503cf99e3
chipsets. Reviewed by: sam
602 lines
16 KiB
C
602 lines
16 KiB
C
/* $OpenBSD: if_uathreg.h,v 1.2 2006/09/18 16:34:23 damien Exp $ */
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2006
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* Damien Bergamini <damien.bergamini@free.fr>
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* Copyright (c) 2006 Sam Leffler, Errno Consulting
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define UATH_CONFIG_INDEX 0
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#define UATH_IFACE_INDEX 0
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/* all fields are big endian */
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struct uath_fwblock {
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uint32_t flags;
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#define UATH_WRITE_BLOCK (1 << 4)
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uint32_t len;
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#define UATH_MAX_FWBLOCK_SIZE 2048
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uint32_t total;
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uint32_t remain;
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uint32_t rxtotal;
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uint32_t pad[123];
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} __packed;
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#define UATH_MAX_CMDSZ 512
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/*
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* Messages are passed in Target Endianness. All fixed-size
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* fields of a WDS Control Message are treated as 32-bit
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* values and Control Msgs are guaranteed to be 32-bit aligned.
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*
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* The format of a WDS Control Message is as follows:
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* Message Length 32 bits
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* Message Opcode 32 bits
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* Message ID 32 bits
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* parameter 1
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* parameter 2
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* ...
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*
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* A variable-length parameter, or a parmeter that is larger than
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* 32 bits is passed as <length, data> pair, where length is a
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* 32-bit quantity and data is padded to 32 bits.
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*/
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struct uath_cmd_hdr {
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uint32_t len; /* msg length including header */
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uint32_t code; /* operation code */
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/* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */
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/* messages from Host -> Target */
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#define WDCMSG_HOST_AVAILABLE 0x01
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#define WDCMSG_BIND 0x02
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#define WDCMSG_TARGET_RESET 0x03
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#define WDCMSG_TARGET_GET_CAPABILITY 0x04
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#define WDCMSG_TARGET_SET_CONFIG 0x05
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#define WDCMSG_TARGET_GET_STATUS 0x06
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#define WDCMSG_TARGET_GET_STATS 0x07
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#define WDCMSG_TARGET_START 0x08
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#define WDCMSG_TARGET_STOP 0x09
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#define WDCMSG_TARGET_ENABLE 0x0a
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#define WDCMSG_TARGET_DISABLE 0x0b
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#define WDCMSG_CREATE_CONNECTION 0x0c
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#define WDCMSG_UPDATE_CONNECT_ATTR 0x0d
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#define WDCMSG_DELETE_CONNECT 0x0e
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#define WDCMSG_SEND 0x0f
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#define WDCMSG_FLUSH 0x10
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/* messages from Target -> Host */
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#define WDCMSG_STATS_UPDATE 0x11
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#define WDCMSG_BMISS 0x12
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#define WDCMSG_DEVICE_AVAIL 0x13
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#define WDCMSG_SEND_COMPLETE 0x14
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#define WDCMSG_DATA_AVAIL 0x15
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#define WDCMSG_SET_PWR_MODE 0x16
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#define WDCMSG_BMISS_ACK 0x17
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#define WDCMSG_SET_LED_STEADY 0x18
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#define WDCMSG_SET_LED_BLINK 0x19
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/* more messages */
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#define WDCMSG_SETUP_BEACON_DESC 0x1a
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#define WDCMSG_BEACON_INIT 0x1b
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#define WDCMSG_RESET_KEY_CACHE 0x1c
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#define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d
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#define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e
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#define WDCMSG_SET_DECOMP_MASK 0x1f
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#define WDCMSG_SET_REGULATORY_DOMAIN 0x20
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#define WDCMSG_SET_LED_STATE 0x21
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#define WDCMSG_WRITE_ASSOCID 0x22
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#define WDCMSG_SET_STA_BEACON_TIMERS 0x23
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#define WDCMSG_GET_TSF 0x24
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#define WDCMSG_RESET_TSF 0x25
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#define WDCMSG_SET_ADHOC_MODE 0x26
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#define WDCMSG_SET_BASIC_RATE 0x27
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#define WDCMSG_MIB_CONTROL 0x28
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#define WDCMSG_GET_CHANNEL_DATA 0x29
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#define WDCMSG_GET_CUR_RSSI 0x2a
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#define WDCMSG_SET_ANTENNA_SWITCH 0x2b
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#define WDCMSG_USE_SHORT_SLOT_TIME 0x2f
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#define WDCMSG_SET_POWER_MODE 0x30
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#define WDCMSG_SETUP_PSPOLL_DESC 0x31
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#define WDCMSG_SET_RX_MULTICAST_FILTER 0x32
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#define WDCMSG_RX_FILTER 0x33
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#define WDCMSG_PER_CALIBRATION 0x34
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#define WDCMSG_RESET 0x35
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#define WDCMSG_DISABLE 0x36
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#define WDCMSG_PHY_DISABLE 0x37
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#define WDCMSG_SET_TX_POWER_LIMIT 0x38
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#define WDCMSG_SET_TX_QUEUE_PARAMS 0x39
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#define WDCMSG_SETUP_TX_QUEUE 0x3a
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#define WDCMSG_RELEASE_TX_QUEUE 0x3b
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#define WDCMSG_SET_DEFAULT_KEY 0x43
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uint32_t msgid; /* msg id (supplied by host) */
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uint32_t magic; /* response desired/target status */
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uint32_t debug[4]; /* debug data area */
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/* msg data follows */
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} __packed;
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struct uath_chunk {
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uint8_t seqnum; /* sequence number for ordering */
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uint8_t flags;
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#define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */
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#define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */
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#define UATH_CFLAGS_DEBUG 0x04 /* for debugging */
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uint16_t length; /* chunk size in bytes */
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/* chunk data follows */
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} __packed;
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#define UATH_RX_DUMMYSIZE 4
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/*
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* Message format for a WDCMSG_DATA_AVAIL message from Target to Host.
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*/
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struct uath_rx_desc {
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uint32_t len; /* msg length including header */
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uint32_t code; /* WDCMSG_DATA_AVAIL */
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uint32_t gennum; /* generation number */
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uint32_t status; /* start of RECEIVE_INFO */
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#define UATH_STATUS_OK 0
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#define UATH_STATUS_STOP_IN_PROGRESS 1
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#define UATH_STATUS_CRC_ERR 2
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#define UATH_STATUS_PHY_ERR 3
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#define UATH_STATUS_DECRYPT_CRC_ERR 4
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#define UATH_STATUS_DECRYPT_MIC_ERR 5
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#define UATH_STATUS_DECOMP_ERR 6
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#define UATH_STATUS_KEY_ERR 7
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#define UATH_STATUS_ERR 8
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uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */
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uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */
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uint32_t framelen; /* frame length */
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uint32_t rate; /* rx rate code */
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uint32_t antenna;
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int32_t rssi;
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uint32_t channel;
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uint32_t phyerror;
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uint32_t connix; /* key table ix for bss traffic */
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uint32_t decrypterror;
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uint32_t keycachemiss;
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uint32_t pad; /* XXX? */
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} __packed;
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struct uath_tx_desc {
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uint32_t msglen;
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uint32_t msgid; /* msg id (supplied by host) */
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uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */
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uint32_t txqid; /* tx queue id and flags */
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#define UATH_TXQID_MASK 0x0f
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#define UATH_TXQID_MINRATE 0x10 /* use min tx rate */
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#define UATH_TXQID_FF 0x20 /* content is fast frame */
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uint32_t connid; /* tx connection id */
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#define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */
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uint32_t flags; /* non-zero if response desired */
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#define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */
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uint32_t buflen; /* payload length */
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} __packed;
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struct uath_cmd_host_available {
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uint32_t sw_ver_major;
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uint32_t sw_ver_minor;
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uint32_t sw_ver_patch;
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uint32_t sw_ver_build;
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} __packed;
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#define ATH_SW_VER_MAJOR 1
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#define ATH_SW_VER_MINOR 5
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#define ATH_SW_VER_PATCH 0
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#define ATH_SW_VER_BUILD 9999
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struct uath_cmd_bind {
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uint32_t targethandle;
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uint32_t hostapiversion;
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} __packed;
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/* structure for command WDCMSG_RESET */
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struct uath_cmd_reset {
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uint32_t flags; /* channel flags */
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#define UATH_CHAN_TURBO 0x0100
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#define UATH_CHAN_CCK 0x0200
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#define UATH_CHAN_OFDM 0x0400
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#define UATH_CHAN_2GHZ 0x1000
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#define UATH_CHAN_5GHZ 0x2000
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uint32_t freq; /* channel frequency */
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uint32_t maxrdpower;
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uint32_t cfgctl;
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uint32_t twiceantennareduction;
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uint32_t channelchange;
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uint32_t keeprccontent;
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} __packed;
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/* structure for commands UATH_CMD_READ_MAC and UATH_CMD_READ_EEPROM */
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struct uath_read_mac {
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uint32_t len;
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uint8_t data[32];
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} __packed;
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/* structure for command UATH_CMD_WRITE_MAC */
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struct uath_write_mac {
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uint32_t reg;
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uint32_t len;
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uint8_t data[32];
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} __packed;
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/* structure for command UATH_CMD_STA_JOIN */
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struct uath_cmd_join_bss {
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uint32_t bssid; /* NB: use zero */
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uint32_t bssmac[2]; /* bssid mac address */
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uint32_t bsstype;
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uint32_t wlanmode;
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uint32_t beaconinterval;
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uint32_t dtiminterval;
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uint32_t cfpinterval;
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uint32_t atimwindow;
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uint32_t defaultrateix;
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uint32_t shortslottime11g;
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uint32_t sleepduration;
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uint32_t bmissthreshold;
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uint32_t tcppowerlimit;
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uint32_t quietduration;
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uint32_t quietoffset;
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uint32_t quietackctsallow;
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uint32_t bssdefaultkey; /* XXX? */
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} __packed;
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struct uath_cmd_assoc_bss {
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uint32_t bssid;
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uint32_t associd;
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} __packed;
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struct uath_cmd_start_bss {
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uint32_t bssid;
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} __packed;
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/* structure for command UATH_CMD_0C */
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struct uath_cmd_0c {
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uint32_t magic1;
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uint32_t magic2;
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uint32_t magic3;
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} __packed;
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struct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */
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uint32_t lednum;
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#define UATH_LED_LINK 0
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#define UATH_LED_ACTIVITY 1
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uint32_t ledmode;
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#define UATH_LED_OFF 0
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#define UATH_LED_ON 1
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} __packed;
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struct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */
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uint32_t lednum;
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uint32_t ledmode;
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uint32_t blinkrate;
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uint32_t slowmode;
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} __packed;
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struct uath_cmd_ledstate { /* WDCMSG_SET_LED_STATE */
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uint32_t connected;
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} __packed;
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struct uath_connkey_rec {
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uint8_t bssid[IEEE80211_ADDR_LEN];
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uint32_t keyiv;
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uint32_t extkeyiv;
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uint16_t keyflags;
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uint16_t keylen;
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uint16_t keytype; /* WEP, TKIP or AES */
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/* As far as I know, MIPS 4Kp is 32-bit processor */
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uint32_t priv;
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uint8_t keyval[32];
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uint16_t aes_keylen;
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uint8_t aes_keyval[16];
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uint8_t mic_txkeyval[8];
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uint8_t mic_rxkeyval[8];
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int64_t keyrsc[17];
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int32_t keytsc[17];
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int32_t keyexttsc[17];
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} __packed;
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/* structure for command UATH_CMD_CRYPTO */
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struct uath_cmd_crypto {
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uint32_t keyidx;
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#define UATH_DEFAULT_KEY 6
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uint32_t xorkey;
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uint32_t size;
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struct uath_connkey_rec rec;
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} __packed;
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struct uath_cmd_rateset {
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uint8_t length;
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#define UATH_MAX_NRATES 32
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uint8_t set[UATH_MAX_NRATES];
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};
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/* structure for command WDCMSG_SET_BASIC_RATE */
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struct uath_cmd_rates {
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uint32_t connid;
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uint32_t keeprccontent;
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uint32_t size;
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struct uath_cmd_rateset rateset;
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} __packed;
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enum {
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WLAN_MODE_NONE = 0,
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WLAN_MODE_11b,
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WLAN_MODE_11a,
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WLAN_MODE_11g,
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WLAN_MODE_11a_TURBO,
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WLAN_MODE_11g_TURBO,
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WLAN_MODE_11a_TURBO_PRIME,
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WLAN_MODE_11g_TURBO_PRIME,
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WLAN_MODE_11a_XR,
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WLAN_MODE_11g_XR,
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};
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struct uath_cmd_connection_attr {
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uint32_t longpreambleonly;
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struct uath_cmd_rateset rateset;
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uint32_t wlanmode;
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} __packed;
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/* structure for command WDCMSG_CREATE_CONNECTION */
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struct uath_cmd_create_connection {
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uint32_t connid;
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uint32_t bssid;
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uint32_t size;
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struct uath_cmd_connection_attr connattr;
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} __packed;
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struct uath_cmd_txq_setparams { /* WDCMSG_SET_TX_QUEUE_PARAMS */
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uint32_t qnum;
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uint32_t aifs;
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uint32_t logcwmin;
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uint32_t logcwmax;
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uint32_t bursttime;
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uint32_t qflags;
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} __packed;
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struct uath_cmd_txq_attr {
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uint32_t priority;
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uint32_t aifs;
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uint32_t logcwmin;
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uint32_t logcwmax;
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uint32_t bursttime;
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uint32_t mode;
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uint32_t qflags;
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} __packed;
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struct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */
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uint32_t qid;
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uint32_t len;
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struct uath_cmd_txq_attr attr;
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} __packed;
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struct uath_cmd_stoptxdma { /* WDCMSG_STOP_TX_DMA */
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uint32_t qnum;
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uint32_t msec;
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} __packed;
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/* structure for command UATH_CMD_31 */
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struct uath_cmd_31 {
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uint32_t magic1;
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uint32_t magic2;
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} __packed;
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struct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */
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uint32_t bits;
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#define UATH_FILTER_RX_UCAST 0x00000001
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#define UATH_FILTER_RX_MCAST 0x00000002
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#define UATH_FILTER_RX_BCAST 0x00000004
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#define UATH_FILTER_RX_CONTROL 0x00000008
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#define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */
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#define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */
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#define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */
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#define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */
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#define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */
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#define UATH_FILTER_RX_PROBE_REQ 0x00000800
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uint32_t op;
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#define UATH_FILTER_OP_INIT 0x0
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#define UATH_FILTER_OP_SET 0x1
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#define UATH_FILTER_OP_CLEAR 0x2
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#define UATH_FILTER_OP_TEMP 0x3
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#define UATH_FILTER_OP_RESTORE 0x4
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} __packed;
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struct uath_cmd_rx_mcast_filter { /* WDCMSG_SET_RX_MCAST_FILTER */
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uint32_t filter0;
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uint32_t filter1;
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} __packed;
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struct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */
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uint32_t defaultrateix;
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uint32_t associd;
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uint32_t timoffset;
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uint32_t turboprime;
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uint32_t bssid[2];
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} __packed;
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struct uath_cmd_set_stabeacon_timers { /* WDCMSG_SET_STA_BEACON_TIMERS */
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uint32_t nexttbtt;
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uint32_t nextdtim;
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uint32_t nextcfp;
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uint32_t beaconperiod;
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uint32_t dtimperiod;
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uint32_t cfpperiod;
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uint32_t cfpduration;
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uint32_t sleepduration;
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uint32_t bsmissthreshold;
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} __packed;
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enum {
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CFG_NONE, /* Sentinal to indicate "no config" */
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CFG_REG_DOMAIN, /* Regulatory Domain */
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CFG_RATE_CONTROL_ENABLE,
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CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */
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CFG_HW_TX_RETRIES,
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CFG_SW_TX_RETRIES,
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CFG_SLOW_CLOCK_ENABLE,
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CFG_COMP_PROC,
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CFG_USER_RTS_THRESHOLD,
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CFG_XR2NORM_RATE_THRESHOLD,
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CFG_XRMODE_SWITCH_COUNT,
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CFG_PROTECTION_TYPE,
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CFG_BURST_SEQ_THRESHOLD,
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CFG_ABOLT,
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CFG_IQ_LOG_COUNT_MAX,
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CFG_MODE_CTS,
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CFG_WME_ENABLED,
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CFG_GPRS_CBR_PERIOD,
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CFG_SERVICE_TYPE,
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/* MAC Address to use. Overrides EEPROM */
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CFG_MAC_ADDR,
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CFG_DEBUG_EAR,
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CFG_INIT_REGS,
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/* An ID for use in error & debug messages */
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CFG_DEBUG_ID,
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CFG_COMP_WIN_SZ,
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CFG_DIVERSITY_CTL,
|
|
CFG_TP_SCALE,
|
|
CFG_TPC_HALF_DBM5,
|
|
CFG_TPC_HALF_DBM2,
|
|
CFG_OVERRD_TX_POWER,
|
|
CFG_USE_32KHZ_CLOCK,
|
|
CFG_GMODE_PROTECTION,
|
|
CFG_GMODE_PROTECT_RATE_INDEX,
|
|
CFG_GMODE_NON_ERP_PREAMBLE,
|
|
CFG_WDC_TRANSPORT_CHUNK_SIZE,
|
|
};
|
|
|
|
enum {
|
|
/* Sentinal to indicate "no capability" */
|
|
CAP_NONE,
|
|
CAP_ALL, /* ALL capabilities */
|
|
CAP_TARGET_VERSION,
|
|
CAP_TARGET_REVISION,
|
|
CAP_MAC_VERSION,
|
|
CAP_MAC_REVISION,
|
|
CAP_PHY_REVISION,
|
|
CAP_ANALOG_5GHz_REVISION,
|
|
CAP_ANALOG_2GHz_REVISION,
|
|
/* Target supports WDC message debug features */
|
|
CAP_DEBUG_WDCMSG_SUPPORT,
|
|
|
|
CAP_REG_DOMAIN,
|
|
CAP_COUNTRY_CODE,
|
|
CAP_REG_CAP_BITS,
|
|
|
|
CAP_WIRELESS_MODES,
|
|
CAP_CHAN_SPREAD_SUPPORT,
|
|
CAP_SLEEP_AFTER_BEACON_BROKEN,
|
|
CAP_COMPRESS_SUPPORT,
|
|
CAP_BURST_SUPPORT,
|
|
CAP_FAST_FRAMES_SUPPORT,
|
|
CAP_CHAP_TUNING_SUPPORT,
|
|
CAP_TURBOG_SUPPORT,
|
|
CAP_TURBO_PRIME_SUPPORT,
|
|
CAP_DEVICE_TYPE,
|
|
CAP_XR_SUPPORT,
|
|
CAP_WME_SUPPORT,
|
|
CAP_TOTAL_QUEUES,
|
|
CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */
|
|
|
|
CAP_LOW_5GHZ_CHAN,
|
|
CAP_HIGH_5GHZ_CHAN,
|
|
CAP_LOW_2GHZ_CHAN,
|
|
CAP_HIGH_2GHZ_CHAN,
|
|
|
|
CAP_MIC_AES_CCM,
|
|
CAP_MIC_CKIP,
|
|
CAP_MIC_TKIP,
|
|
CAP_MIC_TKIP_WME,
|
|
CAP_CIPHER_AES_CCM,
|
|
CAP_CIPHER_CKIP,
|
|
CAP_CIPHER_TKIP,
|
|
|
|
CAP_TWICE_ANTENNAGAIN_5G,
|
|
CAP_TWICE_ANTENNAGAIN_2G,
|
|
};
|
|
|
|
enum {
|
|
ST_NONE, /* Sentinal to indicate "no status" */
|
|
ST_ALL,
|
|
ST_SERVICE_TYPE,
|
|
ST_WLAN_MODE,
|
|
ST_FREQ,
|
|
ST_BAND,
|
|
ST_LAST_RSSI,
|
|
ST_PS_FRAMES_DROPPED,
|
|
ST_CACHED_DEF_ANT,
|
|
ST_COUNT_OTHER_RX_ANT,
|
|
ST_USE_FAST_DIVERSITY,
|
|
ST_MAC_ADDR,
|
|
ST_RX_GENERATION_NUM,
|
|
ST_TX_QUEUE_DEPTH,
|
|
ST_SERIAL_NUMBER,
|
|
ST_WDC_TRANSPORT_CHUNK_SIZE,
|
|
};
|
|
|
|
enum {
|
|
BSS_ATTR_BEACON_INTERVAL,
|
|
BSS_ATTR_DTIM_INTERVAL,
|
|
BSS_ATTR_CFP_INTERVAL,
|
|
BSS_ATTR_CFP_MAX_DURATION,
|
|
BSS_ATTR_ATIM_WINDOW,
|
|
BSS_ATTR_DEFAULT_RATE_INDEX,
|
|
BSS_ATTR_SHORT_SLOT_TIME_11g,
|
|
BSS_ATTR_SLEEP_DURATION,
|
|
BSS_ATTR_BMISS_THRESHOLD,
|
|
BSS_ATTR_TPC_POWER_LIMIT,
|
|
BSS_ATTR_BSS_KEY_UPDATE,
|
|
};
|
|
|
|
struct uath_cmd_update_bss_attribute {
|
|
uint32_t bssid;
|
|
uint32_t attribute; /* BSS_ATTR_BEACON_INTERVAL, et al. */
|
|
uint32_t cfgsize; /* should be zero 0 */
|
|
uint32_t cfgdata;
|
|
};
|
|
|
|
struct uath_cmd_update_bss_attribute_key {
|
|
uint32_t bssid;
|
|
uint32_t attribute; /* BSS_ATTR_BSS_KEY_UPDATE */
|
|
uint32_t cfgsize; /* size of remaining data */
|
|
uint32_t bsskeyix;
|
|
uint32_t isdefaultkey;
|
|
uint32_t keyiv; /* IV generation control */
|
|
uint32_t extkeyiv; /* extended IV for TKIP & CCM */
|
|
uint32_t keyflags;
|
|
uint32_t keytype;
|
|
uint32_t initvalue; /* XXX */
|
|
uint32_t keyval[4];
|
|
uint32_t mictxkeyval[2];
|
|
uint32_t micrxkeyval[2];
|
|
uint32_t keyrsc[2];
|
|
};
|
|
|
|
enum {
|
|
TARGET_DEVICE_AWAKE,
|
|
TARGET_DEVICE_SLEEP,
|
|
TARGET_DEVICE_PWRDN,
|
|
TARGET_DEVICE_PWRSAVE,
|
|
TARGET_DEVICE_SUSPEND,
|
|
TARGET_DEVICE_RESUME,
|
|
};
|
|
|
|
#define UATH_MAX_TXBUFSZ \
|
|
(sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc) + \
|
|
IEEE80211_MAX_LEN)
|
|
|
|
/*
|
|
* it's not easy to measure how the chunk is passed into the host if the target
|
|
* passed the multi-chunks so just we check a minimal size we can imagine.
|
|
*/
|
|
#define UATH_MIN_RXBUFSZ (sizeof(struct uath_chunk))
|