809ad0530a
support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
217 lines
6.8 KiB
ArmAsm
217 lines
6.8 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $ */
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/*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Eben Upton
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#if 0
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#define Invalidate_I_cache(Rtmp1, Rtmp2) \
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mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
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#else
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/*
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* Workaround for
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*
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* Erratum 411920 in ARM1136 (fixed in r1p4)
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* Erratum 415045 in ARM1176 (fixed in r0p5?)
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*
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* - value of arg 'reg' Should Be Zero
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*/
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#define Invalidate_I_cache(Rtmp1, Rtmp2) \
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mov Rtmp1, #0; /* SBZ */ \
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mrs Rtmp2, cpsr; \
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cpsid ifa; \
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mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
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mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
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mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
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mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
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msr cpsr_cx, Rtmp2; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop; \
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nop;
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#endif
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#if 1
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#define Flush_D_cache(reg) \
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mov reg, #0; /* SBZ */ \
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mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
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mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
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#else
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#define Flush_D_cache(reg) \
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1: mov reg, #0; /* SBZ */ \
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mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
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mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
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ands reg, reg, #01; /* Check if it is clean */ \
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bne 1b; /* loop if not */ \
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mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
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#endif
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ENTRY(arm11x6_setttb)
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#ifdef PMAP_CACHE_VIVT
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Flush_D_cache(r1)
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Invalidate_I_cache(r1, r2)
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#else
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mov r1, #0
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#endif
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mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
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mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
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mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */
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RET
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ENTRY_NP(arm11x6_idcache_wbinv_all)
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Flush_D_cache(r0)
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Invalidate_I_cache(r0, r1)
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RET
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ENTRY_NP(arm11x6_dcache_wbinv_all)
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Flush_D_cache(r0)
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RET
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ENTRY_NP(arm11x6_icache_sync_all)
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Flush_D_cache(r0)
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Invalidate_I_cache(r0, r1)
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RET
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ENTRY_NP(arm11x6_flush_prefetchbuf)
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mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
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RET
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ENTRY_NP(arm11x6_icache_sync_range)
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add r1, r1, r0
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sub r1, r1, #1
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/* Erratum ARM1136 371025, workaround #2 */
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/* Erratum ARM1176 371367 */
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mrs r2, cpsr /* save the CPSR */
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cpsid ifa /* disable interrupts (irq,fiq,abort) */
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mov r3, #0
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mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
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mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
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add r3, pc, #0x24
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mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
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mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
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msr cpsr_cx, r2 /* local_irq_restore */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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ENTRY_NP(arm11x6_idcache_wbinv_range)
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add r1, r1, r0
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sub r1, r1, #1
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/* Erratum ARM1136 371025, workaround #2 */
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/* Erratum ARM1176 371367 */
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mrs r2, cpsr /* save the CPSR */
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cpsid ifa /* disable interrupts (irq,fiq,abort) */
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mov r3, #0
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mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
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mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
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add r3, pc, #0x24
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mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
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mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
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msr cpsr_cx, r2 /* local_irq_restore */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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/*
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* Preload the cache before issuing the WFI by conditionally disabling the
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* mcr intstructions the first time around the loop. Ensure the function is
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* cacheline aligned.
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*/
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.arch armv6
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.p2align 5
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ENTRY_NP(arm11x6_sleep)
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mov r0, #0
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mov r1, #2
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1:
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subs r1, #1
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nop
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mcreq p15, 0, r0, c7, c10, 4 /* data sync barrier */
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mcreq p15, 0, r0, c7, c0, 4 /* wait for interrupt */
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nop
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nop
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nop
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bne 1b
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RET
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