3c15abf75c
out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month |
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hwpmc_amd.c | ||
hwpmc_amd.h | ||
hwpmc_arm.c | ||
hwpmc_core.c | ||
hwpmc_core.h | ||
hwpmc_ia64.c | ||
hwpmc_intel.c | ||
hwpmc_logging.c | ||
hwpmc_mod.c | ||
hwpmc_pentium.c | ||
hwpmc_pentium.h | ||
hwpmc_piv.c | ||
hwpmc_piv.h | ||
hwpmc_powerpc.c | ||
hwpmc_ppro.c | ||
hwpmc_ppro.h | ||
hwpmc_sparc64.c | ||
hwpmc_tsc.c | ||
hwpmc_tsc.h | ||
hwpmc_x86.c | ||
pmc_events.h |