653 lines
14 KiB
C
653 lines
14 KiB
C
/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/pmc_mdep.h>
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#include <machine/cpu.h>
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#define CPU_ID_CORTEX_VER_MASK 0xff
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#define CPU_ID_CORTEX_VER_SHIFT 4
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static int armv7_npmcs;
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struct armv7_event_code_map {
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enum pmc_event pe_ev;
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uint8_t pe_code;
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};
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const struct armv7_event_code_map armv7_event_codes[] = {
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{ PMC_EV_ARMV7_PMNC_SW_INCR, 0x00 },
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{ PMC_EV_ARMV7_L1_ICACHE_REFILL, 0x01 },
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{ PMC_EV_ARMV7_ITLB_REFILL, 0x02 },
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{ PMC_EV_ARMV7_L1_DCACHE_REFILL, 0x03 },
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{ PMC_EV_ARMV7_L1_DCACHE_ACCESS, 0x04 },
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{ PMC_EV_ARMV7_DTLB_REFILL, 0x05 },
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{ PMC_EV_ARMV7_MEM_READ, 0x06 },
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{ PMC_EV_ARMV7_MEM_WRITE, 0x07 },
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{ PMC_EV_ARMV7_INSTR_EXECUTED, 0x08 },
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{ PMC_EV_ARMV7_EXC_TAKEN, 0x09 },
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{ PMC_EV_ARMV7_EXC_EXECUTED, 0x0A },
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{ PMC_EV_ARMV7_CID_WRITE, 0x0B },
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{ PMC_EV_ARMV7_PC_WRITE, 0x0C },
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{ PMC_EV_ARMV7_PC_IMM_BRANCH, 0x0D },
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{ PMC_EV_ARMV7_PC_PROC_RETURN, 0x0E },
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{ PMC_EV_ARMV7_MEM_UNALIGNED_ACCESS, 0x0F },
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{ PMC_EV_ARMV7_PC_BRANCH_MIS_PRED, 0x10 },
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{ PMC_EV_ARMV7_CLOCK_CYCLES, 0x11 },
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{ PMC_EV_ARMV7_PC_BRANCH_PRED, 0x12 },
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{ PMC_EV_ARMV7_MEM_ACCESS, 0x13 },
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{ PMC_EV_ARMV7_L1_ICACHE_ACCESS, 0x14 },
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{ PMC_EV_ARMV7_L1_DCACHE_WB, 0x15 },
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{ PMC_EV_ARMV7_L2_CACHE_ACCESS, 0x16 },
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{ PMC_EV_ARMV7_L2_CACHE_REFILL, 0x17 },
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{ PMC_EV_ARMV7_L2_CACHE_WB, 0x18 },
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{ PMC_EV_ARMV7_BUS_ACCESS, 0x19 },
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{ PMC_EV_ARMV7_MEM_ERROR, 0x1A },
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{ PMC_EV_ARMV7_INSTR_SPEC, 0x1B },
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{ PMC_EV_ARMV7_TTBR_WRITE, 0x1C },
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{ PMC_EV_ARMV7_BUS_CYCLES, 0x1D },
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{ PMC_EV_ARMV7_CPU_CYCLES, 0xFF },
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};
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const int armv7_event_codes_size =
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sizeof(armv7_event_codes) / sizeof(armv7_event_codes[0]);
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/*
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* Per-processor information.
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*/
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struct armv7_cpu {
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struct pmc_hw *pc_armv7pmcs;
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int cortex_ver;
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};
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static struct armv7_cpu **armv7_pcpu;
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/*
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* Performance Monitor Control Register
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*/
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static __inline uint32_t
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armv7_pmnc_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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armv7_pmnc_write(uint32_t reg)
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{
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__asm __volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (reg));
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}
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/*
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* Clock Counter Register (PMCCNTR)
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* Counts processor clock cycles.
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*/
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static __inline uint32_t
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armv7_ccnt_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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armv7_ccnt_write(uint32_t reg)
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{
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__asm __volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (reg));
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}
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/*
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* Interrupt Enable Set Register
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*/
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static __inline void
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armv7_interrupt_enable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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__asm __volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (reg));
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}
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/*
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* Interrupt Clear Set Register
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*/
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static __inline void
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armv7_interrupt_disable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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__asm __volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (reg));
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}
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/*
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* Overflow Flag Register
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*/
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static __inline uint32_t
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armv7_flag_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (reg));
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return (reg);
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}
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static __inline void
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armv7_flag_write(uint32_t reg)
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{
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__asm __volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (reg));
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}
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/*
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* Event Selection Register
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*/
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static __inline void
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armv7_evtsel_write(uint32_t reg)
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{
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__asm __volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (reg));
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}
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/*
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* PMSELR
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*/
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static __inline void
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armv7_select_counter(unsigned int pmc)
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{
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__asm __volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (pmc));
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}
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/*
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* Counter Set Enable Register
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*/
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static __inline void
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armv7_counter_enable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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__asm __volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (reg));
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}
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/*
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* Counter Clear Enable Register
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*/
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static __inline void
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armv7_counter_disable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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__asm __volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (reg));
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}
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/*
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* Performance Count Register N
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*/
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static uint32_t
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armv7_pmcn_read(unsigned int pmc)
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{
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uint32_t reg = 0;
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KASSERT(pmc < 4, ("[armv7,%d] illegal PMC number %d", __LINE__, pmc));
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armv7_select_counter(pmc);
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__asm __volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (reg));
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return (reg);
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}
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static uint32_t
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armv7_pmcn_write(unsigned int pmc, uint32_t reg)
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{
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KASSERT(pmc < 4, ("[armv7,%d] illegal PMC number %d", __LINE__, pmc));
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armv7_select_counter(pmc);
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__asm __volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (reg));
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return (reg);
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}
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static int
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armv7_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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uint32_t caps, config;
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struct armv7_cpu *pac;
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enum pmc_event pe;
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int i;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row index %d", __LINE__, ri));
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pac = armv7_pcpu[cpu];
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caps = a->pm_caps;
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if (a->pm_class != PMC_CLASS_ARMV7)
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return (EINVAL);
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pe = a->pm_ev;
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for (i = 0; i < armv7_event_codes_size; i++) {
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if (armv7_event_codes[i].pe_ev == pe) {
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config = armv7_event_codes[i].pe_code;
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break;
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}
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}
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if (i == armv7_event_codes_size)
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return EINVAL;
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pm->pm_md.pm_armv7.pm_armv7_evsel = config;
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PMCDBG(MDP,ALL,2,"armv7-allocate ri=%d -> config=0x%x", ri, config);
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return 0;
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}
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static int
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armv7_read_pmc(int cpu, int ri, pmc_value_t *v)
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{
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pmc_value_t tmp;
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struct pmc *pm;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row index %d", __LINE__, ri));
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pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
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if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
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tmp = armv7_ccnt_read();
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else
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tmp = armv7_pmcn_read(ri);
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PMCDBG(MDP,REA,2,"armv7-read id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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*v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
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else
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*v = tmp;
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return 0;
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}
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static int
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armv7_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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struct pmc *pm;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row-index %d", __LINE__, ri));
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pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
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PMCDBG(MDP,WRI,1,"armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
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armv7_ccnt_write(v);
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else
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armv7_pmcn_write(ri, v);
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return 0;
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}
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static int
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armv7_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row-index %d", __LINE__, ri));
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[armv7,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return 0;
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}
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static int
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armv7_start_pmc(int cpu, int ri)
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{
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struct pmc_hw *phw;
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uint32_t config;
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struct pmc *pm;
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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pm = phw->phw_pmc;
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config = pm->pm_md.pm_armv7.pm_armv7_evsel;
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/*
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* Configure the event selection.
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*/
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armv7_select_counter(ri);
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armv7_evtsel_write(config);
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/*
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* Enable the PMC.
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*/
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armv7_interrupt_enable(ri);
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armv7_counter_enable(ri);
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return 0;
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}
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static int
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armv7_stop_pmc(int cpu, int ri)
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{
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struct pmc_hw *phw;
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struct pmc *pm;
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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pm = phw->phw_pmc;
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/*
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* Disable the PMCs.
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*/
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armv7_counter_disable(ri);
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armv7_interrupt_disable(ri);
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return 0;
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}
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static int
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armv7_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row-index %d", __LINE__, ri));
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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KASSERT(phw->phw_pmc == NULL,
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("[armv7,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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return 0;
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}
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static int
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armv7_intr(int cpu, struct trapframe *tf)
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{
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struct armv7_cpu *pc;
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int retval, ri;
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struct pmc *pm;
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int error;
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int reg;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] CPU %d out of range", __LINE__, cpu));
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retval = 0;
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pc = armv7_pcpu[cpu];
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for (ri = 0; ri < armv7_npmcs; ri++) {
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pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
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if (pm == NULL)
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continue;
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if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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continue;
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/* Check if counter has overflowed */
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if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF)
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reg = (1 << 31);
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else
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reg = (1 << ri);
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if ((armv7_flag_read() & reg) == 0) {
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continue;
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}
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/* Clear Overflow Flag */
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armv7_flag_write(reg);
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retval = 1; /* Found an interrupting PMC. */
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if (pm->pm_state != PMC_STATE_RUNNING)
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continue;
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error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
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TRAPF_USERMODE(tf));
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if (error)
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armv7_stop_pmc(cpu, ri);
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/* Reload sampling count */
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armv7_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
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}
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return (retval);
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}
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static int
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armv7_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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char armv7_name[PMC_NAME_MAX];
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struct pmc_hw *phw;
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int error;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d], illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] row-index %d out of range", __LINE__, ri));
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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snprintf(armv7_name, sizeof(armv7_name), "ARMV7-%d", ri);
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if ((error = copystr(armv7_name, pi->pm_name, PMC_NAME_MAX,
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NULL)) != 0)
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return error;
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pi->pm_class = PMC_CLASS_ARMV7;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
|
|
pi->pm_enabled = TRUE;
|
|
*ppmc = phw->phw_pmc;
|
|
} else {
|
|
pi->pm_enabled = FALSE;
|
|
*ppmc = NULL;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
armv7_get_config(int cpu, int ri, struct pmc **ppm)
|
|
{
|
|
|
|
*ppm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* XXX don't know what we should do here.
|
|
*/
|
|
static int
|
|
armv7_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
armv7_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
armv7_pcpu_init(struct pmc_mdep *md, int cpu)
|
|
{
|
|
struct armv7_cpu *pac;
|
|
struct pmc_hw *phw;
|
|
struct pmc_cpu *pc;
|
|
uint32_t pmnc;
|
|
int first_ri;
|
|
int cpuid;
|
|
int i;
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[armv7,%d] wrong cpu number %d", __LINE__, cpu));
|
|
PMCDBG(MDP,INI,1,"armv7-init cpu=%d", cpu);
|
|
|
|
armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC,
|
|
M_WAITOK|M_ZERO);
|
|
|
|
cpuid = cpu_ident();
|
|
pac->cortex_ver = (cpuid >> CPU_ID_CORTEX_VER_SHIFT) & \
|
|
CPU_ID_CORTEX_VER_MASK;
|
|
|
|
pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs,
|
|
M_PMC, M_WAITOK|M_ZERO);
|
|
pc = pmc_pcpu[cpu];
|
|
first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7].pcd_ri;
|
|
KASSERT(pc != NULL, ("[armv7,%d] NULL per-cpu pointer", __LINE__));
|
|
|
|
for (i = 0, phw = pac->pc_armv7pmcs; i < armv7_npmcs; i++, phw++) {
|
|
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
|
PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
|
|
phw->phw_pmc = NULL;
|
|
pc->pc_hwpmcs[i + first_ri] = phw;
|
|
}
|
|
|
|
/* Enable unit */
|
|
pmnc = armv7_pmnc_read();
|
|
pmnc |= ARMV7_PMNC_ENABLE;
|
|
armv7_pmnc_write(pmnc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
armv7_pcpu_fini(struct pmc_mdep *md, int cpu)
|
|
{
|
|
uint32_t pmnc;
|
|
|
|
pmnc = armv7_pmnc_read();
|
|
pmnc &= ~ARMV7_PMNC_ENABLE;
|
|
armv7_pmnc_write(pmnc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct pmc_mdep *
|
|
pmc_armv7_initialize()
|
|
{
|
|
struct pmc_mdep *pmc_mdep;
|
|
struct pmc_classdep *pcd;
|
|
int reg;
|
|
|
|
reg = armv7_pmnc_read();
|
|
|
|
armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \
|
|
ARMV7_PMNC_N_MASK;
|
|
|
|
PMCDBG(MDP,INI,1,"armv7-init npmcs=%d", armv7_npmcs);
|
|
|
|
/*
|
|
* Allocate space for pointers to PMC HW descriptors and for
|
|
* the MDEP structure used by MI code.
|
|
*/
|
|
armv7_pcpu = malloc(sizeof(struct armv7_cpu *) * pmc_cpu_max(),
|
|
M_PMC, M_WAITOK | M_ZERO);
|
|
|
|
/* Just one class */
|
|
pmc_mdep = pmc_mdep_alloc(1);
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV7;
|
|
|
|
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7];
|
|
pcd->pcd_caps = ARMV7_PMC_CAPS;
|
|
pcd->pcd_class = PMC_CLASS_ARMV7;
|
|
pcd->pcd_num = armv7_npmcs;
|
|
pcd->pcd_ri = pmc_mdep->pmd_npmc;
|
|
pcd->pcd_width = 32;
|
|
|
|
pcd->pcd_allocate_pmc = armv7_allocate_pmc;
|
|
pcd->pcd_config_pmc = armv7_config_pmc;
|
|
pcd->pcd_pcpu_fini = armv7_pcpu_fini;
|
|
pcd->pcd_pcpu_init = armv7_pcpu_init;
|
|
pcd->pcd_describe = armv7_describe;
|
|
pcd->pcd_get_config = armv7_get_config;
|
|
pcd->pcd_read_pmc = armv7_read_pmc;
|
|
pcd->pcd_release_pmc = armv7_release_pmc;
|
|
pcd->pcd_start_pmc = armv7_start_pmc;
|
|
pcd->pcd_stop_pmc = armv7_stop_pmc;
|
|
pcd->pcd_write_pmc = armv7_write_pmc;
|
|
|
|
pmc_mdep->pmd_intr = armv7_intr;
|
|
pmc_mdep->pmd_switch_in = armv7_switch_in;
|
|
pmc_mdep->pmd_switch_out = armv7_switch_out;
|
|
|
|
pmc_mdep->pmd_npmc += armv7_npmcs;
|
|
|
|
return (pmc_mdep);
|
|
}
|
|
|
|
void
|
|
pmc_armv7_finalize(struct pmc_mdep *md)
|
|
{
|
|
|
|
}
|