3226c13778
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
91 lines
2.8 KiB
C
91 lines
2.8 KiB
C
/*-
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* Copyright (C) 2007 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_uart.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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bus_space_tag_t uart_bus_space_io;
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bus_space_tag_t uart_bus_space_mem;
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int
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uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
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{
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return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
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}
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int
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uart_cpu_getdev(int devtype, struct uart_devinfo *di)
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{
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struct uart_class *class = &uart_ns8250_class;
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/*
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* If env specification for UART exists it takes precedence:
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* hw.uart.console="mm:0xf1012000" or similar
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*/
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if (uart_getenv(devtype, di, class) == 0)
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return (0);
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/*
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* Fall back to default UART0 console settings
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*/
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di->ops = uart_getops(class);
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di->bas.chan = 0;
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di->bas.bst = obio_tag;
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if (bus_space_map(di->bas.bst, MV_UART0_BASE, MV_UART_SIZE,
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0, &di->bas.bsh) != 0)
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return (ENXIO);
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di->baudrate = 115200;
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di->bas.regshft = 2;
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di->bas.rclk = get_tclk();
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di->databits = 8;
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di->stopbits = 1;
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di->parity = UART_PARITY_NONE;
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uart_bus_space_mem = obio_tag;
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uart_bus_space_io = NULL;
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return (0);
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}
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