524 lines
11 KiB
C
524 lines
11 KiB
C
/*-
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* Copyright (c) 2007 Marcel Moolenaar
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IA64_CPU_H_
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#define _MACHINE_IA64_CPU_H_
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/*
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* Local Interrupt ID.
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*/
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#define IA64_LID_GET_SAPIC_ID(x) ((u_int)((x) >> 16) & 0xffff)
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#define IA64_LID_SET_SAPIC_ID(x) ((u_int)((x) & 0xffff) << 16)
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/*
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* Definition of DCR bits.
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*/
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#define IA64_DCR_PP 0x0000000000000001
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#define IA64_DCR_BE 0x0000000000000002
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#define IA64_DCR_LC 0x0000000000000004
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#define IA64_DCR_DM 0x0000000000000100
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#define IA64_DCR_DP 0x0000000000000200
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#define IA64_DCR_DK 0x0000000000000400
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#define IA64_DCR_DX 0x0000000000000800
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#define IA64_DCR_DR 0x0000000000001000
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#define IA64_DCR_DA 0x0000000000002000
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#define IA64_DCR_DD 0x0000000000004000
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#define IA64_DCR_DEFAULT \
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(IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
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IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
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/*
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* Definition of PSR and IPSR bits.
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*/
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#define IA64_PSR_BE 0x0000000000000002
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#define IA64_PSR_UP 0x0000000000000004
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#define IA64_PSR_AC 0x0000000000000008
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#define IA64_PSR_MFL 0x0000000000000010
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#define IA64_PSR_MFH 0x0000000000000020
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#define IA64_PSR_IC 0x0000000000002000
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#define IA64_PSR_I 0x0000000000004000
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#define IA64_PSR_PK 0x0000000000008000
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#define IA64_PSR_DT 0x0000000000020000
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#define IA64_PSR_DFL 0x0000000000040000
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#define IA64_PSR_DFH 0x0000000000080000
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#define IA64_PSR_SP 0x0000000000100000
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#define IA64_PSR_PP 0x0000000000200000
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#define IA64_PSR_DI 0x0000000000400000
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#define IA64_PSR_SI 0x0000000000800000
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#define IA64_PSR_DB 0x0000000001000000
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#define IA64_PSR_LP 0x0000000002000000
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#define IA64_PSR_TB 0x0000000004000000
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#define IA64_PSR_RT 0x0000000008000000
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#define IA64_PSR_CPL 0x0000000300000000
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#define IA64_PSR_CPL_KERN 0x0000000000000000
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#define IA64_PSR_CPL_1 0x0000000100000000
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#define IA64_PSR_CPL_2 0x0000000200000000
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#define IA64_PSR_CPL_USER 0x0000000300000000
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#define IA64_PSR_IS 0x0000000400000000
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#define IA64_PSR_MC 0x0000000800000000
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#define IA64_PSR_IT 0x0000001000000000
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#define IA64_PSR_ID 0x0000002000000000
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#define IA64_PSR_DA 0x0000004000000000
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#define IA64_PSR_DD 0x0000008000000000
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#define IA64_PSR_SS 0x0000010000000000
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#define IA64_PSR_RI 0x0000060000000000
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#define IA64_PSR_RI_0 0x0000000000000000
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#define IA64_PSR_RI_1 0x0000020000000000
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#define IA64_PSR_RI_2 0x0000040000000000
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#define IA64_PSR_ED 0x0000080000000000
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#define IA64_PSR_BN 0x0000100000000000
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#define IA64_PSR_IA 0x0000200000000000
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/*
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* Definition of ISR bits.
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*/
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#define IA64_ISR_CODE 0x000000000000ffff
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#define IA64_ISR_VECTOR 0x0000000000ff0000
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#define IA64_ISR_X 0x0000000100000000
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#define IA64_ISR_W 0x0000000200000000
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#define IA64_ISR_R 0x0000000400000000
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#define IA64_ISR_NA 0x0000000800000000
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#define IA64_ISR_SP 0x0000001000000000
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#define IA64_ISR_RS 0x0000002000000000
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#define IA64_ISR_IR 0x0000004000000000
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#define IA64_ISR_NI 0x0000008000000000
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#define IA64_ISR_SO 0x0000010000000000
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#define IA64_ISR_EI 0x0000060000000000
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#define IA64_ISR_EI_0 0x0000000000000000
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#define IA64_ISR_EI_1 0x0000020000000000
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#define IA64_ISR_EI_2 0x0000040000000000
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#define IA64_ISR_ED 0x0000080000000000
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/*
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* Vector numbers for various ia64 interrupts.
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*/
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#define IA64_VEC_VHPT 0
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#define IA64_VEC_ITLB 1
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#define IA64_VEC_DTLB 2
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#define IA64_VEC_ALT_ITLB 3
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#define IA64_VEC_ALT_DTLB 4
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#define IA64_VEC_NESTED_DTLB 5
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#define IA64_VEC_IKEY_MISS 6
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#define IA64_VEC_DKEY_MISS 7
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#define IA64_VEC_DIRTY_BIT 8
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#define IA64_VEC_INST_ACCESS 9
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#define IA64_VEC_DATA_ACCESS 10
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#define IA64_VEC_BREAK 11
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#define IA64_VEC_EXT_INTR 12
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#define IA64_VEC_PAGE_NOT_PRESENT 20
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#define IA64_VEC_KEY_PERMISSION 21
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#define IA64_VEC_INST_ACCESS_RIGHTS 22
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#define IA64_VEC_DATA_ACCESS_RIGHTS 23
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#define IA64_VEC_GENERAL_EXCEPTION 24
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#define IA64_VEC_DISABLED_FP 25
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#define IA64_VEC_NAT_CONSUMPTION 26
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#define IA64_VEC_SPECULATION 27
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#define IA64_VEC_DEBUG 29
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#define IA64_VEC_UNALIGNED_REFERENCE 30
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#define IA64_VEC_UNSUPP_DATA_REFERENCE 31
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#define IA64_VEC_FLOATING_POINT_FAULT 32
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#define IA64_VEC_FLOATING_POINT_TRAP 33
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#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
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#define IA64_VEC_TAKEN_BRANCH_TRAP 35
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#define IA64_VEC_SINGLE_STEP_TRAP 36
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#define IA64_VEC_IA32_EXCEPTION 45
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#define IA64_VEC_IA32_INTERCEPT 46
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#define IA64_VEC_IA32_INTERRUPT 47
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/*
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* IA-32 exceptions.
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*/
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#define IA32_EXCEPTION_DIVIDE 0
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#define IA32_EXCEPTION_DEBUG 1
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#define IA32_EXCEPTION_BREAK 3
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#define IA32_EXCEPTION_OVERFLOW 4
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#define IA32_EXCEPTION_BOUND 5
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#define IA32_EXCEPTION_DNA 7
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#define IA32_EXCEPTION_NOT_PRESENT 11
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#define IA32_EXCEPTION_STACK_FAULT 12
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#define IA32_EXCEPTION_GPFAULT 13
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#define IA32_EXCEPTION_FPERROR 16
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#define IA32_EXCEPTION_ALIGNMENT_CHECK 17
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#define IA32_EXCEPTION_STREAMING_SIMD 19
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#define IA32_INTERCEPT_INSTRUCTION 0
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#define IA32_INTERCEPT_GATE 1
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#define IA32_INTERCEPT_SYSTEM_FLAG 2
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#define IA32_INTERCEPT_LOCK 4
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#ifndef LOCORE
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/*
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* Various special ia64 instructions.
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*/
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/*
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* Memory Fence.
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*/
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static __inline void
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ia64_mf(void)
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{
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__asm __volatile("mf");
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}
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static __inline void
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ia64_mf_a(void)
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{
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__asm __volatile("mf.a");
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}
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/*
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* Flush Cache.
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*/
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static __inline void
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ia64_fc(uint64_t va)
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{
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__asm __volatile("fc %0" :: "r"(va));
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}
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static __inline void
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ia64_fc_i(uint64_t va)
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{
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__asm __volatile("fc.i %0" :: "r"(va));
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}
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/*
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* Sync instruction stream.
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*/
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static __inline void
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ia64_sync_i(void)
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{
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__asm __volatile("sync.i");
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}
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/*
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* Calculate address in VHPT for va.
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*/
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static __inline uint64_t
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ia64_thash(uint64_t va)
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{
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uint64_t result;
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__asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
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return result;
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}
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/*
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* Calculate VHPT tag for va.
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*/
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static __inline uint64_t
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ia64_ttag(uint64_t va)
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{
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uint64_t result;
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__asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
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return result;
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}
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/*
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* Convert virtual address to physical.
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*/
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static __inline uint64_t
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ia64_tpa(uint64_t va)
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{
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uint64_t result;
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__asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
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return result;
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}
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/*
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* Generate a ptc.e instruction.
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*/
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static __inline void
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ia64_ptc_e(uint64_t v)
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{
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__asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v));
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}
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/*
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* Generate a ptc.g instruction.
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*/
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static __inline void
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ia64_ptc_g(uint64_t va, uint64_t log2size)
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{
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__asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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}
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/*
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* Generate a ptc.ga instruction.
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*/
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static __inline void
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ia64_ptc_ga(uint64_t va, uint64_t log2size)
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{
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__asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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}
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/*
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* Generate a ptc.l instruction.
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*/
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static __inline void
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ia64_ptc_l(uint64_t va, uint64_t log2size)
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{
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__asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
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}
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/*
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* Unordered memory load.
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*/
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static __inline uint8_t
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ia64_ld1(uint8_t *p)
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{
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uint8_t v;
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__asm __volatile("ld1 %0=[%1];;" : "=r"(v) : "r"(p));
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return (v);
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}
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static __inline uint16_t
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ia64_ld2(uint16_t *p)
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{
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uint16_t v;
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__asm __volatile("ld2 %0=[%1];;" : "=r"(v) : "r"(p));
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return (v);
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}
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static __inline uint32_t
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ia64_ld4(uint32_t *p)
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{
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uint32_t v;
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__asm __volatile("ld4 %0=[%1];;" : "=r"(v) : "r"(p));
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return (v);
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}
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static __inline uint64_t
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ia64_ld8(uint64_t *p)
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{
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uint64_t v;
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__asm __volatile("ld8 %0=[%1];;" : "=r"(v) : "r"(p));
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return (v);
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}
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/*
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* Unordered memory store.
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*/
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static __inline void
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ia64_st1(uint8_t *p, uint8_t v)
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{
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__asm __volatile("st1 [%0]=%1;;" :: "r"(p), "r"(v));
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}
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static __inline void
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ia64_st2(uint16_t *p, uint16_t v)
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{
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__asm __volatile("st2 [%0]=%1;;" :: "r"(p), "r"(v));
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}
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static __inline void
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ia64_st4(uint32_t *p, uint32_t v)
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{
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__asm __volatile("st4 [%0]=%1;;" :: "r"(p), "r"(v));
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}
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static __inline void
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ia64_st8(uint64_t *p, uint64_t v)
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{
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__asm __volatile("st8 [%0]=%1;;" :: "r"(p), "r"(v));
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}
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/*
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* Read the value of psr.
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*/
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static __inline uint64_t
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ia64_get_psr(void)
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{
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uint64_t result;
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__asm __volatile("mov %0=psr;;" : "=r" (result));
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return result;
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}
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/*
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* Define accessors for application registers.
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*/
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#define IA64_AR(name) \
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\
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static __inline uint64_t \
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ia64_get_##name(void) \
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{ \
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uint64_t result; \
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__asm __volatile("mov %0=ar." #name : "=r" (result)); \
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return result; \
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} \
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\
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static __inline void \
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ia64_set_##name(uint64_t v) \
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{ \
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__asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \
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}
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IA64_AR(k0)
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IA64_AR(k1)
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IA64_AR(k2)
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IA64_AR(k3)
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IA64_AR(k4)
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IA64_AR(k5)
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IA64_AR(k6)
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IA64_AR(k7)
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IA64_AR(rsc)
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IA64_AR(bsp)
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IA64_AR(bspstore)
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IA64_AR(rnat)
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IA64_AR(fcr)
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IA64_AR(eflag)
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IA64_AR(csd)
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IA64_AR(ssd)
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IA64_AR(cflg)
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IA64_AR(fsr)
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IA64_AR(fir)
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IA64_AR(fdr)
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IA64_AR(ccv)
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IA64_AR(unat)
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IA64_AR(fpsr)
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IA64_AR(itc)
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IA64_AR(pfs)
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IA64_AR(lc)
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IA64_AR(ec)
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/*
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* Define accessors for control registers.
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*/
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#define IA64_CR(name) \
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\
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static __inline uint64_t \
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ia64_get_##name(void) \
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{ \
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uint64_t result; \
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__asm __volatile("mov %0=cr." #name : "=r" (result)); \
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return result; \
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} \
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\
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static __inline void \
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ia64_set_##name(uint64_t v) \
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{ \
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__asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \
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}
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IA64_CR(dcr)
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IA64_CR(itm)
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IA64_CR(iva)
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IA64_CR(pta)
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IA64_CR(ipsr)
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IA64_CR(isr)
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IA64_CR(iip)
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IA64_CR(ifa)
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IA64_CR(itir)
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IA64_CR(iipa)
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IA64_CR(ifs)
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IA64_CR(iim)
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IA64_CR(iha)
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IA64_CR(lid)
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IA64_CR(ivr)
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IA64_CR(tpr)
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IA64_CR(eoi)
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IA64_CR(irr0)
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IA64_CR(irr1)
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IA64_CR(irr2)
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IA64_CR(irr3)
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IA64_CR(itv)
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IA64_CR(pmv)
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IA64_CR(cmcv)
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IA64_CR(lrr0)
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IA64_CR(lrr1)
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/*
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* Write a region register.
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*/
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static __inline void
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ia64_set_rr(uint64_t rrbase, uint64_t v)
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{
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__asm __volatile("mov rr[%0]=%1"
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:: "r"(rrbase), "r"(v) : "memory");
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}
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/*
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* Read a CPUID register.
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*/
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static __inline uint64_t
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ia64_get_cpuid(int i)
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{
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uint64_t result;
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__asm __volatile("mov %0=cpuid[%1]"
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: "=r" (result) : "r"(i));
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return result;
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}
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static __inline void
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ia64_disable_highfp(void)
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{
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__asm __volatile("ssm psr.dfh;; srlz.d");
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}
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static __inline void
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ia64_enable_highfp(void)
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{
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__asm __volatile("rsm psr.dfh;; srlz.d");
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}
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/*
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* Avoid inline functions for the following so that they still work
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* correctly when inlining is not enabled (e.g. -O0). Function calls
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* need data serialization after setting psr, which results in a
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* hazard.
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*/
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#define ia64_srlz_d() __asm __volatile("srlz.d")
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#define ia64_srlz_i() __asm __volatile("srlz.i;;")
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#endif /* !LOCORE */
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#endif /* _MACHINE_IA64_CPU_H_ */
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