438 lines
16 KiB
C
438 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __SDHCI_H__
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#define __SDHCI_H__
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#include "opt_mmccam.h"
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#define DMA_BLOCK_SIZE 4096
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#define DMA_BOUNDARY 0 /* DMA reload every 4K */
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/* Controller doesn't honor resets unless we touch the clock register */
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#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
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/* Controller really supports DMA */
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#define SDHCI_QUIRK_FORCE_DMA (1 << 1)
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/* Controller has unusable DMA engine */
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#define SDHCI_QUIRK_BROKEN_DMA (1 << 2)
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/* Controller doesn't like to be reset when there is no card inserted. */
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#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3)
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/* Controller has flaky internal state so reset it on each ios change */
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#define SDHCI_QUIRK_RESET_ON_IOS (1 << 4)
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/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5)
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/* Controller needs to be reset after each request to stay stable */
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#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6)
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/* Controller has an off-by-one issue with timeout value */
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#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7)
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/* Controller has broken read timings */
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#define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8)
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/* Controller needs lowered frequency */
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#define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9)
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/* Data timeout is invalid, should use SD clock */
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#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10)
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/* Timeout value is invalid, should be overriden */
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#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11)
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/* SDHCI_CAPABILITIES is invalid */
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#define SDHCI_QUIRK_MISSING_CAPS (1 << 12)
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/* Hardware shifts the 136-bit response, don't do it in software. */
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#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13)
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/* Wait to see reset bit asserted before waiting for de-asserted */
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#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14)
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/* Leave controller in standard mode when putting card in HS mode. */
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#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15)
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/* Alternate clock source is required when supplying a 400 KHz clock. */
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#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16)
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/* Card insert/remove interrupts don't work, polling required. */
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#define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17)
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/* All controller slots are non-removable. */
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#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18)
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/* Issue custom Intel controller reset sequence after power-up. */
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#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19)
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/* Data timeout is invalid, use 1 MHz clock instead. */
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#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20)
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/* Controller doesn't allow access boot partitions. */
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#define SDHCI_QUIRK_BOOT_NOACC (1 << 21)
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/* Controller waits for busy responses. */
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#define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22)
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/* Controller supports eMMC DDR52 mode. */
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#define SDHCI_QUIRK_MMC_DDR52 (1 << 23)
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/* Controller support for UHS DDR50 mode is broken. */
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#define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24)
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/* Controller support for eMMC HS200 mode is broken. */
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#define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25)
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/* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */
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#define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26)
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/* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */
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#define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27)
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/* Controller does not support or the support for ACMD12 is broken. */
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#define SDHCI_QUIRK_BROKEN_AUTO_STOP (1 << 28)
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/* Controller supports eMMC HS400 mode if SDHCI_CAN_SDR104 is set. */
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#define SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 (1 << 29)
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_ACMD12 0x04
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_COMMAND_FLAGS 0x0E
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_TYPE_NORMAL 0x00
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#define SDHCI_CMD_TYPE_SUSPEND 0x40
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#define SDHCI_CMD_TYPE_RESUME 0x80
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#define SDHCI_CMD_TYPE_ABORT 0xc0
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#define SDHCI_CMD_TYPE_MASK 0xc0
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#define SDHCI_COMMAND 0x0F
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DAT_INHIBIT 0x00000002
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#define SDHCI_DAT_ACTIVE 0x00000004
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#define SDHCI_RETUNE_REQUEST 0x00000008
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_CARD_STABLE 0x00020000
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#define SDHCI_CARD_PIN 0x00040000
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_STATE_DAT_MASK 0x00f00000
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#define SDHCI_STATE_CMD 0x01000000
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_CTRL_SDMA 0x08
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#define SDHCI_CTRL_ADMA2 0x10
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#define SDHCI_CTRL_ADMA264 0x18
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_CTRL_CARD_DET 0x40
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#define SDHCI_CTRL_FORCE_CARD 0x80
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_MASK 0xff
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#define SDHCI_DIVIDER_MASK_LEN 8
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_MASK 3
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_DIVIDERS_MASK \
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((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \
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(SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT))
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE 0x00000001
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#define SDHCI_INT_DATA_END 0x00000002
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#define SDHCI_INT_BLOCK_GAP 0x00000004
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#define SDHCI_INT_DMA_END 0x00000008
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#define SDHCI_INT_SPACE_AVAIL 0x00000010
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#define SDHCI_INT_DATA_AVAIL 0x00000020
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#define SDHCI_INT_CARD_INSERT 0x00000040
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_INT_A 0x00000200
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#define SDHCI_INT_INT_B 0x00000400
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#define SDHCI_INT_INT_C 0x00000800
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#define SDHCI_INT_RETUNE 0x00001000
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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#define SDHCI_INT_END_BIT 0x00040000
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#define SDHCI_INT_INDEX 0x00080000
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#define SDHCI_INT_DATA_TIMEOUT 0x00100000
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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#define SDHCI_INT_ACMD12ERR 0x01000000
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#define SDHCI_INT_ADMAERR 0x02000000
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#define SDHCI_INT_TUNEERR 0x04000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT)
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#define SDHCI_ACMD12_ERR 0x3C
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_CTRL2_PRESET_VALUE 0x8000
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#define SDHCI_CTRL2_ASYNC_INTR 0x4000
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#define SDHCI_CTRL2_64BIT_ENABLE 0x2000
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#define SDHCI_CTRL2_HOST_V4_ENABLE 0x1000
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#define SDHCI_CTRL2_CMD23_ENABLE 0x0800
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#define SDHCI_CTRL2_ADMA2_LENGTH_MODE 0x0400
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#define SDHCI_CTRL2_UHS2_IFACE_ENABLE 0x0100
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#define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080
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#define SDHCI_CTRL2_EXEC_TUNING 0x0040
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#define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030
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#define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000
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#define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010
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#define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020
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#define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030
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#define SDHCI_CTRL2_S18_ENABLE 0x0008
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#define SDHCI_CTRL2_UHS_MASK 0x0007
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#define SDHCI_CTRL2_UHS_SDR12 0x0000
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#define SDHCI_CTRL2_UHS_SDR25 0x0001
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#define SDHCI_CTRL2_UHS_SDR50 0x0002
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#define SDHCI_CTRL2_UHS_SDR104 0x0003
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#define SDHCI_CTRL2_UHS_DDR50 0x0004
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#define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_8BITBUS 0x00040000
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#define SDHCI_CAN_DO_ADMA2 0x00080000
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_DMA 0x00400000
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#define SDHCI_CAN_DO_SUSPEND 0x00800000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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#define SDHCI_CAN_DO_64BIT 0x10000000
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#define SDHCI_CAN_ASYNC_INTR 0x20000000
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#define SDHCI_SLOTTYPE_MASK 0xC0000000
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#define SDHCI_SLOTTYPE_REMOVABLE 0x00000000
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#define SDHCI_SLOTTYPE_EMBEDDED 0x40000000
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#define SDHCI_SLOTTYPE_SHARED 0x80000000
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#define SDHCI_CAPABILITIES2 0x44
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#define SDHCI_CAN_SDR50 0x00000001
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#define SDHCI_CAN_SDR104 0x00000002
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#define SDHCI_CAN_DDR50 0x00000004
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#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010
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#define SDHCI_CAN_DRIVE_TYPE_C 0x00000020
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#define SDHCI_CAN_DRIVE_TYPE_D 0x00000040
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#define SDHCI_RETUNE_CNT_MASK 0x00000F00
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#define SDHCI_RETUNE_CNT_SHIFT 8
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#define SDHCI_TUNE_SDR50 0x00002000
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#define SDHCI_RETUNE_MODES_MASK 0x0000C000
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#define SDHCI_RETUNE_MODES_SHIFT 14
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#define SDHCI_CLOCK_MULT_MASK 0x00FF0000
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#define SDHCI_CLOCK_MULT_SHIFT 16
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#define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */
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#define SDHCI_MAX_CURRENT 0x48
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#define SDHCI_FORCE_AUTO_EVENT 0x50
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#define SDHCI_FORCE_INTR_EVENT 0x52
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#define SDHCI_ADMA_ERR 0x54
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#define SDHCI_ADMA_ERR_LENGTH 0x04
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#define SDHCI_ADMA_ERR_STATE_MASK 0x03
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#define SDHCI_ADMA_ERR_STATE_STOP 0x00
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#define SDHCI_ADMA_ERR_STATE_FDS 0x01
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#define SDHCI_ADMA_ERR_STATE_TFR 0x03
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#define SDHCI_ADMA_ADDRESS_LO 0x58
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#define SDHCI_ADMA_ADDRESS_HI 0x5C
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#define SDHCI_PRESET_VALUE 0x60
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#define SDHCI_SHARED_BUS_CTRL 0xE0
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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#define SDHCI_SPEC_400 3
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#define SDHCI_SPEC_410 4
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#define SDHCI_SPEC_420 5
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SYSCTL_DECL(_hw_sdhci);
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extern u_int sdhci_quirk_clear;
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extern u_int sdhci_quirk_set;
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struct sdhci_slot {
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struct mtx mtx; /* Slot mutex */
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u_int quirks; /* Chip specific quirks */
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u_int caps; /* Override SDHCI_CAPABILITIES */
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u_int caps2; /* Override SDHCI_CAPABILITIES2 */
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device_t bus; /* Bus device */
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device_t dev; /* Slot device */
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u_char num; /* Slot number */
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u_char opt; /* Slot options */
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#define SDHCI_HAVE_DMA 0x01
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#define SDHCI_PLATFORM_TRANSFER 0x02
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#define SDHCI_NON_REMOVABLE 0x04
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#define SDHCI_TUNING_SUPPORTED 0x08
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#define SDHCI_TUNING_ENABLED 0x10
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#define SDHCI_SDR50_NEEDS_TUNING 0x20
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#define SDHCI_SLOT_EMBEDDED 0x40
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u_char version;
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int timeout; /* Transfer timeout */
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uint32_t max_clk; /* Max possible freq */
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uint32_t timeout_clk; /* Timeout freq */
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bus_dma_tag_t dmatag;
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bus_dmamap_t dmamap;
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u_char *dmamem;
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bus_addr_t paddr; /* DMA buffer address */
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struct task card_task; /* Card presence check task */
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struct timeout_task
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card_delayed_task;/* Card insert delayed task */
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struct callout card_poll_callout;/* Card present polling callout */
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struct callout timeout_callout;/* Card command/data response timeout */
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struct callout retune_callout; /* Re-tuning mode 1 callout */
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struct mmc_host host; /* Host parameters */
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struct mmc_request *req; /* Current request */
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struct mmc_command *curcmd; /* Current command of current request */
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struct mmc_request *tune_req; /* Tuning request */
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struct mmc_command *tune_cmd; /* Tuning command of tuning request */
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struct mmc_data *tune_data; /* Tuning data of tuning command */
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uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */
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uint32_t intmask; /* Current interrupt mask */
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uint32_t clock; /* Current clock freq. */
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size_t offset; /* Data buffer offset */
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uint8_t hostctrl; /* Current host control register */
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uint8_t retune_count; /* Controller re-tuning count [s] */
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uint8_t retune_mode; /* Controller re-tuning mode */
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#define SDHCI_RETUNE_MODE_1 0x00
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#define SDHCI_RETUNE_MODE_2 0x01
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#define SDHCI_RETUNE_MODE_3 0x02
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uint8_t retune_req; /* Re-tuning request status */
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#define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */
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#define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */
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u_char power; /* Current power */
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u_char bus_busy; /* Bus busy status */
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u_char cmd_done; /* CMD command part done flag */
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u_char data_done; /* DAT command part done flag */
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u_char flags; /* Request execution flags */
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#define CMD_STARTED 1
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#define STOP_STARTED 2
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#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
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#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */
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#ifdef MMCCAM
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/* CAM stuff */
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union ccb *ccb;
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struct cam_devq *devq;
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struct cam_sim *sim;
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struct mtx sim_mtx;
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u_char card_present; /* XXX Maybe derive this from elsewhere? */
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#endif
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};
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int sdhci_generic_read_ivar(device_t bus, device_t child, int which,
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uintptr_t *result);
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int sdhci_generic_write_ivar(device_t bus, device_t child, int which,
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uintptr_t value);
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int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num);
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void sdhci_start_slot(struct sdhci_slot *slot);
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/* performs generic clean-up for platform transfers */
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void sdhci_finish_data(struct sdhci_slot *slot);
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int sdhci_cleanup_slot(struct sdhci_slot *slot);
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int sdhci_generic_suspend(struct sdhci_slot *slot);
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int sdhci_generic_resume(struct sdhci_slot *slot);
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int sdhci_generic_update_ios(device_t brdev, device_t reqdev);
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int sdhci_generic_tune(device_t brdev, device_t reqdev, bool hs400);
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int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev);
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int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset);
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int sdhci_generic_request(device_t brdev, device_t reqdev,
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struct mmc_request *req);
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int sdhci_generic_get_ro(device_t brdev, device_t reqdev);
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int sdhci_generic_acquire_host(device_t brdev, device_t reqdev);
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int sdhci_generic_release_host(device_t brdev, device_t reqdev);
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void sdhci_generic_intr(struct sdhci_slot *slot);
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uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot);
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bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot);
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void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot);
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void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present);
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#endif /* __SDHCI_H__ */
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