4edef187b8
I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
385 lines
10 KiB
C
385 lines
10 KiB
C
/*-
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* Copyright (c) 2011 Advanced Computing Technologies LLC
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* Written by: John H. Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Support APIs for Host to PCI bridge drivers and drivers that
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* provide PCI domains.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/systm.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcib_private.h>
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/*
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* Try to read the bus number of a host-PCI bridge using appropriate config
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* registers.
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*/
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int
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host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
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uint8_t *busnum)
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{
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uint32_t id;
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id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
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if (id == 0xffffffff)
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return (0);
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switch (id) {
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case 0x12258086:
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/* Intel 824?? */
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/* XXX This is a guess */
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/* *busnum = read_config(bus, slot, func, 0x41, 1); */
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*busnum = bus;
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break;
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case 0x84c48086:
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/* Intel 82454KX/GX (Orion) */
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*busnum = read_config(bus, slot, func, 0x4a, 1);
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break;
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case 0x84ca8086:
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/*
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* For the 450nx chipset, there is a whole bundle of
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* things pretending to be host bridges. The MIOC will
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* be seen first and isn't really a pci bridge (the
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* actual busses are attached to the PXB's). We need to
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* read the registers of the MIOC to figure out the
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* bus numbers for the PXB channels.
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*
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* Since the MIOC doesn't have a pci bus attached, we
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* pretend it wasn't there.
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*/
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return (0);
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case 0x84cb8086:
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switch (slot) {
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case 0x12:
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/* Intel 82454NX PXB#0, Bus#A */
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*busnum = read_config(bus, 0x10, func, 0xd0, 1);
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break;
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case 0x13:
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/* Intel 82454NX PXB#0, Bus#B */
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*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
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break;
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case 0x14:
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/* Intel 82454NX PXB#1, Bus#A */
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*busnum = read_config(bus, 0x10, func, 0xd3, 1);
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break;
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case 0x15:
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/* Intel 82454NX PXB#1, Bus#B */
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*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
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break;
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}
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break;
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/* ServerWorks -- vendor 0x1166 */
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case 0x00051166:
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case 0x00061166:
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case 0x00081166:
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case 0x00091166:
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case 0x00101166:
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case 0x00111166:
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case 0x00171166:
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case 0x01011166:
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case 0x010f1014:
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case 0x01101166:
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case 0x02011166:
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case 0x02251166:
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case 0x03021014:
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*busnum = read_config(bus, slot, func, 0x44, 1);
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break;
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/* Compaq/HP -- vendor 0x0e11 */
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case 0x60100e11:
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*busnum = read_config(bus, slot, func, 0xc8, 1);
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break;
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default:
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/* Don't know how to read bus number. */
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return 0;
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}
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return 1;
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}
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#ifdef NEW_PCIB
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/*
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* Return a pointer to a pretty name for a PCI device. If the device
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* has a driver attached, the device's name is used, otherwise a name
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* is generated from the device's PCI address.
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*/
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const char *
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pcib_child_name(device_t child)
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{
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static char buf[64];
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if (device_get_nameunit(child) != NULL)
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return (device_get_nameunit(child));
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snprintf(buf, sizeof(buf), "pci%d:%d:%d:%d", pci_get_domain(child),
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pci_get_bus(child), pci_get_slot(child), pci_get_function(child));
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return (buf);
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}
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/*
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* Some Host-PCI bridge drivers know which resource ranges they can
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* decode and should only allocate subranges to child PCI devices.
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* This API provides a way to manage this. The bridge driver should
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* initialize this structure during attach and call
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* pcib_host_res_decodes() on each resource range it decodes. It can
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* then use pcib_host_res_alloc() and pcib_host_res_adjust() as helper
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* routines for BUS_ALLOC_RESOURCE() and BUS_ADJUST_RESOURCE(). This
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* API assumes that resources for any decoded ranges can be safely
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* allocated from the parent via bus_generic_alloc_resource().
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*/
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int
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pcib_host_res_init(device_t pcib, struct pcib_host_resources *hr)
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{
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hr->hr_pcib = pcib;
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resource_list_init(&hr->hr_rl);
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return (0);
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}
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int
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pcib_host_res_free(device_t pcib, struct pcib_host_resources *hr)
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{
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resource_list_free(&hr->hr_rl);
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return (0);
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}
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int
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pcib_host_res_decodes(struct pcib_host_resources *hr, int type, u_long start,
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u_long end, u_int flags)
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{
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struct resource_list_entry *rle;
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int rid;
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if (bootverbose)
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device_printf(hr->hr_pcib, "decoding %d %srange %#lx-%#lx\n",
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type, flags & RF_PREFETCHABLE ? "prefetchable ": "", start,
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end);
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rid = resource_list_add_next(&hr->hr_rl, type, start, end,
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end - start + 1);
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if (flags & RF_PREFETCHABLE) {
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KASSERT(type == SYS_RES_MEMORY,
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("only memory is prefetchable"));
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rle = resource_list_find(&hr->hr_rl, type, rid);
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rle->flags = RLE_PREFETCH;
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}
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return (0);
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}
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struct resource *
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pcib_host_res_alloc(struct pcib_host_resources *hr, device_t dev, int type,
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int *rid, u_long start, u_long end, u_long count, u_int flags)
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{
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struct resource_list_entry *rle;
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struct resource *r;
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u_long new_start, new_end;
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if (flags & RF_PREFETCHABLE)
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KASSERT(type == SYS_RES_MEMORY,
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("only memory is prefetchable"));
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rle = resource_list_find(&hr->hr_rl, type, 0);
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if (rle == NULL) {
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/*
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* No decoding ranges for this resource type, just pass
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* the request up to the parent.
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*/
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return (bus_generic_alloc_resource(hr->hr_pcib, dev, type, rid,
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start, end, count, flags));
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}
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restart:
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/* Try to allocate from each decoded range. */
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for (; rle != NULL; rle = STAILQ_NEXT(rle, link)) {
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if (rle->type != type)
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continue;
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if (((flags & RF_PREFETCHABLE) != 0) !=
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((rle->flags & RLE_PREFETCH) != 0))
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continue;
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new_start = ulmax(start, rle->start);
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new_end = ulmin(end, rle->end);
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if (new_start > new_end ||
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new_start + count - 1 > new_end ||
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new_start + count < new_start)
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continue;
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r = bus_generic_alloc_resource(hr->hr_pcib, dev, type, rid,
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new_start, new_end, count, flags);
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if (r != NULL) {
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if (bootverbose)
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device_printf(hr->hr_pcib,
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"allocated type %d (%#lx-%#lx) for rid %x of %s\n",
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type, rman_get_start(r), rman_get_end(r),
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*rid, pcib_child_name(dev));
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return (r);
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}
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}
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/*
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* If we failed to find a prefetch range for a memory
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* resource, try again without prefetch.
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*/
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if (flags & RF_PREFETCHABLE) {
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flags &= ~RF_PREFETCHABLE;
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rle = resource_list_find(&hr->hr_rl, type, 0);
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goto restart;
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}
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return (NULL);
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}
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int
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pcib_host_res_adjust(struct pcib_host_resources *hr, device_t dev, int type,
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struct resource *r, u_long start, u_long end)
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{
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struct resource_list_entry *rle;
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rle = resource_list_find(&hr->hr_rl, type, 0);
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if (rle == NULL) {
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/*
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* No decoding ranges for this resource type, just pass
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* the request up to the parent.
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*/
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return (bus_generic_adjust_resource(hr->hr_pcib, dev, type, r,
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start, end));
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}
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/* Only allow adjustments that stay within a decoded range. */
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for (; rle != NULL; rle = STAILQ_NEXT(rle, link)) {
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if (rle->start <= start && rle->end >= end)
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return (bus_generic_adjust_resource(hr->hr_pcib, dev,
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type, r, start, end));
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}
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return (ERANGE);
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}
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#ifdef PCI_RES_BUS
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struct pci_domain {
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int pd_domain;
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struct rman pd_bus_rman;
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TAILQ_ENTRY(pci_domain) pd_link;
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};
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static TAILQ_HEAD(, pci_domain) domains = TAILQ_HEAD_INITIALIZER(domains);
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/*
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* Each PCI domain maintains its own resource manager for PCI bus
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* numbers in that domain. Domain objects are created on first use.
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* Host to PCI bridge drivers and PCI-PCI bridge drivers should
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* allocate their bus ranges from their domain.
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*/
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static struct pci_domain *
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pci_find_domain(int domain)
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{
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struct pci_domain *d;
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char buf[64];
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int error;
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TAILQ_FOREACH(d, &domains, pd_link) {
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if (d->pd_domain == domain)
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return (d);
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}
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snprintf(buf, sizeof(buf), "PCI domain %d bus numbers", domain);
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d = malloc(sizeof(*d) + strlen(buf) + 1, M_DEVBUF, M_WAITOK | M_ZERO);
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d->pd_domain = domain;
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d->pd_bus_rman.rm_start = 0;
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d->pd_bus_rman.rm_end = PCI_BUSMAX;
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d->pd_bus_rman.rm_type = RMAN_ARRAY;
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strcpy((char *)(d + 1), buf);
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d->pd_bus_rman.rm_descr = (char *)(d + 1);
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error = rman_init(&d->pd_bus_rman);
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if (error == 0)
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error = rman_manage_region(&d->pd_bus_rman, 0, PCI_BUSMAX);
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if (error)
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panic("Failed to initialize PCI domain %d rman", domain);
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TAILQ_INSERT_TAIL(&domains, d, pd_link);
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return (d);
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}
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struct resource *
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pci_domain_alloc_bus(int domain, device_t dev, int *rid, u_long start,
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u_long end, u_long count, u_int flags)
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{
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struct pci_domain *d;
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struct resource *res;
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if (domain < 0 || domain > PCI_DOMAINMAX)
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return (NULL);
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d = pci_find_domain(domain);
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res = rman_reserve_resource(&d->pd_bus_rman, start, end, count, flags,
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dev);
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if (res == NULL)
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return (NULL);
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rman_set_rid(res, *rid);
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return (res);
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}
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int
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pci_domain_adjust_bus(int domain, device_t dev, struct resource *r,
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u_long start, u_long end)
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{
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#ifdef INVARIANTS
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struct pci_domain *d;
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#endif
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if (domain < 0 || domain > PCI_DOMAINMAX)
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return (EINVAL);
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#ifdef INVARIANTS
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d = pci_find_domain(domain);
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KASSERT(rman_is_region_manager(r, &d->pd_bus_rman), ("bad resource"));
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#endif
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return (rman_adjust_resource(r, start, end));
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}
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int
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pci_domain_release_bus(int domain, device_t dev, int rid, struct resource *r)
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{
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#ifdef INVARIANTS
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struct pci_domain *d;
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#endif
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if (domain < 0 || domain > PCI_DOMAINMAX)
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return (EINVAL);
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#ifdef INVARIANTS
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d = pci_find_domain(domain);
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KASSERT(rman_is_region_manager(r, &d->pd_bus_rman), ("bad resource"));
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#endif
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return (rman_release_resource(r));
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}
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#endif /* PCI_RES_BUS */
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#endif /* NEW_PCIB */
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