229 lines
8.1 KiB
C
229 lines
8.1 KiB
C
/*
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* Copyright (c) 2000, 2001 Richard Hodges and Matriplex, inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Matriplex, inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*
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* This driver is derived from the Nicstar driver by Mark Tinguely, and
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* some of the original driver still exists here. Those portions are...
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* Copyright (c) 1996, 1997, 1998, 1999 Mark Tinguely
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* All rights reserved.
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*
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******************************************************************************
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*
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* This driver supports the Fore LE155, LE25, and IDT 77211 cards.
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*
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* ATM CBR connections are supported, and bandwidth is allocated in
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* slots of 64k each. Three VBR queues handle traffic for VBR and
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* UBR. Two UBR queues prioritize UBR traffic. ILMI and signalling
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* get the higher priority queue, as well as UBR traffic that specifies
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* a peak cell rate. All other UBR traffic goes into the lower queue.
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*
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******************************************************************************
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*
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* $FreeBSD$
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*/
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/*******************************************************************************
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*
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* New data types
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*/
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typedef struct {
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struct mbuf *mget; /* head of mbuf queue, pull mbufs from here */
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struct mbuf **mput; /* tail (ptr to m_nextpkt) put mbufs here */
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u_long scd; /* segmentation channel descriptor address */
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u_long *scq_base; /* segmentation channel queue base address */
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u_long *scq_next; /* next address */
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u_long *scq_last; /* last address written */
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int scq_len; /* size of SCQ buffer (64 or 512) */
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int scq_cur; /* current number entries in SCQ buffer */
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int rate; /* cells per second allocated to this queue */
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int vbr_m; /* VBR m/n = max duty cycle for queue */
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int vbr_n; /* 1 <= m <= 7 and 1 <= n <= 127 */
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} TX_QUEUE;
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/* To avoid expensive SRAM reads, scq_cur tracks the number of SCQ entries
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* in use. Only idt_transmit_top may increase this, and only idt_intr_tsq
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* may decrease it.
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*/
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/* mbuf chains on the queue use the fields:
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* m_next is the usual pointer to next mbuf
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* m_nextpkt is the next packet on the queue
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* m_pkthdr.rcvif is a pointer to the connection
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* m_pkthdr.header is a pointer to the TX queue
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*/
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typedef struct {
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struct vccb *vccinf;
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char status; /* zero if closed */
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char vpi;
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u_short vci;
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TX_QUEUE *queue; /* transmit queue for this connection */
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struct mbuf *recv; /* current receive mbuf, or NULL */
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int rlen; /* current receive length */
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int maxpdu; /* largest PDU we will ever see */
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int traf_pcr; /* peak cell rate */
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int traf_scr; /* sustained cell rate */
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u_char aal; /* AAL for this connection */
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u_char class; /* T_ATM_CBR, T_ATM_VBR, or T_ATM_UBR */
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u_char flg_mpeg2ts:1; /* send data as 2 TS == 8 AAL5 cells */
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u_char flg_clp:1; /* CLP flag for outbound cells */
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} CONNECTION;
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#define MAX_CONNECTION 4096 /* max number of connections */
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#define GET_RDTSC(var) {__asm__ volatile("rdtsc":"=A"(var)); }
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/*******************************************************************************
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*
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* Device softc structure
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*/
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struct idt_softc {
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/* HARP data */
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/* XXX: must be first member of struct. */
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Cmn_unit iu_cmn; /* Common unit stuff */
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#if 0
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struct arpcom idt_ac; /* ifnet for device */
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#endif
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/* Device data */
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device_t dev;
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int debug;
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struct resource * mem;
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int mem_rid;
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int mem_type;
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bus_space_tag_t bustag;
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bus_space_handle_t bushandle;
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struct resource * irq;
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int irq_rid;
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void * irq_ih;
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struct callout_handle ch;
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struct mtx mtx;
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vm_offset_t virt_baseaddr; /* nicstar register virtual address */
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vm_offset_t cmd_reg; /* command register offset 0x14 */
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vm_offset_t stat_reg; /* status register offset 0x60 */
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vm_offset_t fixbuf; /* buffer that holds TSQ, RSQ, variable SCQ */
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u_long timer_wrap; /* keep track of wrapped timers */
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u_long rsqh; /* Recieve Status Queue, reg is write-only */
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CONNECTION *connection; /* connection table */
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int conn_maxvpi; /* number of VPI values */
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int conn_maxvci; /* number of VCI values */
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int cellrate_rmax; /* max RX cells per second */
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int cellrate_tmax; /* max TX cells per second */
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int cellrate_rcur; /* current committed RX cellrate */
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int cellrate_tcur; /* current committed TX cellrate */
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int txslots_max; /* number of CBR TX slots for interface */
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int txslots_cur; /* current CBR TX slots in use */
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TX_QUEUE cbr_txqb[IDT_MAX_CBRQUEUE];
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TX_QUEUE *cbr_slot[IDT_MAX_CBRSLOTS];
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TX_QUEUE *cbr_free[IDT_MAX_CBRQUEUE];
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TX_QUEUE queue_vbr;
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TX_QUEUE queue_abr;
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TX_QUEUE queue_ubr;
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vm_offset_t cbr_base; /* base of memory for CBR TX queues */
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int cbr_size; /* size of memory for CBR TX queues */
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int cbr_freect;
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u_long raw_headp; /* head of raw cell queue, physical */
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struct mbuf *raw_headm; /* head of raw cell queue, virtual */
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u_long *tsq_base; /* virtual TSQ base address */
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u_long *tsq_head; /* virtual TSQ head pointer */
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int tsq_size; /* number of TSQ entries (1024) */
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volatile u_long *reg_cfg;
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volatile u_long *reg_cmd;
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volatile u_long *reg_data;
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volatile u_long *reg_tsqh;
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volatile u_long *reg_gp;
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volatile u_long *reg_stat;
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struct mbuf **mcheck;
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int sram; /* amount of SRAM */
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int pci_rev; /* hardware revision ID */
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char *hardware; /* hardware description string */
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u_char flg_le25:1; /* flag indicates LE25 instead of LE155 */
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u_char flg_igcrc:1; /* ignore receive CRC errors */
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};
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typedef struct idt_softc nicstar_reg_t;
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typedef struct idt_softc IDT;
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#define iu_pif iu_cmn.cu_pif
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#define stats_ipdus iu_pif.pif_ipdus
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#define stats_opdus iu_pif.pif_opdus
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#define stats_ibytes iu_pif.pif_ibytes
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#define stats_obytes iu_pif.pif_obytes
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#define stats_ierrors iu_pif.pif_ierrors
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#define stats_oerrors iu_pif.pif_oerrors
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#define stats_cmderrors iu_pif.pif_cmderrors
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/*
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* Device VCC Entry
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*
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* Contains the common and IDT-specific information for each VCC
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* which is opened through a IDT device.
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*/
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struct nidt_vcc {
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struct cmn_vcc iv_cmn; /* Common VCC stuff */
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};
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typedef struct nidt_vcc Idt_vcc;
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extern int idt_sysctl_logvcs;
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extern int idt_sysctl_vbriscbr;
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void nicstar_intr(void *);
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void phys_init(nicstar_reg_t * const);
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void nicstar_init(nicstar_reg_t * const);
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int idt_harp_init(nicstar_reg_t * const);
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void idt_device_stop(IDT *);
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void idt_release_mem(IDT *);
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CONNECTION *idt_connect_find(IDT *, int, int);
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caddr_t idt_mbuf_base(struct mbuf *);
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int idt_slots_cbr(IDT *, int);
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int idt_connect_opencls(IDT *, CONNECTION *, int);
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int idt_connect_txopen(IDT *, CONNECTION *);
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int idt_connect_txclose(IDT *, CONNECTION *);
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int nicstar_eeprom_rd(nicstar_reg_t * const, u_long);
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void idt_receive(IDT *, struct mbuf *, int, int);
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void idt_transmit(IDT *, struct mbuf *, int, int, int);
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