354 lines
11 KiB
C
354 lines
11 KiB
C
/* $OpenBSD: if_txvar.h,v 1.7 1999/11/17 05:21:19 jason Exp $ */
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 1997 Semen Ustimenko
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Configuration
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*/
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/*#define EPIC_DEBUG 1*/
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/*#define EPIC_USEIOSPACE 1*/
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#define EARLY_RX 1
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#ifndef ETHER_MAX_LEN
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#define ETHER_MAX_LEN 1518
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#endif
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#ifndef ETHER_MIN_LEN
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#define ETHER_MIN_LEN 64
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#endif
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#ifndef ETHER_CRC_LEN
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#define ETHER_CRC_LEN 4
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#endif
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#define TX_RING_SIZE 16 /* Leave this a power of 2 */
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#define RX_RING_SIZE 16 /* And this too, to do not */
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/* confuse RX(TX)_RING_MASK */
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#define TX_RING_MASK (TX_RING_SIZE - 1)
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#define RX_RING_MASK (RX_RING_SIZE - 1)
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#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
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/* PCI aux configuration registers */
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#if defined(__FreeBSD__)
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#define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */
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#define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */
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#else /* __OpenBSD__ */
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#define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */
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#define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */
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#endif /* __FreeBSD__ */
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/* PCI identification */
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#define SMC_VENDORID 0x10B8
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#define SMC_DEVICEID_83C170 0x0005
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/* EPIC's registers */
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#define COMMAND 0x0000
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#define INTSTAT 0x0004 /* Interrupt status. See below */
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#define INTMASK 0x0008 /* Interrupt mask. See below */
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#define GENCTL 0x000C
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#define NVCTL 0x0010
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#define EECTL 0x0014 /* EEPROM control **/
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#define TEST1 0x001C /* XXXXX */
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#define CRCCNT 0x0020 /* CRC error counter */
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#define ALICNT 0x0024 /* FrameTooLang error counter */
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#define MPCNT 0x0028 /* MissedFrames error counters */
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#define MIICTL 0x0030
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#define MIIDATA 0x0034
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#define MIICFG 0x0038
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#define IPG 0x003C
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#define LAN0 0x0040 /* MAC address */
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#define LAN1 0x0044 /* MAC address */
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#define LAN2 0x0048 /* MAC address */
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#define ID_CHK 0x004C
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#define MC0 0x0050 /* Multicast filter table */
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#define MC1 0x0054 /* Multicast filter table */
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#define MC2 0x0058 /* Multicast filter table */
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#define MC3 0x005C /* Multicast filter table */
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#define RXCON 0x0060 /* Rx control register */
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#define TXCON 0x0070 /* Tx control register */
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#define TXSTAT 0x0074
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#define PRCDAR 0x0084 /* RxRing bus address */
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#define PRSTAT 0x00A4
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#define PRCPTHR 0x00B0
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#define PTCDAR 0x00C4 /* TxRing bus address */
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#define ETXTHR 0x00DC
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#define COMMAND_STOP_RX 0x01
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#define COMMAND_START_RX 0x02
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#define COMMAND_TXQUEUED 0x04
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#define COMMAND_RXQUEUED 0x08
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#define COMMAND_NEXTFRAME 0x10
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#define COMMAND_STOP_TDMA 0x20
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#define COMMAND_STOP_RDMA 0x40
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#define COMMAND_TXUGO 0x80
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/* Interrupt register bits */
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#define INTSTAT_RCC 0x00000001
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#define INTSTAT_HCC 0x00000002
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#define INTSTAT_RQE 0x00000004
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#define INTSTAT_OVW 0x00000008
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#define INTSTAT_RXE 0x00000010
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#define INTSTAT_TXC 0x00000020
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#define INTSTAT_TCC 0x00000040
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#define INTSTAT_TQE 0x00000080
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#define INTSTAT_TXU 0x00000100
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#define INTSTAT_CNT 0x00000200
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#define INTSTAT_PREI 0x00000400
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#define INTSTAT_RCT 0x00000800
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#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */
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#define INTSTAT_UNUSED1 0x00002000
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#define INTSTAT_UNUSED2 0x00004000
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#define INTSTAT_GP2 0x00008000 /* PHY Event */
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#define INTSTAT_INT_ACTV 0x00010000
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#define INTSTAT_RXIDLE 0x00020000
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#define INTSTAT_TXIDLE 0x00040000
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#define INTSTAT_RCIP 0x00080000
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#define INTSTAT_TCIP 0x00100000
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#define INTSTAT_RBE 0x00200000
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#define INTSTAT_RCTS 0x00400000
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#define INTSTAT_RSV 0x00800000
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#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */
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#define INTSTAT_APE 0x02000000 /* PCI Fatal error */
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#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */
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#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */
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#define GENCTL_SOFT_RESET 0x00000001
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#define GENCTL_ENABLE_INTERRUPT 0x00000002
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#define GENCTL_SOFTWARE_INTERRUPT 0x00000004
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#define GENCTL_POWER_DOWN 0x00000008
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#define GENCTL_ONECOPY 0x00000010
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#define GENCTL_BIG_ENDIAN 0x00000020
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#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040
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#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080
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#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300
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#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200
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#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100
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#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000
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#define GENCTL_MEMORY_READ_LINE 0x00000400
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#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800
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#define GENCTL_SOFTWARE1 0x00001000
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#define GENCTL_SOFTWARE2 0x00002000
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#define GENCTL_RESET_PHY 0x00004000
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#define NVCTL_ENABLE_MEMORY_MAP 0x00000001
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#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002
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#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004
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#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008
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#define NVCTL_GP1 0x00000010
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#define NVCTL_GP2 0x00000020
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#define NVCTL_CARDBUS_MODE 0x00000040
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#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7)
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#define RXCON_SAVE_ERRORED_PACKETS 0x00000001
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#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002
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#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004
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#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008
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#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010
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#define RXCON_PROMISCUOUS_MODE 0x00000020
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#define RXCON_MONITOR_MODE 0x00000040
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#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080
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#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000
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#define RXCON_EXTERNAL_BUFFER_16K 0x00000100
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#define RXCON_EXTERNAL_BUFFER_32K 0x00000200
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#define RXCON_EXTERNAL_BUFFER_128K 0x00000300
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#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001
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#define TXCON_LOOPBACK_DISABLE 0x00000000
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#define TXCON_LOOPBACK_MODE_INT 0x00000002
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#define TXCON_LOOPBACK_MODE_PHY 0x00000004
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#define TXCON_LOOPBACK_MODE 0x00000006
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#define TXCON_FULL_DUPLEX 0x00000006
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#define TXCON_SLOT_TIME 0x00000078
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#define MIICFG_SERIAL_ENABLE 0x00000001
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#define MIICFG_694_ENABLE 0x00000002
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#define MIICFG_694_STATUS 0x00000004
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#define MIICFG_PHY_PRESENT 0x00000008
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#define MIICFG_SMI_ENABLE 0x00000010
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#define TEST1_CLOCK_TEST 0x00000008
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/*
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* Some default values
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*/
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#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE)
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#define TRANSMIT_THRESHOLD 0x300
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#if defined(EARLY_RX)
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#define RXCON_EARLY (RXCON_EARLY_RECEIVE_ENABLE | \
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RXCON_SAVE_ERRORED_PACKETS)
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#else
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#define RXCON_EARLY (0)
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#endif
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#define RXCON_DEFAULT (RXCON_EARLY | \
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RXCON_RECEIVE_MULTICAST_FRAMES | \
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RXCON_RECEIVE_BROADCAST_FRAMES)
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/*
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* Structures definition and Functions prototypes
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*/
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/* EPIC's hardware descriptors, must be aligned on dword in memory */
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/* NB: to make driver happy, this two structures MUST have thier sizes */
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/* be divisor of PAGE_SIZE */
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struct epic_tx_desc {
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volatile u_int16_t status;
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volatile u_int16_t txlength;
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volatile u_int32_t bufaddr;
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volatile u_int16_t buflength;
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volatile u_int16_t control;
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volatile u_int32_t next;
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};
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struct epic_rx_desc {
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volatile u_int16_t status;
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volatile u_int16_t rxlength;
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volatile u_int32_t bufaddr;
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volatile u_int32_t buflength;
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volatile u_int32_t next;
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};
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/* This structure defines EPIC's fragment list, maximum number of frags */
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/* is 63. Let use maximum, becouse size of struct MUST be divisor of */
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/* PAGE_SIZE, and sometimes come mbufs with more then 30 frags */
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#define EPIC_MAX_FRAGS 63
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struct epic_frag_list {
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volatile u_int32_t numfrags;
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struct {
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volatile u_int32_t fragaddr;
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volatile u_int32_t fraglen;
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} frag[EPIC_MAX_FRAGS];
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volatile u_int32_t pad; /* align on 256 bytes */
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};
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/* This is driver's structure to define EPIC descriptors */
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struct epic_rx_buffer {
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struct mbuf * mbuf; /* mbuf receiving packet */
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};
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struct epic_tx_buffer {
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struct mbuf * mbuf; /* mbuf contained packet */
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};
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/*
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* NB: ALIGN OF ABOVE STRUCTURES
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* epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword
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*/
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/* Driver status structure */
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typedef struct {
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struct arpcom arpcom;
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#if defined(__OpenBSD__)
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mii_data_t sc_mii;
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struct device dev;
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#else /* __FreeBSD__ */
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struct resource *res;
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struct resource *irq;
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device_t miibus;
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device_t dev;
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struct callout_handle stat_ch;
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u_int32_t unit;
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#endif
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void *sc_ih;
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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struct epic_rx_buffer rx_buffer[RX_RING_SIZE];
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struct epic_tx_buffer tx_buffer[TX_RING_SIZE];
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/* Each element of array MUST be aligned on dword */
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/* and bounded on PAGE_SIZE */
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struct epic_rx_desc *rx_desc;
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struct epic_tx_desc *tx_desc;
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struct epic_frag_list *tx_flist;
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u_int32_t flags;
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u_int32_t tx_threshold;
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u_int32_t txcon;
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u_int32_t phyid;
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u_int32_t cur_tx;
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u_int32_t cur_rx;
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u_int32_t dirty_tx;
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u_int32_t pending_txs;
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void *pool;
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} epic_softc_t;
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struct epic_type {
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u_int16_t ven_id;
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u_int16_t dev_id;
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char *name;
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};
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#if defined(EPIC_DEBUG)
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#define dprintf(a) printf a
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#else
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#define dprintf(a)
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#endif
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#if defined(__FreeBSD__)
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#define EPIC_FORMAT "tx%d"
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#define EPIC_ARGS(sc) (sc->unit)
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#define EPIC_BPFTAP_ARG(ifp) ifp
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#else /* __OpenBSD__ */
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#define EPIC_FORMAT "%s"
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#define EPIC_ARGS(sc) (sc->sc_dev.dv_xname)
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#define EPIC_BPFTAP_ARG(ifp) (ifp)->if_bpf
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#endif
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#define sc_if arpcom.ac_if
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#define sc_macaddr arpcom.ac_enaddr
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#define CSR_WRITE_4(sc,reg,val) \
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bus_space_write_4( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
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#define CSR_WRITE_2(sc,reg,val) \
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bus_space_write_2( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
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#define CSR_WRITE_1(sc,reg,val) \
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bus_space_write_1( (sc)->sc_st, (sc)->sc_sh, (reg), (val) )
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#define CSR_READ_4(sc,reg) \
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bus_space_read_4( (sc)->sc_st, (sc)->sc_sh, (reg) )
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#define CSR_READ_2(sc,reg) \
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bus_space_read_2( (sc)->sc_st, (sc)->sc_sh, (reg) )
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#define CSR_READ_1(sc,reg) \
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bus_space_read_1( (sc)->sc_st, (sc)->sc_sh, (reg) )
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#define PHY_READ_2(sc,phy,reg) \
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epic_read_phy_reg((sc),(phy),(reg))
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#define PHY_WRITE_2(sc,phy,reg,val) \
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epic_write_phy_reg((sc),(phy),(reg),(val))
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/* Macro to get either mbuf cluster or nothing */
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#define EPIC_MGETCLUSTER(m) \
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{ MGETHDR((m),M_DONTWAIT,MT_DATA); \
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if (m) { \
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MCLGET((m),M_DONTWAIT); \
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if( 0 == ((m)->m_flags & M_EXT) ) { \
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m_freem(m); \
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(m) = NULL; \
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} \
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} \
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}
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