andrew ccf948ce6c Fix the cache type identification ... DIC and IDC are supported when the field bits are set. Sponsored by: Innovate UK		2020-02-26 15:56:07 +00:00
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acpica	Ignore the SMMUv3 and PMCG interrupt controller in the IORT tables	2020-01-31 09:51:38 +00:00
arm64	Fix the cache type identification	2020-02-26 15:56:07 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
cloudabi64	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
conf	Add PCI Express driver for the ARM Neoverse N1 System Development	2020-02-11 15:12:09 +00:00
coresight	Extract eventfilter declarations to sys/_eventfilter.h	2019-05-20 00:38:23 +00:00
include	Generalise the arm64 ASID allocator.	2020-02-26 11:50:24 +00:00
intel	Add support for Intel Stratix 10 platform.	2019-09-13 16:50:57 +00:00
linux	Implement the Linux/arm64 VDSO gettimeofday and clock_gettime	2020-02-08 13:35:56 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (13 of many)	2020-02-24 10:45:22 +00:00