Marius Strobl aafdd1d65a The broken DDR52 support of Intel Bay Trail eMMC controllers rumored ...

in the commit log of r321385 has been confirmed via the public VLI54
erratum. Thus, stop advertising DDR52 for these controllers.
Note that this change should hardly make a difference in practice as
eMMC chips from the same era as these SoCs most likely support HS200
at least, probably even up to HS400ES.

2018-05-14 21:46:06 +00:00

..

fsl_sdhci.c

Don't call sdhci_cleanup_slot() if sdhci_init_slot() never got called.

2018-02-17 23:39:10 +00:00

sdhci_acpi.c

The broken DDR52 support of Intel Bay Trail eMMC controllers rumored

2018-05-14 21:46:06 +00:00

sdhci_fdt_gpio.c

Release all previously allocated resources.

2017-03-08 14:52:03 +00:00

sdhci_fdt_gpio.h

…

sdhci_fdt.c

Fix build when option MMCCAM is defined.

2018-03-08 22:49:36 +00:00

sdhci_if.m

o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to

2017-07-23 16:11:47 +00:00

sdhci_pci.c

The broken DDR52 support of Intel Bay Trail eMMC controllers rumored

2018-05-14 21:46:06 +00:00

sdhci.c

Fix a bug introduced in r327339; at the point in time re-tuning is

2018-01-13 16:21:13 +00:00

sdhci.h

sys/dev: further adoption of SPDX licensing ID tags.

2017-11-27 14:52:40 +00:00