28bd1409da
command register. The lazy BAR allocation code in FreeBSD sometimes disables this bit when it detects a range conflict, and will re-enable it on demand when a driver allocates the BAR. Thus, the bit is no longer a reliable indication of capability, and should not be checked. This results in the elimination of a lot of code from drivers, and also gives the opportunity to simplify a lot of drivers to use a helper API to set the busmaster enable bit. This changes fixes some recent reports of disk controllers and their associated drives/enclosures disappearing during boot. Submitted by: jhb Reviewed by: jfv, marius, achadd, achim MFC after: 1 day
367 lines
9.4 KiB
C
367 lines
9.4 KiB
C
/*-
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* Copyright (c) Comtrol Corporation <support@comtrol.com>
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* All rights reserved.
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*
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* PCI-specific part separated from:
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* sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted prodived that the follwoing conditions
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* are met.
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* 1. Redistributions of source code must retain the above copyright
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* notive, this list of conditions and the following disclainer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials prodided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Comtrol Corporation.
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* 4. The name of Comtrol Corporation may not be used to endorse or
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* promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/fcntl.h>
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#include <sys/malloc.h>
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#include <sys/tty.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#define ROCKET_C
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#include <dev/rp/rpreg.h>
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#include <dev/rp/rpvar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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/* PCI IDs */
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#define RP_VENDOR_ID 0x11FE
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#define RP_DEVICE_ID_32I 0x0001
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#define RP_DEVICE_ID_8I 0x0002
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#define RP_DEVICE_ID_16I 0x0003
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#define RP_DEVICE_ID_4Q 0x0004
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#define RP_DEVICE_ID_8O 0x0005
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#define RP_DEVICE_ID_8J 0x0006
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#define RP_DEVICE_ID_4J 0x0007
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#define RP_DEVICE_ID_6M 0x000C
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#define RP_DEVICE_ID_4M 0x000D
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#define RP_DEVICE_ID_UPCI_32 0x0801
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#define RP_DEVICE_ID_UPCI_16 0x0803
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#define RP_DEVICE_ID_UPCI_8O 0x0805
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/**************************************************************************
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MUDBAC remapped for PCI
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**************************************************************************/
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#define _CFG_INT_PCI 0x40
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#define _PCI_INT_FUNC 0x3A
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#define PCI_STROB 0x2000
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#define INTR_EN_PCI 0x0010
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/***************************************************************************
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Function: sPCIControllerEOI
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Purpose: Strobe the MUDBAC's End Of Interrupt bit.
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Call: sPCIControllerEOI(CtlP)
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CONTROLLER_T *CtlP; Ptr to controller structure
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*/
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#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
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/***************************************************************************
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Function: sPCIGetControllerIntStatus
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Purpose: Get the controller interrupt status
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Call: sPCIGetControllerIntStatus(CtlP)
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CONTROLLER_T *CtlP; Ptr to controller structure
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Return: Byte_t: The controller interrupt status in the lower 4
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bits. Bits 0 through 3 represent AIOP's 0
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through 3 respectively. If a bit is set that
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AIOP is interrupting. Bits 4 through 7 will
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always be cleared.
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*/
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#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
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static devclass_t rp_devclass;
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static int rp_pciprobe(device_t dev);
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static int rp_pciattach(device_t dev);
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#ifdef notdef
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static int rp_pcidetach(device_t dev);
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static int rp_pcishutdown(device_t dev);
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#endif /* notdef */
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static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
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static int sPCIInitController( CONTROLLER_t *CtlP,
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int AiopNum,
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int IRQNum,
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Byte_t Frequency,
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int PeriodicOnly,
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int VendorDevice);
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static rp_aiop2rid_t rp_pci_aiop2rid;
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static rp_aiop2off_t rp_pci_aiop2off;
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static rp_ctlmask_t rp_pci_ctlmask;
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/*
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* The following functions are the pci-specific part
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* of rp driver.
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*/
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static int
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rp_pciprobe(device_t dev)
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{
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char *s;
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s = NULL;
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if (pci_get_vendor(dev) == RP_VENDOR_ID)
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s = "RocketPort PCI";
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if (s != NULL) {
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device_set_desc(dev, s);
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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rp_pciattach(device_t dev)
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{
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int num_ports, num_aiops;
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int aiop;
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CONTROLLER_t *ctlp;
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int unit;
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int retval;
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ctlp = device_get_softc(dev);
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bzero(ctlp, sizeof(*ctlp));
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ctlp->dev = dev;
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unit = device_get_unit(dev);
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ctlp->aiop2rid = rp_pci_aiop2rid;
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ctlp->aiop2off = rp_pci_aiop2off;
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ctlp->ctlmask = rp_pci_ctlmask;
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/* The IO ports of AIOPs for a PCI controller are continuous. */
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ctlp->io_num = 1;
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ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
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ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
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if (ctlp->io_rid == NULL || ctlp->io == NULL) {
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device_printf(dev, "rp_pciattach: Out of memory.\n");
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retval = ENOMEM;
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goto nogo;
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}
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ctlp->bus_ctlp = NULL;
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switch (pci_get_device(dev)) {
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case RP_DEVICE_ID_UPCI_16:
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case RP_DEVICE_ID_UPCI_32:
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case RP_DEVICE_ID_UPCI_8O:
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ctlp->io_rid[0] = PCIR_BAR(2);
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break;
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default:
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ctlp->io_rid[0] = PCIR_BAR(0);
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break;
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}
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ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&ctlp->io_rid[0], RF_ACTIVE);
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if(ctlp->io[0] == NULL) {
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device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
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retval = ENXIO;
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goto nogo;
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}
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num_aiops = sPCIInitController(ctlp,
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MAX_AIOPS_PER_BOARD, 0,
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FREQ_DIS, 0, pci_get_device(dev));
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num_ports = 0;
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for(aiop=0; aiop < num_aiops; aiop++) {
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sResetAiopByNum(ctlp, aiop);
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num_ports += sGetAiopNumChan(ctlp, aiop);
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}
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retval = rp_attachcommon(ctlp, num_aiops, num_ports);
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if (retval != 0)
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goto nogo;
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return (0);
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nogo:
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rp_pcireleaseresource(ctlp);
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return (retval);
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}
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static int
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rp_pcidetach(device_t dev)
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{
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CONTROLLER_t *ctlp;
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ctlp = device_get_softc(dev);
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rp_pcireleaseresource(ctlp);
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return (0);
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}
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static int
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rp_pcishutdown(device_t dev)
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{
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CONTROLLER_t *ctlp;
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ctlp = device_get_softc(dev);
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rp_pcireleaseresource(ctlp);
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return (0);
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}
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static void
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rp_pcireleaseresource(CONTROLLER_t *ctlp)
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{
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rp_untimeout();
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if (ctlp->io != NULL) {
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if (ctlp->io[0] != NULL)
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bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
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free(ctlp->io, M_DEVBUF);
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ctlp->io = NULL;
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}
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if (ctlp->io_rid != NULL) {
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free(ctlp->io_rid, M_DEVBUF);
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ctlp->io = NULL;
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}
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rp_releaseresource(ctlp);
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}
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static int
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sPCIInitController( CONTROLLER_t *CtlP,
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int AiopNum,
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int IRQNum,
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Byte_t Frequency,
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int PeriodicOnly,
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int VendorDevice)
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{
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int i;
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CtlP->CtlID = CTLID_0001; /* controller release 1 */
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sPCIControllerEOI(CtlP);
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/* Init AIOPs */
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CtlP->NumAiop = 0;
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for(i=0; i < AiopNum; i++)
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{
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/*device_printf(CtlP->dev, "aiop %d.\n", i);*/
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CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
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/*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
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if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
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{
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break; /* done looking for AIOPs */
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}
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switch( VendorDevice ) {
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case RP_DEVICE_ID_4Q:
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case RP_DEVICE_ID_4J:
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case RP_DEVICE_ID_4M:
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CtlP->AiopNumChan[i] = 4;
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break;
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case RP_DEVICE_ID_6M:
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CtlP->AiopNumChan[i] = 6;
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break;
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case RP_DEVICE_ID_8O:
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case RP_DEVICE_ID_8J:
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case RP_DEVICE_ID_8I:
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case RP_DEVICE_ID_16I:
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case RP_DEVICE_ID_32I:
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CtlP->AiopNumChan[i] = 8;
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break;
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default:
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#ifdef notdef
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CtlP->AiopNumChan[i] = 8;
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#else
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CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
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#endif /* notdef */
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break;
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}
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/*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
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rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE); /* clock prescaler */
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/*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
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rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
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/*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
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CtlP->NumAiop++; /* bump count of AIOPs */
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}
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if(CtlP->NumAiop == 0)
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return(-1);
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else
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return(CtlP->NumAiop);
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}
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/*
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* ARGSUSED
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* Maps (aiop, offset) to rid.
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*/
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static int
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rp_pci_aiop2rid(int aiop, int offset)
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{
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/* Always return zero for a PCI controller. */
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return 0;
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}
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/*
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* ARGSUSED
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* Maps (aiop, offset) to the offset of resource.
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*/
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static int
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rp_pci_aiop2off(int aiop, int offset)
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{
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/* Each AIOP reserves 0x40 bytes. */
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return aiop * 0x40 + offset;
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}
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/* Read the int status for a PCI controller. */
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static unsigned char
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rp_pci_ctlmask(CONTROLLER_t *ctlp)
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{
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return sPCIGetControllerIntStatus(ctlp);
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}
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static device_method_t rp_pcimethods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rp_pciprobe),
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DEVMETHOD(device_attach, rp_pciattach),
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DEVMETHOD(device_detach, rp_pcidetach),
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DEVMETHOD(device_shutdown, rp_pcishutdown),
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{ 0, 0 }
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};
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static driver_t rp_pcidriver = {
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"rp",
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rp_pcimethods,
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sizeof(CONTROLLER_t),
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};
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/*
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* rp can be attached to a pci bus.
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*/
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DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
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