54912308c8
Move cxgbetool from tools/tools to usr.sbin. Compile and install it on platforms where cxgbe(4) is built by default. Knobs (WITH_CXGBETOOL and WITHOUT_CXGBETOOL) have been added so that the user can override the default setting. Reviewed by: ngie@, gnn@, bdrewery@ MFC after: 1 month Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D9854
40403 lines
1.1 MiB
40403 lines
1.1 MiB
/* This file is automatically generated --- changes will be lost */
|
|
/* Generation Date : Tue Dec 8 09:33:01 IST 2015 */
|
|
/* Directory name: t4_reg.txt, Changeset: */
|
|
__FBSDID("$FreeBSD$");
|
|
|
|
struct reg_info t4_sge_regs[] = {
|
|
{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1e004, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1e400, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1e404, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1e800, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1e804, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1ec00, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1ec04, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1f000, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1f004, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1f400, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1f404, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1f800, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1f804, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_PF_KDOORBELL", 0x1fc00, 0 },
|
|
{ "QID", 15, 17 },
|
|
{ "Priority", 14, 1 },
|
|
{ "PIDX", 0, 14 },
|
|
{ "SGE_PF_GTS", 0x1fc04, 0 },
|
|
{ "IngressQID", 16, 16 },
|
|
{ "TimerReg", 13, 3 },
|
|
{ "SEIntArm", 12, 1 },
|
|
{ "CIDXInc", 0, 12 },
|
|
{ "SGE_CONTROL", 0x1008, 0 },
|
|
{ "IgrAllCPLtoFL", 31, 1 },
|
|
{ "FLSplitMin", 22, 9 },
|
|
{ "FLSplitMode", 20, 2 },
|
|
{ "DCASysType", 19, 1 },
|
|
{ "RxPktCPLMode", 18, 1 },
|
|
{ "EgrStatusPageSize", 17, 1 },
|
|
{ "IngHintEnable1", 15, 1 },
|
|
{ "IngHintEnable0", 14, 1 },
|
|
{ "IngIntCompareIDX", 13, 1 },
|
|
{ "PktShift", 10, 3 },
|
|
{ "IngPCIeBoundary", 7, 3 },
|
|
{ "IngPadBoundary", 4, 3 },
|
|
{ "EgrPCIeBoundary", 1, 3 },
|
|
{ "GlobalEnable", 0, 1 },
|
|
{ "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
|
|
{ "HostPageSizePF7", 28, 4 },
|
|
{ "HostPageSizePF6", 24, 4 },
|
|
{ "HostPageSizePF5", 20, 4 },
|
|
{ "HostPageSizePF4", 16, 4 },
|
|
{ "HostPageSizePF3", 12, 4 },
|
|
{ "HostPageSizePF2", 8, 4 },
|
|
{ "HostPageSizePF1", 4, 4 },
|
|
{ "HostPageSizePF0", 0, 4 },
|
|
{ "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
|
|
{ "QueuesPerPagePF7", 28, 4 },
|
|
{ "QueuesPerPagePF6", 24, 4 },
|
|
{ "QueuesPerPagePF5", 20, 4 },
|
|
{ "QueuesPerPagePF4", 16, 4 },
|
|
{ "QueuesPerPagePF3", 12, 4 },
|
|
{ "QueuesPerPagePF2", 8, 4 },
|
|
{ "QueuesPerPagePF1", 4, 4 },
|
|
{ "QueuesPerPagePF0", 0, 4 },
|
|
{ "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
|
|
{ "QueuesPerPageVFPF7", 28, 4 },
|
|
{ "QueuesPerPageVFPF6", 24, 4 },
|
|
{ "QueuesPerPageVFPF5", 20, 4 },
|
|
{ "QueuesPerPageVFPF4", 16, 4 },
|
|
{ "QueuesPerPageVFPF3", 12, 4 },
|
|
{ "QueuesPerPageVFPF2", 8, 4 },
|
|
{ "QueuesPerPageVFPF1", 4, 4 },
|
|
{ "QueuesPerPageVFPF0", 0, 4 },
|
|
{ "SGE_USER_MODE_LIMITS", 0x1018, 0 },
|
|
{ "Opcode_Min", 24, 8 },
|
|
{ "Opcode_Max", 16, 8 },
|
|
{ "Length_Min", 8, 8 },
|
|
{ "Length_Max", 0, 8 },
|
|
{ "SGE_WR_ERROR", 0x101c, 0 },
|
|
{ "SGE_PERR_INJECT", 0x1020, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "SGE_INT_CAUSE1", 0x1024, 0 },
|
|
{ "perr_flm_CreditFifo", 30, 1 },
|
|
{ "perr_imsg_hint_fifo", 29, 1 },
|
|
{ "perr_mc_pc", 28, 1 },
|
|
{ "perr_mc_igr_ctxt", 27, 1 },
|
|
{ "perr_mc_egr_ctxt", 26, 1 },
|
|
{ "perr_mc_flm", 25, 1 },
|
|
{ "perr_pc_mctag", 24, 1 },
|
|
{ "perr_pc_chpi_rsp1", 23, 1 },
|
|
{ "perr_pc_chpi_rsp0", 22, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
|
|
{ "perr_dmarbt", 17, 1 },
|
|
{ "perr_flm_DbpFifo", 16, 1 },
|
|
{ "perr_flm_MCReq_fifo", 15, 1 },
|
|
{ "perr_flm_HintFifo", 14, 1 },
|
|
{ "perr_align_ctl_fifo3", 13, 1 },
|
|
{ "perr_align_ctl_fifo2", 12, 1 },
|
|
{ "perr_align_ctl_fifo1", 11, 1 },
|
|
{ "perr_align_ctl_fifo0", 10, 1 },
|
|
{ "perr_edma_fifo3", 9, 1 },
|
|
{ "perr_edma_fifo2", 8, 1 },
|
|
{ "perr_edma_fifo1", 7, 1 },
|
|
{ "perr_edma_fifo0", 6, 1 },
|
|
{ "perr_pd_fifo3", 5, 1 },
|
|
{ "perr_pd_fifo2", 4, 1 },
|
|
{ "perr_pd_fifo1", 3, 1 },
|
|
{ "perr_pd_fifo0", 2, 1 },
|
|
{ "perr_ing_ctxt_mifrsp", 1, 1 },
|
|
{ "perr_egr_ctxt_mifrsp", 0, 1 },
|
|
{ "SGE_INT_ENABLE1", 0x1028, 0 },
|
|
{ "perr_flm_CreditFifo", 30, 1 },
|
|
{ "perr_imsg_hint_fifo", 29, 1 },
|
|
{ "perr_mc_pc", 28, 1 },
|
|
{ "perr_mc_igr_ctxt", 27, 1 },
|
|
{ "perr_mc_egr_ctxt", 26, 1 },
|
|
{ "perr_mc_flm", 25, 1 },
|
|
{ "perr_pc_mctag", 24, 1 },
|
|
{ "perr_pc_chpi_rsp1", 23, 1 },
|
|
{ "perr_pc_chpi_rsp0", 22, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
|
|
{ "perr_dmarbt", 17, 1 },
|
|
{ "perr_flm_DbpFifo", 16, 1 },
|
|
{ "perr_flm_MCReq_fifo", 15, 1 },
|
|
{ "perr_flm_HintFifo", 14, 1 },
|
|
{ "perr_align_ctl_fifo3", 13, 1 },
|
|
{ "perr_align_ctl_fifo2", 12, 1 },
|
|
{ "perr_align_ctl_fifo1", 11, 1 },
|
|
{ "perr_align_ctl_fifo0", 10, 1 },
|
|
{ "perr_edma_fifo3", 9, 1 },
|
|
{ "perr_edma_fifo2", 8, 1 },
|
|
{ "perr_edma_fifo1", 7, 1 },
|
|
{ "perr_edma_fifo0", 6, 1 },
|
|
{ "perr_pd_fifo3", 5, 1 },
|
|
{ "perr_pd_fifo2", 4, 1 },
|
|
{ "perr_pd_fifo1", 3, 1 },
|
|
{ "perr_pd_fifo0", 2, 1 },
|
|
{ "perr_ing_ctxt_mifrsp", 1, 1 },
|
|
{ "perr_egr_ctxt_mifrsp", 0, 1 },
|
|
{ "SGE_PERR_ENABLE1", 0x102c, 0 },
|
|
{ "perr_flm_CreditFifo", 30, 1 },
|
|
{ "perr_imsg_hint_fifo", 29, 1 },
|
|
{ "perr_mc_pc", 28, 1 },
|
|
{ "perr_mc_igr_ctxt", 27, 1 },
|
|
{ "perr_mc_egr_ctxt", 26, 1 },
|
|
{ "perr_mc_flm", 25, 1 },
|
|
{ "perr_pc_mctag", 24, 1 },
|
|
{ "perr_pc_chpi_rsp1", 23, 1 },
|
|
{ "perr_pc_chpi_rsp0", 22, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
|
|
{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
|
|
{ "perr_dmarbt", 17, 1 },
|
|
{ "perr_flm_DbpFifo", 16, 1 },
|
|
{ "perr_flm_MCReq_fifo", 15, 1 },
|
|
{ "perr_flm_HintFifo", 14, 1 },
|
|
{ "perr_align_ctl_fifo3", 13, 1 },
|
|
{ "perr_align_ctl_fifo2", 12, 1 },
|
|
{ "perr_align_ctl_fifo1", 11, 1 },
|
|
{ "perr_align_ctl_fifo0", 10, 1 },
|
|
{ "perr_edma_fifo3", 9, 1 },
|
|
{ "perr_edma_fifo2", 8, 1 },
|
|
{ "perr_edma_fifo1", 7, 1 },
|
|
{ "perr_edma_fifo0", 6, 1 },
|
|
{ "perr_pd_fifo3", 5, 1 },
|
|
{ "perr_pd_fifo2", 4, 1 },
|
|
{ "perr_pd_fifo1", 3, 1 },
|
|
{ "perr_pd_fifo0", 2, 1 },
|
|
{ "perr_ing_ctxt_mifrsp", 1, 1 },
|
|
{ "perr_egr_ctxt_mifrsp", 0, 1 },
|
|
{ "SGE_INT_CAUSE2", 0x1030, 0 },
|
|
{ "perr_hint_delay_fifo1", 30, 1 },
|
|
{ "perr_hint_delay_fifo0", 29, 1 },
|
|
{ "perr_imsg_pd_fifo", 28, 1 },
|
|
{ "perr_ulptx_fifo1", 27, 1 },
|
|
{ "perr_ulptx_fifo0", 26, 1 },
|
|
{ "perr_idma2imsg_fifo1", 25, 1 },
|
|
{ "perr_idma2imsg_fifo0", 24, 1 },
|
|
{ "perr_headersplit_fifo1", 23, 1 },
|
|
{ "perr_headersplit_fifo0", 22, 1 },
|
|
{ "perr_eswitch_fifo3", 21, 1 },
|
|
{ "perr_eswitch_fifo2", 20, 1 },
|
|
{ "perr_eswitch_fifo1", 19, 1 },
|
|
{ "perr_eswitch_fifo0", 18, 1 },
|
|
{ "perr_pc_dbp1", 17, 1 },
|
|
{ "perr_pc_dbp0", 16, 1 },
|
|
{ "perr_imsg_ob_fifo", 15, 1 },
|
|
{ "perr_conm_sram", 14, 1 },
|
|
{ "perr_pc_mc_rsp", 13, 1 },
|
|
{ "perr_isw_idma0_fifo", 12, 1 },
|
|
{ "perr_isw_idma1_fifo", 11, 1 },
|
|
{ "perr_isw_dbp_fifo", 10, 1 },
|
|
{ "perr_isw_gts_fifo", 9, 1 },
|
|
{ "perr_itp_evr", 8, 1 },
|
|
{ "perr_flm_cntxmem", 7, 1 },
|
|
{ "perr_flm_l1Cache", 6, 1 },
|
|
{ "perr_dbp_hint_fifo", 5, 1 },
|
|
{ "perr_dbp_hp_fifo", 4, 1 },
|
|
{ "perr_dbp_lp_fifo", 3, 1 },
|
|
{ "perr_ing_ctxt_cache", 2, 1 },
|
|
{ "perr_egr_ctxt_cache", 1, 1 },
|
|
{ "perr_base_size", 0, 1 },
|
|
{ "SGE_INT_ENABLE2", 0x1034, 0 },
|
|
{ "perr_hint_delay_fifo1", 30, 1 },
|
|
{ "perr_hint_delay_fifo0", 29, 1 },
|
|
{ "perr_imsg_pd_fifo", 28, 1 },
|
|
{ "perr_ulptx_fifo1", 27, 1 },
|
|
{ "perr_ulptx_fifo0", 26, 1 },
|
|
{ "perr_idma2imsg_fifo1", 25, 1 },
|
|
{ "perr_idma2imsg_fifo0", 24, 1 },
|
|
{ "perr_headersplit_fifo1", 23, 1 },
|
|
{ "perr_headersplit_fifo0", 22, 1 },
|
|
{ "perr_eswitch_fifo3", 21, 1 },
|
|
{ "perr_eswitch_fifo2", 20, 1 },
|
|
{ "perr_eswitch_fifo1", 19, 1 },
|
|
{ "perr_eswitch_fifo0", 18, 1 },
|
|
{ "perr_pc_dbp1", 17, 1 },
|
|
{ "perr_pc_dbp0", 16, 1 },
|
|
{ "perr_imsg_ob_fifo", 15, 1 },
|
|
{ "perr_conm_sram", 14, 1 },
|
|
{ "perr_pc_mc_rsp", 13, 1 },
|
|
{ "perr_isw_idma0_fifo", 12, 1 },
|
|
{ "perr_isw_idma1_fifo", 11, 1 },
|
|
{ "perr_isw_dbp_fifo", 10, 1 },
|
|
{ "perr_isw_gts_fifo", 9, 1 },
|
|
{ "perr_itp_evr", 8, 1 },
|
|
{ "perr_flm_cntxmem", 7, 1 },
|
|
{ "perr_flm_l1Cache", 6, 1 },
|
|
{ "perr_dbp_hint_fifo", 5, 1 },
|
|
{ "perr_dbp_hp_fifo", 4, 1 },
|
|
{ "perr_dbp_lp_fifo", 3, 1 },
|
|
{ "perr_ing_ctxt_cache", 2, 1 },
|
|
{ "perr_egr_ctxt_cache", 1, 1 },
|
|
{ "perr_base_size", 0, 1 },
|
|
{ "SGE_PERR_ENABLE2", 0x1038, 0 },
|
|
{ "perr_hint_delay_fifo1", 30, 1 },
|
|
{ "perr_hint_delay_fifo0", 29, 1 },
|
|
{ "perr_imsg_pd_fifo", 28, 1 },
|
|
{ "perr_ulptx_fifo1", 27, 1 },
|
|
{ "perr_ulptx_fifo0", 26, 1 },
|
|
{ "perr_idma2imsg_fifo1", 25, 1 },
|
|
{ "perr_idma2imsg_fifo0", 24, 1 },
|
|
{ "perr_headersplit_fifo1", 23, 1 },
|
|
{ "perr_headersplit_fifo0", 22, 1 },
|
|
{ "perr_eswitch_fifo3", 21, 1 },
|
|
{ "perr_eswitch_fifo2", 20, 1 },
|
|
{ "perr_eswitch_fifo1", 19, 1 },
|
|
{ "perr_eswitch_fifo0", 18, 1 },
|
|
{ "perr_pc_dbp1", 17, 1 },
|
|
{ "perr_pc_dbp0", 16, 1 },
|
|
{ "perr_imsg_ob_fifo", 15, 1 },
|
|
{ "perr_conm_sram", 14, 1 },
|
|
{ "perr_pc_mc_rsp", 13, 1 },
|
|
{ "perr_isw_idma0_fifo", 12, 1 },
|
|
{ "perr_isw_idma1_fifo", 11, 1 },
|
|
{ "perr_isw_dbp_fifo", 10, 1 },
|
|
{ "perr_isw_gts_fifo", 9, 1 },
|
|
{ "perr_itp_evr", 8, 1 },
|
|
{ "perr_flm_cntxmem", 7, 1 },
|
|
{ "perr_flm_l1Cache", 6, 1 },
|
|
{ "perr_dbp_hint_fifo", 5, 1 },
|
|
{ "perr_dbp_hp_fifo", 4, 1 },
|
|
{ "perr_dbp_lp_fifo", 3, 1 },
|
|
{ "perr_ing_ctxt_cache", 2, 1 },
|
|
{ "perr_egr_ctxt_cache", 1, 1 },
|
|
{ "perr_base_size", 0, 1 },
|
|
{ "SGE_INT_CAUSE3", 0x103c, 0 },
|
|
{ "err_flm_dbp", 31, 1 },
|
|
{ "err_flm_idma1", 30, 1 },
|
|
{ "err_flm_idma0", 29, 1 },
|
|
{ "err_flm_hint", 28, 1 },
|
|
{ "err_pcie_error3", 27, 1 },
|
|
{ "err_pcie_error2", 26, 1 },
|
|
{ "err_pcie_error1", 25, 1 },
|
|
{ "err_pcie_error0", 24, 1 },
|
|
{ "err_timer_above_max_qid", 23, 1 },
|
|
{ "err_cpl_exceed_iqe_size", 22, 1 },
|
|
{ "err_invalid_cidx_inc", 21, 1 },
|
|
{ "err_itp_time_paused", 20, 1 },
|
|
{ "err_cpl_opcode_0", 19, 1 },
|
|
{ "err_dropped_db", 18, 1 },
|
|
{ "err_data_cpl_on_high_qid1", 17, 1 },
|
|
{ "err_data_cpl_on_high_qid0", 16, 1 },
|
|
{ "err_bad_db_pidx3", 15, 1 },
|
|
{ "err_bad_db_pidx2", 14, 1 },
|
|
{ "err_bad_db_pidx1", 13, 1 },
|
|
{ "err_bad_db_pidx0", 12, 1 },
|
|
{ "err_ing_pcie_chan", 11, 1 },
|
|
{ "err_ing_ctxt_prio", 10, 1 },
|
|
{ "err_egr_ctxt_prio", 9, 1 },
|
|
{ "dbfifo_hp_int", 8, 1 },
|
|
{ "dbfifo_lp_int", 7, 1 },
|
|
{ "reg_address_err", 6, 1 },
|
|
{ "ingress_size_err", 5, 1 },
|
|
{ "egress_size_err", 4, 1 },
|
|
{ "err_inv_ctxt3", 3, 1 },
|
|
{ "err_inv_ctxt2", 2, 1 },
|
|
{ "err_inv_ctxt1", 1, 1 },
|
|
{ "err_inv_ctxt0", 0, 1 },
|
|
{ "SGE_INT_ENABLE3", 0x1040, 0 },
|
|
{ "err_flm_dbp", 31, 1 },
|
|
{ "err_flm_idma1", 30, 1 },
|
|
{ "err_flm_idma0", 29, 1 },
|
|
{ "err_flm_hint", 28, 1 },
|
|
{ "err_pcie_error3", 27, 1 },
|
|
{ "err_pcie_error2", 26, 1 },
|
|
{ "err_pcie_error1", 25, 1 },
|
|
{ "err_pcie_error0", 24, 1 },
|
|
{ "err_timer_above_max_qid", 23, 1 },
|
|
{ "err_cpl_exceed_iqe_size", 22, 1 },
|
|
{ "err_invalid_cidx_inc", 21, 1 },
|
|
{ "err_itp_time_paused", 20, 1 },
|
|
{ "err_cpl_opcode_0", 19, 1 },
|
|
{ "err_dropped_db", 18, 1 },
|
|
{ "err_data_cpl_on_high_qid1", 17, 1 },
|
|
{ "err_data_cpl_on_high_qid0", 16, 1 },
|
|
{ "err_bad_db_pidx3", 15, 1 },
|
|
{ "err_bad_db_pidx2", 14, 1 },
|
|
{ "err_bad_db_pidx1", 13, 1 },
|
|
{ "err_bad_db_pidx0", 12, 1 },
|
|
{ "err_ing_pcie_chan", 11, 1 },
|
|
{ "err_ing_ctxt_prio", 10, 1 },
|
|
{ "err_egr_ctxt_prio", 9, 1 },
|
|
{ "dbfifo_hp_int", 8, 1 },
|
|
{ "dbfifo_lp_int", 7, 1 },
|
|
{ "reg_address_err", 6, 1 },
|
|
{ "ingress_size_err", 5, 1 },
|
|
{ "egress_size_err", 4, 1 },
|
|
{ "err_inv_ctxt3", 3, 1 },
|
|
{ "err_inv_ctxt2", 2, 1 },
|
|
{ "err_inv_ctxt1", 1, 1 },
|
|
{ "err_inv_ctxt0", 0, 1 },
|
|
{ "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_FLM_CFG", 0x1090, 0 },
|
|
{ "OpMode", 26, 6 },
|
|
{ "NoHdr", 18, 1 },
|
|
{ "CachePtrCnt", 16, 2 },
|
|
{ "EDRAMPtrCnt", 14, 2 },
|
|
{ "HdrStartFLQ", 11, 3 },
|
|
{ "FetchThresh", 6, 5 },
|
|
{ "CreditCnt", 4, 2 },
|
|
{ "NoEDRAM", 0, 1 },
|
|
{ "SGE_CONM_CTRL", 0x1094, 0 },
|
|
{ "EgrThreshold", 8, 6 },
|
|
{ "IngThreshold", 2, 6 },
|
|
{ "MPS_Enable", 1, 1 },
|
|
{ "TP_Enable", 0, 1 },
|
|
{ "SGE_TIMESTAMP_LO", 0x1098, 0 },
|
|
{ "SGE_TIMESTAMP_HI", 0x109c, 0 },
|
|
{ "Opcode", 28, 2 },
|
|
{ "Value", 0, 28 },
|
|
{ "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
|
|
{ "Threshold_0", 24, 6 },
|
|
{ "Threshold_1", 16, 6 },
|
|
{ "Threshold_2", 8, 6 },
|
|
{ "Threshold_3", 0, 6 },
|
|
{ "SGE_DBFIFO_STATUS", 0x10a4, 0 },
|
|
{ "HP_Int_Thresh", 28, 4 },
|
|
{ "HP_Count", 16, 11 },
|
|
{ "LP_Int_Thresh", 12, 4 },
|
|
{ "LP_Count", 0, 11 },
|
|
{ "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
|
|
{ "HintDepthCtl", 27, 5 },
|
|
{ "NoCoalesce", 26, 1 },
|
|
{ "HP_Weight", 24, 2 },
|
|
{ "HP_Disable", 23, 1 },
|
|
{ "ForceUserDBtoLP", 22, 1 },
|
|
{ "ForceVFPF0DBtoLP", 21, 1 },
|
|
{ "ForceVFPF1DBtoLP", 20, 1 },
|
|
{ "ForceVFPF2DBtoLP", 19, 1 },
|
|
{ "ForceVFPF3DBtoLP", 18, 1 },
|
|
{ "ForceVFPF4DBtoLP", 17, 1 },
|
|
{ "ForceVFPF5DBtoLP", 16, 1 },
|
|
{ "ForceVFPF6DBtoLP", 15, 1 },
|
|
{ "ForceVFPF7DBtoLP", 14, 1 },
|
|
{ "Enable_Drop", 13, 1 },
|
|
{ "Drop_Timeout", 1, 12 },
|
|
{ "Dropped_DB", 0, 1 },
|
|
{ "SGE_DROPPED_DOORBELL", 0x10ac, 0 },
|
|
{ "SGE_DOORBELL_THROTTLE_CONTROL", 0x10b0, 0 },
|
|
{ "Throttle_Count", 1, 12 },
|
|
{ "Throttle_Enable", 0, 1 },
|
|
{ "SGE_ITP_CONTROL", 0x10b4, 0 },
|
|
{ "Critical_Time", 10, 15 },
|
|
{ "LL_Empty", 4, 6 },
|
|
{ "LL_Read_Wait_Disable", 0, 1 },
|
|
{ "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
|
|
{ "TimerValue0", 16, 16 },
|
|
{ "TimerValue1", 0, 16 },
|
|
{ "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
|
|
{ "TimerValue2", 16, 16 },
|
|
{ "TimerValue3", 0, 16 },
|
|
{ "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
|
|
{ "TimerValue4", 16, 16 },
|
|
{ "TimerValue5", 0, 16 },
|
|
{ "SGE_PD_RSP_CREDIT01", 0x10c4, 0 },
|
|
{ "RspCreditEn0", 31, 1 },
|
|
{ "MaxTag0", 24, 7 },
|
|
{ "MaxRspCnt0", 16, 8 },
|
|
{ "RspCreditEn1", 15, 1 },
|
|
{ "MaxTag1", 8, 7 },
|
|
{ "MaxRspCnt1", 0, 8 },
|
|
{ "SGE_PD_RSP_CREDIT23", 0x10c8, 0 },
|
|
{ "RspCreditEn2", 31, 1 },
|
|
{ "MaxTag2", 24, 7 },
|
|
{ "MaxRspCnt2", 16, 8 },
|
|
{ "RspCreditEn3", 15, 1 },
|
|
{ "MaxTag3", 8, 7 },
|
|
{ "MaxRspCnt3", 0, 8 },
|
|
{ "SGE_DEBUG_INDEX", 0x10cc, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
|
|
{ "SGE_REVISION", 0x10d8, 0 },
|
|
{ "SGE_INT_CAUSE4", 0x10dc, 0 },
|
|
{ "err_bad_upfl_inc_credit3", 8, 1 },
|
|
{ "err_bad_upfl_inc_credit2", 7, 1 },
|
|
{ "err_bad_upfl_inc_credit1", 6, 1 },
|
|
{ "err_bad_upfl_inc_credit0", 5, 1 },
|
|
{ "err_physaddr_len0_idma1", 4, 1 },
|
|
{ "err_physaddr_len0_idma0", 3, 1 },
|
|
{ "err_flm_invalid_pkt_drop1", 2, 1 },
|
|
{ "err_flm_invalid_pkt_drop0", 1, 1 },
|
|
{ "err_unexpected_timer", 0, 1 },
|
|
{ "SGE_INT_ENABLE4", 0x10e0, 0 },
|
|
{ "err_bad_upfl_inc_credit3", 8, 1 },
|
|
{ "err_bad_upfl_inc_credit2", 7, 1 },
|
|
{ "err_bad_upfl_inc_credit1", 6, 1 },
|
|
{ "err_bad_upfl_inc_credit0", 5, 1 },
|
|
{ "err_physaddr_len0_idma1", 4, 1 },
|
|
{ "err_physaddr_len0_idma0", 3, 1 },
|
|
{ "err_flm_invalid_pkt_drop1", 2, 1 },
|
|
{ "err_flm_invalid_pkt_drop0", 1, 1 },
|
|
{ "err_unexpected_timer", 0, 1 },
|
|
{ "SGE_STAT_TOTAL", 0x10e4, 0 },
|
|
{ "SGE_STAT_MATCH", 0x10e8, 0 },
|
|
{ "SGE_STAT_CFG", 0x10ec, 0 },
|
|
{ "ITPOpMode", 8, 1 },
|
|
{ "EgrCtxtOpMode", 6, 2 },
|
|
{ "IngCtxtOpMode", 4, 2 },
|
|
{ "StatMode", 2, 2 },
|
|
{ "StatSource", 0, 2 },
|
|
{ "SGE_HINT_CFG", 0x10f0, 0 },
|
|
{ "HintsAllowedNoHdr", 6, 6 },
|
|
{ "HintsAllowedHdr", 0, 6 },
|
|
{ "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
|
|
{ "QueuesPerPagePF7", 28, 4 },
|
|
{ "QueuesPerPagePF6", 24, 4 },
|
|
{ "QueuesPerPagePF5", 20, 4 },
|
|
{ "QueuesPerPagePF4", 16, 4 },
|
|
{ "QueuesPerPagePF3", 12, 4 },
|
|
{ "QueuesPerPagePF2", 8, 4 },
|
|
{ "QueuesPerPagePF1", 4, 4 },
|
|
{ "QueuesPerPagePF0", 0, 4 },
|
|
{ "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
|
|
{ "QueuesPerPageVFPF7", 28, 4 },
|
|
{ "QueuesPerPageVFPF6", 24, 4 },
|
|
{ "QueuesPerPageVFPF5", 20, 4 },
|
|
{ "QueuesPerPageVFPF4", 16, 4 },
|
|
{ "QueuesPerPageVFPF3", 12, 4 },
|
|
{ "QueuesPerPageVFPF2", 8, 4 },
|
|
{ "QueuesPerPageVFPF1", 4, 4 },
|
|
{ "QueuesPerPageVFPF0", 0, 4 },
|
|
{ "SGE_PD_WRR_CONFIG", 0x10fc, 0 },
|
|
{ "SGE_ERROR_STATS", 0x1100, 0 },
|
|
{ "Uncaptured_Error", 18, 1 },
|
|
{ "Error_QID_Valid", 17, 1 },
|
|
{ "Error_QID", 0, 17 },
|
|
{ "SGE_SHARED_TAG_CHAN_CFG", 0x1104, 0 },
|
|
{ "MinTag3", 24, 8 },
|
|
{ "MinTag2", 16, 8 },
|
|
{ "MinTag1", 8, 8 },
|
|
{ "MinTag0", 0, 8 },
|
|
{ "SGE_SHARED_TAG_POOL_CFG", 0x1108, 0 },
|
|
{ "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
|
|
{ "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
|
|
{ "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
|
|
{ "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
|
|
{ "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
|
|
{ "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
|
|
{ "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
|
|
{ "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
|
|
{ "SGE_CTXT_CMD", 0x11fc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Opcode", 28, 2 },
|
|
{ "CtxtType", 24, 2 },
|
|
{ "QID", 0, 17 },
|
|
{ "SGE_CTXT_DATA0", 0x1200, 0 },
|
|
{ "SGE_CTXT_DATA1", 0x1204, 0 },
|
|
{ "SGE_CTXT_DATA2", 0x1208, 0 },
|
|
{ "SGE_CTXT_DATA3", 0x120c, 0 },
|
|
{ "SGE_CTXT_DATA4", 0x1210, 0 },
|
|
{ "SGE_CTXT_DATA5", 0x1214, 0 },
|
|
{ "SGE_CTXT_DATA6", 0x1218, 0 },
|
|
{ "SGE_CTXT_DATA7", 0x121c, 0 },
|
|
{ "SGE_CTXT_MASK0", 0x1220, 0 },
|
|
{ "SGE_CTXT_MASK1", 0x1224, 0 },
|
|
{ "SGE_CTXT_MASK2", 0x1228, 0 },
|
|
{ "SGE_CTXT_MASK3", 0x122c, 0 },
|
|
{ "SGE_CTXT_MASK4", 0x1230, 0 },
|
|
{ "SGE_CTXT_MASK5", 0x1234, 0 },
|
|
{ "SGE_CTXT_MASK6", 0x1238, 0 },
|
|
{ "SGE_CTXT_MASK7", 0x123c, 0 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1300, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1308, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1310, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1318, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1320, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1328, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1330, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1338, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1340, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1348, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1350, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1358, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1360, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1368, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1370, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1378, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1380, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1388, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1390, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1398, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13a0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13a8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13b0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13b8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13c0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13c8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13d0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13d8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13e0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13e8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13f0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13f8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1400, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1408, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1410, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1418, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1420, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1428, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1430, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1438, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1440, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1448, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1450, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1458, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1460, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1468, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1470, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1478, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1480, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1488, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1490, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1498, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14a0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14a8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14b0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14b8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14c0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14c8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14d0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14d8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14e0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14e8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14f0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14f8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1500, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1508, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1510, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1518, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1520, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1528, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1530, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1538, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1540, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1548, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1550, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1558, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1560, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1568, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1570, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1578, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1580, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1588, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1590, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1598, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15a0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15a8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15b0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15b8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15c0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15c8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15d0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15d8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15e0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15e8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15f0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15f8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1600, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1608, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1610, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1618, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1620, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1628, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1630, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1638, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1640, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1648, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1650, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1658, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1660, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1668, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1670, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1678, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1680, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1688, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1690, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1698, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16a0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16a8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16b0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16b8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16c0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16c8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16d0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16d8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16e0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16e8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16f0, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16f8, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1700, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1708, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1710, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1718, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1720, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1728, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1730, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1738, 0 },
|
|
{ "Egress_Log2Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Log2Size", 5, 5 },
|
|
{ "Ingress1_Log2Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1304, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x130c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1314, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x131c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1324, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x132c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1334, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x133c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1344, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x134c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1354, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x135c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1364, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x136c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1374, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x137c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1384, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x138c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1394, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x139c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1404, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x140c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1414, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x141c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1424, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x142c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1434, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x143c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1444, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x144c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1454, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x145c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1464, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x146c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1474, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x147c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1484, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x148c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1494, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x149c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1504, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x150c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1514, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x151c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1524, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x152c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1534, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x153c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1544, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x154c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1554, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x155c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1564, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x156c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1574, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x157c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1584, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x158c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1594, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x159c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1604, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x160c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1614, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x161c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1624, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x162c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1634, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x163c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1644, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x164c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1654, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x165c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1664, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x166c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1674, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x167c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1684, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x168c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1694, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x169c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1704, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x170c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1714, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x171c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1724, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x172c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1734, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x173c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_LA_RDPTR_0", 0x1800, 0 },
|
|
{ "SGE_LA_RDDATA_0", 0x1804, 0 },
|
|
{ "SGE_LA_WRPTR_0", 0x1808, 0 },
|
|
{ "SGE_LA_RESERVED_0", 0x180c, 0 },
|
|
{ "SGE_LA_RDPTR_1", 0x1810, 0 },
|
|
{ "SGE_LA_RDDATA_1", 0x1814, 0 },
|
|
{ "SGE_LA_WRPTR_1", 0x1818, 0 },
|
|
{ "SGE_LA_RESERVED_1", 0x181c, 0 },
|
|
{ "SGE_LA_RDPTR_2", 0x1820, 0 },
|
|
{ "SGE_LA_RDDATA_2", 0x1824, 0 },
|
|
{ "SGE_LA_WRPTR_2", 0x1828, 0 },
|
|
{ "SGE_LA_RESERVED_2", 0x182c, 0 },
|
|
{ "SGE_LA_RDPTR_3", 0x1830, 0 },
|
|
{ "SGE_LA_RDDATA_3", 0x1834, 0 },
|
|
{ "SGE_LA_WRPTR_3", 0x1838, 0 },
|
|
{ "SGE_LA_RESERVED_3", 0x183c, 0 },
|
|
{ "SGE_LA_RDPTR_4", 0x1840, 0 },
|
|
{ "SGE_LA_RDDATA_4", 0x1844, 0 },
|
|
{ "SGE_LA_WRPTR_4", 0x1848, 0 },
|
|
{ "SGE_LA_RESERVED_4", 0x184c, 0 },
|
|
{ "SGE_LA_RDPTR_5", 0x1850, 0 },
|
|
{ "SGE_LA_RDDATA_5", 0x1854, 0 },
|
|
{ "SGE_LA_WRPTR_5", 0x1858, 0 },
|
|
{ "SGE_LA_RESERVED_5", 0x185c, 0 },
|
|
{ "SGE_LA_RDPTR_6", 0x1860, 0 },
|
|
{ "SGE_LA_RDDATA_6", 0x1864, 0 },
|
|
{ "SGE_LA_WRPTR_6", 0x1868, 0 },
|
|
{ "SGE_LA_RESERVED_6", 0x186c, 0 },
|
|
{ "SGE_LA_RDPTR_7", 0x1870, 0 },
|
|
{ "SGE_LA_RDDATA_7", 0x1874, 0 },
|
|
{ "SGE_LA_WRPTR_7", 0x1878, 0 },
|
|
{ "SGE_LA_RESERVED_7", 0x187c, 0 },
|
|
{ "SGE_LA_RDPTR_8", 0x1880, 0 },
|
|
{ "SGE_LA_RDDATA_8", 0x1884, 0 },
|
|
{ "SGE_LA_WRPTR_8", 0x1888, 0 },
|
|
{ "SGE_LA_RESERVED_8", 0x188c, 0 },
|
|
{ "SGE_LA_RDPTR_9", 0x1890, 0 },
|
|
{ "SGE_LA_RDDATA_9", 0x1894, 0 },
|
|
{ "SGE_LA_WRPTR_9", 0x1898, 0 },
|
|
{ "SGE_LA_RESERVED_9", 0x189c, 0 },
|
|
{ "SGE_LA_RDPTR_10", 0x18a0, 0 },
|
|
{ "SGE_LA_RDDATA_10", 0x18a4, 0 },
|
|
{ "SGE_LA_WRPTR_10", 0x18a8, 0 },
|
|
{ "SGE_LA_RESERVED_10", 0x18ac, 0 },
|
|
{ "SGE_LA_RDPTR_11", 0x18b0, 0 },
|
|
{ "SGE_LA_RDDATA_11", 0x18b4, 0 },
|
|
{ "SGE_LA_WRPTR_11", 0x18b8, 0 },
|
|
{ "SGE_LA_RESERVED_11", 0x18bc, 0 },
|
|
{ "SGE_LA_RDPTR_12", 0x18c0, 0 },
|
|
{ "SGE_LA_RDDATA_12", 0x18c4, 0 },
|
|
{ "SGE_LA_WRPTR_12", 0x18c8, 0 },
|
|
{ "SGE_LA_RESERVED_12", 0x18cc, 0 },
|
|
{ "SGE_LA_RDPTR_13", 0x18d0, 0 },
|
|
{ "SGE_LA_RDDATA_13", 0x18d4, 0 },
|
|
{ "SGE_LA_WRPTR_13", 0x18d8, 0 },
|
|
{ "SGE_LA_RESERVED_13", 0x18dc, 0 },
|
|
{ "SGE_LA_RDPTR_14", 0x18e0, 0 },
|
|
{ "SGE_LA_RDDATA_14", 0x18e4, 0 },
|
|
{ "SGE_LA_WRPTR_14", 0x18e8, 0 },
|
|
{ "SGE_LA_RESERVED_14", 0x18ec, 0 },
|
|
{ "SGE_LA_RDPTR_15", 0x18f0, 0 },
|
|
{ "SGE_LA_RDDATA_15", 0x18f4, 0 },
|
|
{ "SGE_LA_WRPTR_15", 0x18f8, 0 },
|
|
{ "SGE_LA_RESERVED_15", 0x18fc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_pcie_regs[] = {
|
|
{ "PCIE_INT_ENABLE", 0x3000, 0 },
|
|
{ "NonFatalErr", 30, 1 },
|
|
{ "UnxSplCplErr", 29, 1 },
|
|
{ "PCIEPINT", 28, 1 },
|
|
{ "PCIESINT", 27, 1 },
|
|
{ "RPLPerr", 26, 1 },
|
|
{ "RxWrPerr", 25, 1 },
|
|
{ "RxCplPerr", 24, 1 },
|
|
{ "PIOTagPerr", 23, 1 },
|
|
{ "MATagPerr", 22, 1 },
|
|
{ "INTXClrPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqPerr", 17, 1 },
|
|
{ "HCntPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqPerr", 14, 1 },
|
|
{ "DCntPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqPerr", 11, 1 },
|
|
{ "CCntPerr", 10, 1 },
|
|
{ "TARTagPerr", 9, 1 },
|
|
{ "PIOReqPerr", 8, 1 },
|
|
{ "PIOCplPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIDataPerr", 2, 1 },
|
|
{ "MSIAddrHPerr", 1, 1 },
|
|
{ "MSIAddrLPerr", 0, 1 },
|
|
{ "PCIE_INT_CAUSE", 0x3004, 0 },
|
|
{ "NonFatalErr", 30, 1 },
|
|
{ "UnxSplCplErr", 29, 1 },
|
|
{ "PCIEPINT", 28, 1 },
|
|
{ "PCIESINT", 27, 1 },
|
|
{ "RPLPerr", 26, 1 },
|
|
{ "RxWrPerr", 25, 1 },
|
|
{ "RxCplPerr", 24, 1 },
|
|
{ "PIOTagPerr", 23, 1 },
|
|
{ "MATagPerr", 22, 1 },
|
|
{ "INTXClrPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqPerr", 17, 1 },
|
|
{ "HCntPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqPerr", 14, 1 },
|
|
{ "DCntPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqPerr", 11, 1 },
|
|
{ "CCntPerr", 10, 1 },
|
|
{ "TARTagPerr", 9, 1 },
|
|
{ "PIOReqPerr", 8, 1 },
|
|
{ "PIOCplPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIDataPerr", 2, 1 },
|
|
{ "MSIAddrHPerr", 1, 1 },
|
|
{ "MSIAddrLPerr", 0, 1 },
|
|
{ "PCIE_PERR_ENABLE", 0x3008, 0 },
|
|
{ "RPLPerr", 26, 1 },
|
|
{ "RxWrPerr", 25, 1 },
|
|
{ "RxCplPerr", 24, 1 },
|
|
{ "PIOTagPerr", 23, 1 },
|
|
{ "MATagPerr", 22, 1 },
|
|
{ "INTXClrPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqPerr", 17, 1 },
|
|
{ "HCntPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqPerr", 14, 1 },
|
|
{ "DCntPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqPerr", 11, 1 },
|
|
{ "CCntPerr", 10, 1 },
|
|
{ "TARTagPerr", 9, 1 },
|
|
{ "PIOReqPerr", 8, 1 },
|
|
{ "PIOCplPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIDataPerr", 2, 1 },
|
|
{ "MSIAddrHPerr", 1, 1 },
|
|
{ "MSIAddrLPerr", 0, 1 },
|
|
{ "PCIE_PERR_INJECT", 0x300c, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "IDE", 0, 1 },
|
|
{ "PCIE_NONFAT_ERR", 0x3010, 0 },
|
|
{ "RdRspErr", 9, 1 },
|
|
{ "VPDRspErr", 8, 1 },
|
|
{ "PopD", 7, 1 },
|
|
{ "PopH", 6, 1 },
|
|
{ "PopC", 5, 1 },
|
|
{ "MemReq", 4, 1 },
|
|
{ "PIOReq", 3, 1 },
|
|
{ "TagDrop", 2, 1 },
|
|
{ "TagCpl", 1, 1 },
|
|
{ "CfgSnp", 0, 1 },
|
|
{ "PCIE_CFG", 0x3014, 0 },
|
|
{ "CfgdMaxPyldSzRx", 26, 3 },
|
|
{ "CfgdMaxPyldSzTx", 23, 3 },
|
|
{ "CfgdMaxRdReqSz", 20, 3 },
|
|
{ "MASyncEn", 19, 1 },
|
|
{ "DCAEnDMA", 18, 1 },
|
|
{ "DCAEnCMD", 17, 1 },
|
|
{ "VFMSIPndEn", 16, 1 },
|
|
{ "ForceTxError", 15, 1 },
|
|
{ "VPDReqProtect", 14, 1 },
|
|
{ "FIDTableInvalid", 13, 1 },
|
|
{ "BypassMSIXCache", 12, 1 },
|
|
{ "BypassMSICache", 11, 1 },
|
|
{ "SimSpeed", 10, 1 },
|
|
{ "TC0_Stamp", 9, 1 },
|
|
{ "AI_TCVal", 6, 3 },
|
|
{ "DMAStopEn", 5, 1 },
|
|
{ "DevStateRstMode", 4, 1 },
|
|
{ "HotRstPCIeCRstMode", 3, 1 },
|
|
{ "DLDnPCIeCRstMode", 2, 1 },
|
|
{ "DLDnPCIePreCRstMode", 1, 1 },
|
|
{ "LinkDnRstEn", 0, 1 },
|
|
{ "PCIE_DMA_CTRL", 0x3018, 0 },
|
|
{ "LittleEndian", 7, 1 },
|
|
{ "PCIE_DMA_CFG", 0x301c, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 9 },
|
|
{ "MaxReqCnt", 8, 8 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x3020, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 12 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_CFG", 0x3024, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 9 },
|
|
{ "MaxReqCnt", 8, 8 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x3028, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 12 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_CFG", 0x302c, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 9 },
|
|
{ "MaxReqCnt", 8, 8 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x3030, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 12 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_CFG", 0x3034, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 9 },
|
|
{ "MaxReqCnt", 8, 8 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x3038, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 12 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 11 },
|
|
{ "PCIE_CMD_CTRL", 0x303c, 0 },
|
|
{ "LittleEndian", 7, 1 },
|
|
{ "PCIE_CMD_CFG", 0x3040, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 4 },
|
|
{ "MaxReqCnt", 8, 5 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_CMD_STAT", 0x3044, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 7 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 8 },
|
|
{ "PCIE_CMD_CFG", 0x3048, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 4 },
|
|
{ "MaxReqCnt", 8, 5 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_CMD_STAT", 0x304c, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 7 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 8 },
|
|
{ "PCIE_HMA_CTRL", 0x3050, 0 },
|
|
{ "IPLTSSM", 12, 4 },
|
|
{ "IPConfigDown", 8, 3 },
|
|
{ "LittleEndian", 7, 1 },
|
|
{ "PCIE_HMA_CFG", 0x3054, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxRdReqSize", 25, 3 },
|
|
{ "MaxRspCnt", 16, 5 },
|
|
{ "MaxReqCnt", 8, 5 },
|
|
{ "MaxTag", 0, 7 },
|
|
{ "PCIE_HMA_STAT", 0x3058, 0 },
|
|
{ "StateReq", 28, 4 },
|
|
{ "RspCnt", 16, 8 },
|
|
{ "StateAReq", 13, 3 },
|
|
{ "TagFree", 12, 1 },
|
|
{ "ReqCnt", 0, 8 },
|
|
{ "PCIE_PIO_FIFO_CFG", 0x305c, 0 },
|
|
{ "CplConfig", 16, 16 },
|
|
{ "PIOStopEn", 12, 1 },
|
|
{ "IPLaneSwap", 11, 1 },
|
|
{ "ForceStrictTS1", 10, 1 },
|
|
{ "ForceProgressCnt", 0, 10 },
|
|
{ "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
|
|
{ "Enable", 30, 1 },
|
|
{ "AI", 29, 1 },
|
|
{ "LocalCfg", 28, 1 },
|
|
{ "Bus", 20, 8 },
|
|
{ "Device", 15, 5 },
|
|
{ "Function", 12, 3 },
|
|
{ "ExtRegister", 8, 4 },
|
|
{ "Register", 0, 8 },
|
|
{ "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 },
|
|
{ "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 },
|
|
{ "PCIEOfst", 6, 26 },
|
|
{ "BIR", 4, 2 },
|
|
{ "Window", 0, 2 },
|
|
{ "PCIE_MAILBOX_OFFSET", 0x30ac, 0 },
|
|
{ "PCIE_MA_CTRL", 0x30b0, 0 },
|
|
{ "TagFree", 29, 1 },
|
|
{ "MaxRspCnt", 24, 5 },
|
|
{ "MaxReqCnt", 16, 5 },
|
|
{ "LittleEndian", 15, 1 },
|
|
{ "MaxPyldSize", 12, 3 },
|
|
{ "MaxRdReqSize", 8, 3 },
|
|
{ "MaxTag", 0, 5 },
|
|
{ "PCIE_MA_SYNC", 0x30b4, 0 },
|
|
{ "PCIE_FW", 0x30b8, 0 },
|
|
{ "PCIE_FW_PF", 0x30bc, 0 },
|
|
{ "PCIE_FW_PF", 0x30c0, 0 },
|
|
{ "PCIE_FW_PF", 0x30c4, 0 },
|
|
{ "PCIE_FW_PF", 0x30c8, 0 },
|
|
{ "PCIE_FW_PF", 0x30cc, 0 },
|
|
{ "PCIE_FW_PF", 0x30d0, 0 },
|
|
{ "PCIE_FW_PF", 0x30d4, 0 },
|
|
{ "PCIE_FW_PF", 0x30d8, 0 },
|
|
{ "PCIE_PIO_PAUSE", 0x30dc, 0 },
|
|
{ "PIOPauseDone", 31, 1 },
|
|
{ "PauseTime", 4, 24 },
|
|
{ "PIOPause", 0, 1 },
|
|
{ "PCIE_SYS_CFG_READY", 0x30e0, 0 },
|
|
{ "PCIE_STATIC_CFG1", 0x30e4, 0 },
|
|
{ "LINKDOWN_RESET_EN", 26, 1 },
|
|
{ "IN_WR_DISCONTIG", 25, 1 },
|
|
{ "IN_RD_CPLSIZE", 22, 3 },
|
|
{ "IN_RD_BUFMODE", 20, 2 },
|
|
{ "GBIF_NPTRANS_TOT", 18, 2 },
|
|
{ "IN_PDAT_TOT", 15, 3 },
|
|
{ "PCIE_NPTRANS_TOT", 12, 3 },
|
|
{ "OUT_PDAT_TOT", 9, 3 },
|
|
{ "GBIF_MAX_WRSIZE", 6, 3 },
|
|
{ "GBIF_MAX_RDSIZE", 3, 3 },
|
|
{ "PCIE_MAX_RDSIZE", 0, 3 },
|
|
{ "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "AI", 30, 1 },
|
|
{ "Pointer", 8, 16 },
|
|
{ "Select", 0, 4 },
|
|
{ "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3100, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3104, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3108, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x310c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3110, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3114, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3118, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x311c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3120, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3124, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3128, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x312c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3130, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3134, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3138, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x313c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3140, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3144, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3148, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x314c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3150, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3154, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3158, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x315c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3160, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3164, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3168, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x316c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3170, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3174, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3178, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x317c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3180, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3184, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3188, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x318c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3190, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3194, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3198, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x319c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x31f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x31fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3200, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3204, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3208, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x320c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3210, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3214, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3218, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x321c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3220, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3224, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3228, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x322c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3230, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3234, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3238, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x323c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3240, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3244, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3248, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x324c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3250, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3254, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3258, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x325c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3260, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3264, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3268, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x326c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3270, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3274, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3278, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x327c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3280, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3284, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3288, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x328c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3290, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3294, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3298, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x329c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x32f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x32fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3300, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3304, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3308, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x330c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3310, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3314, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3318, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x331c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3320, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3324, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3328, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x332c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3330, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3334, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3338, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x333c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3340, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3344, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3348, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x334c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3350, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3354, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3358, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x335c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3360, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3364, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3368, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x336c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3370, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3374, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3378, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x337c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3380, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3384, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3388, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x338c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3390, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3394, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3398, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x339c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x33f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x33fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3400, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3404, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3408, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x340c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3410, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3414, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3418, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x341c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3420, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3424, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3428, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x342c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3430, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3434, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3438, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x343c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3440, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3444, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3448, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x344c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3450, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3454, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3458, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x345c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3460, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3464, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3468, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x346c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3470, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3474, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3478, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x347c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3480, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3484, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3488, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x348c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3490, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3494, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3498, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x349c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x34f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x34fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3500, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3504, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3508, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x350c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3510, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3514, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3518, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x351c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3520, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3524, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3528, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x352c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3530, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3534, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3538, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x353c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3540, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3544, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3548, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x354c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3550, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3554, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3558, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x355c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3560, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3564, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3568, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x356c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3570, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3574, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3578, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x357c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3580, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3584, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3588, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x358c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3590, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3594, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3598, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x359c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x35f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x35fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3600, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3604, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3608, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x360c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3610, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3614, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3618, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x361c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3620, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3624, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3628, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x362c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3630, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3634, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3638, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x363c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3640, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3644, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3648, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x364c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3650, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3654, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3658, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x365c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3660, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3664, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3668, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x366c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3670, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3674, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3678, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x367c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3680, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3684, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3688, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x368c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3690, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3694, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3698, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x369c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x36f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x36fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3700, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3704, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3708, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x370c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3710, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3714, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3718, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x371c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3720, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3724, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3728, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x372c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3730, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3734, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3738, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x373c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3740, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3744, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3748, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x374c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3750, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3754, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3758, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x375c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3760, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3764, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3768, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x376c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3770, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3774, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3778, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x377c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3780, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3784, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3788, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x378c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3790, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3794, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3798, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x379c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x37f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x37fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3800, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3804, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3808, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x380c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3810, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3814, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3818, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x381c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3820, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3824, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3828, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x382c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3830, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3834, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3838, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x383c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3840, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3844, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3848, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x384c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3850, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3854, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3858, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x385c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3860, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3864, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3868, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x386c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3870, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3874, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3878, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x387c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3880, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3884, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3888, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x388c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3890, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x3894, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x3898, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x389c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38a0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38a8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38b0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38b8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38c0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38c8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38d0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38d8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38e0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38e8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38f0, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FUNC_INT_CFG", 0x38f8, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_FUNC_CTL_STAT", 0x38fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PndTxns", 8, 10 },
|
|
{ "VFVld", 3, 1 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_FID", 0x3900, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3904, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3908, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x390c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3910, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3914, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3918, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x391c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3920, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3924, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3928, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x392c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3930, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3934, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3938, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x393c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3940, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3944, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3948, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x394c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3950, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3954, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3958, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x395c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3960, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3964, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3968, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x396c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3970, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3974, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3978, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x397c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3980, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3984, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3988, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x398c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3990, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3994, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3998, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x399c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x39fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3a9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3aa0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3aa4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3aa8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3aac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ab0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ab4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ab8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3abc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ac0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ac4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ac8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3acc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ad0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ad4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ad8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3adc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ae0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ae4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ae8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3aec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3af0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3af4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3af8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3afc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3b9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ba0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ba4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ba8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bcc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bdc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3be0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3be4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3be8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bf0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bf4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bf8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3bfc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3c9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ca0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ca4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ca8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ccc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cdc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ce0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ce4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ce8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cf0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cf4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cf8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3cfc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3d9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3da0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3da4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3da8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3db0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3db4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3db8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dcc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ddc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3de0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3de4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3de8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3df0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3df4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3df8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3dfc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3e9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ea0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ea4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ea8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3eac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3eb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3eb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3eb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ebc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ec0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ec4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ec8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ecc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ed0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ed4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ed8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3edc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ee0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ee4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ee8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3eec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ef0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ef4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ef8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3efc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3f9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fa0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fa4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fa8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fcc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fdc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fe0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fe4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fe8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3fec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ff0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ff4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ff8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x3ffc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4000, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4004, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4008, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x400c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4010, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4014, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4018, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x401c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4020, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4024, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4028, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x402c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4030, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4034, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4038, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x403c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4040, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4044, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4048, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x404c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4050, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4054, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4058, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x405c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4060, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4064, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4068, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x406c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4070, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4074, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4078, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x407c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4080, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4084, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4088, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x408c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4090, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4094, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4098, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x409c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x40fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4100, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4104, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4108, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x410c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4110, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4114, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4118, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x411c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4120, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4124, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4128, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x412c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4130, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4134, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4138, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x413c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4140, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4144, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4148, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x414c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4150, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4154, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4158, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x415c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4160, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4164, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4168, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x416c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4170, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4174, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4178, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x417c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4180, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4184, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4188, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x418c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4190, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4194, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4198, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x419c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x41fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4200, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4204, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4208, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x420c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4210, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4214, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4218, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x421c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4220, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4224, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4228, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x422c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4230, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4234, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4238, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x423c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4240, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4244, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4248, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x424c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4250, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4254, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4258, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x425c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4260, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4264, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4268, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x426c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4270, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4274, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4278, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x427c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4280, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4284, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4288, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x428c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4290, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4294, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4298, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x429c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x42fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4300, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4304, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4308, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x430c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4310, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4314, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4318, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x431c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4320, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4324, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4328, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x432c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4330, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4334, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4338, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x433c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4340, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4344, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4348, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x434c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4350, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4354, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4358, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x435c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4360, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4364, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4368, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x436c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4370, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4374, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4378, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x437c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4380, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4384, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4388, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x438c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4390, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4394, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4398, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x439c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x43fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4400, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4404, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4408, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x440c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4410, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4414, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4418, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x441c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4420, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4424, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4428, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x442c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4430, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4434, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4438, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x443c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4440, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4444, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4448, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x444c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4450, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4454, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4458, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x445c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4460, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4464, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4468, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x446c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4470, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4474, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4478, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x447c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4480, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4484, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4488, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x448c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4490, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4494, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4498, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x449c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x44fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4500, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4504, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4508, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x450c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4510, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4514, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4518, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x451c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4520, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4524, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4528, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x452c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4530, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4534, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4538, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x453c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4540, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4544, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4548, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x454c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4550, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4554, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4558, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x455c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4560, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4564, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4568, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x456c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4570, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4574, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4578, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x457c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4580, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4584, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4588, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x458c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4590, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4594, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4598, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x459c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x45fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4600, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4604, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4608, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x460c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4610, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4614, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4618, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x461c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4620, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4624, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4628, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x462c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4630, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4634, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4638, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x463c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4640, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4644, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4648, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x464c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4650, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4654, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4658, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x465c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4660, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4664, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4668, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x466c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4670, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4674, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4678, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x467c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4680, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4684, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4688, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x468c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4690, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4694, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4698, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x469c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x46fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4700, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4704, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4708, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x470c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4710, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4714, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4718, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x471c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4720, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4724, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4728, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x472c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4730, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4734, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4738, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x473c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4740, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4744, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4748, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x474c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4750, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4754, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4758, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x475c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4760, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4764, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4768, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x476c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4770, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4774, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4778, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x477c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4780, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4784, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4788, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x478c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4790, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4794, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4798, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x479c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x47fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4800, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4804, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4808, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x480c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4810, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4814, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4818, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x481c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4820, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4824, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4828, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x482c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4830, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4834, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4838, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x483c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4840, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4844, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4848, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x484c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4850, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4854, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4858, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x485c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4860, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4864, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4868, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x486c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4870, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4874, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4878, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x487c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4880, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4884, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4888, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x488c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4890, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4894, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4898, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x489c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x48fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4900, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4904, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4908, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x490c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4910, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4914, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4918, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x491c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4920, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4924, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4928, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x492c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4930, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4934, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4938, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x493c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4940, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4944, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4948, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x494c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4950, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4954, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4958, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x495c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4960, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4964, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4968, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x496c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4970, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4974, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4978, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x497c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4980, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4984, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4988, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x498c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4990, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4994, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4998, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x499c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x49fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4a9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4aa0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4aa4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4aa8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4aac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ab0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ab4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ab8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4abc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ac0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ac4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ac8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4acc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ad0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ad4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ad8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4adc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ae0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ae4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ae8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4aec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4af0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4af4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4af8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4afc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4b9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ba0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ba4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ba8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bcc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bdc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4be0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4be4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4be8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bf0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bf4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bf8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4bfc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4c9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ca0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ca4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ca8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ccc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cdc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ce0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ce4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ce8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cf0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cf4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cf8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4cfc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4d9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4da0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4da4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4da8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4db0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4db4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4db8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dcc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ddc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4de0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4de4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4de8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4df0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4df4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4df8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4dfc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4e9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ea0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ea4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ea8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4eac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4eb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4eb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4eb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ebc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ec0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ec4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ec8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ecc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ed0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ed4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ed8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4edc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ee0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ee4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ee8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4eec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ef0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ef4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ef8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4efc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f00, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f04, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f08, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f0c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f10, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f14, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f18, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f1c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f20, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f24, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f28, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f2c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f30, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f34, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f38, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f3c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f40, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f44, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f48, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f4c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f50, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f54, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f58, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f5c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f60, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f64, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f68, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f6c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f70, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f74, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f78, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f7c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f80, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f84, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f88, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f8c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f90, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f94, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f98, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4f9c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fa0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fa4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fa8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fb0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fb4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fb8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fbc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fc0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fc4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fc8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fcc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fd0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fd4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fd8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fdc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fe0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fe4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fe8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4fec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ff0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ff4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ff8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x4ffc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5000, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5004, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5008, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x500c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5010, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5014, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5018, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x501c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5020, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5024, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5028, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x502c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5030, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5034, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5038, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x503c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5040, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5044, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5048, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x504c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5050, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5054, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5058, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x505c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5060, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5064, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5068, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x506c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5070, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5074, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5078, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x507c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5080, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5084, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5088, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x508c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5090, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5094, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5098, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x509c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x50fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5100, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5104, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5108, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x510c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5110, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5114, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5118, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x511c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5120, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5124, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5128, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x512c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5130, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5134, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5138, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x513c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5140, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5144, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5148, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x514c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5150, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5154, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5158, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x515c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5160, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5164, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5168, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x516c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5170, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5174, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5178, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x517c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5180, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5184, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5188, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x518c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5190, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5194, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5198, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x519c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x51fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5200, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5204, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5208, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x520c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5210, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5214, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5218, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x521c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5220, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5224, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5228, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x522c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5230, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5234, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5238, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x523c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5240, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5244, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5248, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x524c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5250, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5254, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5258, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x525c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5260, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5264, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5268, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x526c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5270, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5274, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5278, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x527c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5280, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5284, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5288, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x528c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5290, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5294, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5298, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x529c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x52fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5300, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5304, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5308, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x530c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5310, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5314, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5318, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x531c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5320, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5324, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5328, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x532c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5330, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5334, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5338, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x533c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5340, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5344, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5348, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x534c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5350, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5354, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5358, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x535c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5360, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5364, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5368, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x536c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5370, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5374, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5378, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x537c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5380, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5384, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5388, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x538c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5390, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5394, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5398, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x539c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x53fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5400, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5404, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5408, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x540c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5410, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5414, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5418, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x541c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5420, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5424, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5428, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x542c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5430, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5434, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5438, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x543c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5440, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5444, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5448, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x544c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5450, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5454, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5458, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x545c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5460, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5464, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5468, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x546c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5470, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5474, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5478, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x547c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5480, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5484, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5488, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x548c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5490, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5494, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5498, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x549c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x54fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5500, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5504, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5508, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x550c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5510, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5514, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5518, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x551c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5520, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5524, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5528, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x552c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5530, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5534, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5538, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x553c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5540, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5544, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5548, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x554c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5550, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5554, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5558, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x555c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5560, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5564, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5568, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x556c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5570, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5574, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5578, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x557c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5580, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5584, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5588, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x558c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5590, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5594, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5598, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x559c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x55fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5600, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5604, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5608, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x560c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5610, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5614, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5618, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x561c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5620, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5624, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5628, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x562c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5630, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5634, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5638, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x563c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5640, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5644, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5648, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x564c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5650, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5654, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5658, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x565c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5660, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5664, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5668, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x566c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5670, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5674, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5678, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x567c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5680, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5684, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5688, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x568c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5690, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5694, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5698, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x569c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x56fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5700, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5704, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5708, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x570c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5710, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5714, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5718, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x571c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5720, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5724, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5728, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x572c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5730, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5734, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5738, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x573c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5740, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5744, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5748, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x574c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5750, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5754, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5758, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x575c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5760, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5764, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5768, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x576c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5770, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5774, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5778, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x577c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5780, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5784, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5788, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x578c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5790, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5794, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5798, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x579c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x57fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5800, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5804, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5808, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x580c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5810, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5814, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5818, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x581c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5820, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5824, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5828, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x582c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5830, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5834, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5838, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x583c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5840, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5844, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5848, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x584c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5850, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5854, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5858, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x585c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5860, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5864, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5868, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x586c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5870, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5874, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5878, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x587c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5880, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5884, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5888, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x588c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5890, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5894, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x5898, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x589c, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58a0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58a4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58a8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58ac, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58b0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58b4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58b8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58bc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58c0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58c4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58c8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58cc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58d0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58d4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58d8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58dc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58e0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58e4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58e8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58ec, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58f0, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58f4, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58f8, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_FID", 0x58fc, 0 },
|
|
{ "Pad", 11, 1 },
|
|
{ "TC", 8, 3 },
|
|
{ "Function", 0, 8 },
|
|
{ "PCIE_REVISION", 0x5a00, 0 },
|
|
{ "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
|
|
{ "PDEBUGSelH", 16, 6 },
|
|
{ "PDEBUGSelL", 0, 6 },
|
|
{ "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
|
|
{ "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
|
|
{ "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
|
|
{ "CDEBUGSelH", 16, 8 },
|
|
{ "CDEBUGSelL", 0, 8 },
|
|
{ "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
|
|
{ "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
|
|
{ "PCIE_DMAW_SOP_CNT", 0x5a1c, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_DMAW_EOP_CNT", 0x5a20, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_DMAR_REQ_CNT", 0x5a24, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_DMAR_RSP_SOP_CNT", 0x5a28, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_DMAR_RSP_EOP_CNT", 0x5a2c, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_DMAR_RSP_ERR_CNT", 0x5a30, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_DMAI_CNT", 0x5a34, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_CMDW_CNT", 0x5a38, 0 },
|
|
{ "CH1_EOP", 24, 8 },
|
|
{ "CH1_SOP", 16, 8 },
|
|
{ "CH0_EOP", 8, 8 },
|
|
{ "CH0_SOP", 0, 8 },
|
|
{ "PCIE_CMDR_REQ_CNT", 0x5a3c, 0 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_CMDR_RSP_CNT", 0x5a40, 0 },
|
|
{ "CH1_EOP", 24, 8 },
|
|
{ "CH1_SOP", 16, 8 },
|
|
{ "CH0_EOP", 8, 8 },
|
|
{ "CH0_SOP", 0, 8 },
|
|
{ "PCIE_CMDR_RSP_ERR_CNT", 0x5a44, 0 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "PCIE_HMA_REQ_CNT", 0x5a48, 0 },
|
|
{ "CH0_READ", 16, 8 },
|
|
{ "CH0_WEOP", 8, 8 },
|
|
{ "CH0_WSOP", 0, 8 },
|
|
{ "PCIE_HMA_RSP_CNT", 0x5a4c, 0 },
|
|
{ "CH0_EOP", 8, 8 },
|
|
{ "CH0_SOP", 0, 8 },
|
|
{ "PCIE_DMA10_RSP_FREE", 0x5a50, 0 },
|
|
{ "CH1", 16, 12 },
|
|
{ "CH0", 0, 12 },
|
|
{ "PCIE_DMA32_RSP_FREE", 0x5a54, 0 },
|
|
{ "CH3", 16, 12 },
|
|
{ "CH2", 0, 12 },
|
|
{ "PCIE_CMD_RSP_FREE", 0x5a58, 0 },
|
|
{ "CH1", 16, 7 },
|
|
{ "CH0", 0, 7 },
|
|
{ "PCIE_HMA_RSP_FREE", 0x5a5c, 0 },
|
|
{ "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
|
|
{ "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
|
|
{ "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
|
|
{ "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
|
|
{ "PCIE_BUS_MST_STAT_4", 0x5a70, 0 },
|
|
{ "PCIE_BUS_MST_STAT_5", 0x5a74, 0 },
|
|
{ "PCIE_BUS_MST_STAT_6", 0x5a78, 0 },
|
|
{ "PCIE_BUS_MST_STAT_7", 0x5a7c, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_4", 0x5a90, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_5", 0x5a94, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_6", 0x5a98, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_7", 0x5a9c, 0 },
|
|
{ "PCIE_MSI_EN_0", 0x5aa0, 0 },
|
|
{ "PCIE_MSI_EN_1", 0x5aa4, 0 },
|
|
{ "PCIE_MSI_EN_2", 0x5aa8, 0 },
|
|
{ "PCIE_MSI_EN_3", 0x5aac, 0 },
|
|
{ "PCIE_MSI_EN_4", 0x5ab0, 0 },
|
|
{ "PCIE_MSI_EN_5", 0x5ab4, 0 },
|
|
{ "PCIE_MSI_EN_6", 0x5ab8, 0 },
|
|
{ "PCIE_MSI_EN_7", 0x5abc, 0 },
|
|
{ "PCIE_MSIX_EN_0", 0x5ac0, 0 },
|
|
{ "PCIE_MSIX_EN_1", 0x5ac4, 0 },
|
|
{ "PCIE_MSIX_EN_2", 0x5ac8, 0 },
|
|
{ "PCIE_MSIX_EN_3", 0x5acc, 0 },
|
|
{ "PCIE_MSIX_EN_4", 0x5ad0, 0 },
|
|
{ "PCIE_MSIX_EN_5", 0x5ad4, 0 },
|
|
{ "PCIE_MSIX_EN_6", 0x5ad8, 0 },
|
|
{ "PCIE_MSIX_EN_7", 0x5adc, 0 },
|
|
{ "PCIE_DMA_BUF_CTL", 0x5ae0, 0 },
|
|
{ "BufRdCnt", 18, 14 },
|
|
{ "BufWrCnt", 9, 9 },
|
|
{ "MaxBufWrReq", 0, 9 },
|
|
{ "PCIE_DMA_BUF_CTL", 0x5ae8, 0 },
|
|
{ "BufRdCnt", 18, 14 },
|
|
{ "BufWrCnt", 9, 9 },
|
|
{ "MaxBufWrReq", 0, 9 },
|
|
{ "PCIE_DMA_BUF_CTL", 0x5af0, 0 },
|
|
{ "BufRdCnt", 18, 14 },
|
|
{ "BufWrCnt", 9, 9 },
|
|
{ "MaxBufWrReq", 0, 9 },
|
|
{ "PCIE_DMA_BUF_CTL", 0x5af8, 0 },
|
|
{ "BufRdCnt", 18, 14 },
|
|
{ "BufWrCnt", 9, 9 },
|
|
{ "MaxBufWrReq", 0, 9 },
|
|
{ "PCIE_CORE_UTL_SYSTEM_BUS_CONTROL", 0x5900, 0 },
|
|
{ "SMTD", 27, 1 },
|
|
{ "SSTD", 26, 1 },
|
|
{ "SWD0", 23, 1 },
|
|
{ "SWD1", 22, 1 },
|
|
{ "SWD2", 21, 1 },
|
|
{ "SWD3", 20, 1 },
|
|
{ "SWD4", 19, 1 },
|
|
{ "SWD5", 18, 1 },
|
|
{ "SWD6", 17, 1 },
|
|
{ "SWD7", 16, 1 },
|
|
{ "SWD8", 15, 1 },
|
|
{ "SRD0", 13, 1 },
|
|
{ "SRD1", 12, 1 },
|
|
{ "SRD2", 11, 1 },
|
|
{ "SRD3", 10, 1 },
|
|
{ "SRD4", 9, 1 },
|
|
{ "SRD5", 8, 1 },
|
|
{ "SRD6", 7, 1 },
|
|
{ "SRD7", 6, 1 },
|
|
{ "SRD8", 5, 1 },
|
|
{ "CRRE", 3, 1 },
|
|
{ "CRMC", 0, 3 },
|
|
{ "PCIE_CORE_UTL_STATUS", 0x5904, 0 },
|
|
{ "USBP", 31, 1 },
|
|
{ "UPEP", 30, 1 },
|
|
{ "RCEP", 29, 1 },
|
|
{ "EPEP", 28, 1 },
|
|
{ "USBS", 27, 1 },
|
|
{ "UPES", 26, 1 },
|
|
{ "RCES", 25, 1 },
|
|
{ "EPES", 24, 1 },
|
|
{ "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 0x5908, 0 },
|
|
{ "RNPP", 31, 1 },
|
|
{ "RPCP", 29, 1 },
|
|
{ "RCIP", 27, 1 },
|
|
{ "RCCP", 26, 1 },
|
|
{ "RFTP", 23, 1 },
|
|
{ "PTRP", 20, 1 },
|
|
{ "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY", 0x590c, 0 },
|
|
{ "RNPS", 31, 1 },
|
|
{ "RPCS", 29, 1 },
|
|
{ "RCIS", 27, 1 },
|
|
{ "RCCS", 26, 1 },
|
|
{ "RFTS", 23, 1 },
|
|
{ "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE", 0x5910, 0 },
|
|
{ "RNPI", 31, 1 },
|
|
{ "RPCI", 29, 1 },
|
|
{ "RCII", 27, 1 },
|
|
{ "RCCI", 26, 1 },
|
|
{ "RFTI", 23, 1 },
|
|
{ "PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION", 0x5920, 0 },
|
|
{ "SBRS", 28, 3 },
|
|
{ "OTWS", 20, 3 },
|
|
{ "PCIE_CORE_REVISION_ID", 0x5924, 0 },
|
|
{ "RVID", 20, 12 },
|
|
{ "BRVN", 12, 8 },
|
|
{ "PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION", 0x5960, 0 },
|
|
{ "OP0H", 24, 4 },
|
|
{ "OP1H", 16, 4 },
|
|
{ "OP2H", 8, 4 },
|
|
{ "OP3H", 0, 4 },
|
|
{ "PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION", 0x5968, 0 },
|
|
{ "OP0D", 24, 7 },
|
|
{ "OP1D", 16, 7 },
|
|
{ "OP2D", 8, 7 },
|
|
{ "OP3D", 0, 7 },
|
|
{ "PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION", 0x5970, 0 },
|
|
{ "IP0H", 24, 6 },
|
|
{ "IP1H", 16, 6 },
|
|
{ "IP2H", 8, 6 },
|
|
{ "IP3H", 0, 6 },
|
|
{ "PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION", 0x5978, 0 },
|
|
{ "IP0D", 24, 8 },
|
|
{ "IP1D", 16, 8 },
|
|
{ "IP2D", 8, 8 },
|
|
{ "IP3D", 0, 8 },
|
|
{ "PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION", 0x5980, 0 },
|
|
{ "ON0H", 24, 4 },
|
|
{ "ON1H", 16, 4 },
|
|
{ "ON2H", 8, 4 },
|
|
{ "ON3H", 0, 4 },
|
|
{ "PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION", 0x5988, 0 },
|
|
{ "IN0H", 24, 6 },
|
|
{ "IN1H", 16, 6 },
|
|
{ "IN2H", 8, 6 },
|
|
{ "IN3H", 0, 6 },
|
|
{ "PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION", 0x5990, 0 },
|
|
{ "OC0T", 24, 8 },
|
|
{ "OC1T", 16, 8 },
|
|
{ "OC2T", 8, 8 },
|
|
{ "OC3T", 0, 8 },
|
|
{ "PCIE_CORE_GBIF_READ_TAGS_ALLOCATION", 0x5998, 0 },
|
|
{ "IC0T", 24, 6 },
|
|
{ "IC1T", 16, 6 },
|
|
{ "IC2T", 8, 6 },
|
|
{ "IC3T", 0, 6 },
|
|
{ "PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL", 0x59a0, 0 },
|
|
{ "VRB0", 31, 1 },
|
|
{ "VRB1", 30, 1 },
|
|
{ "VRB2", 29, 1 },
|
|
{ "VRB3", 28, 1 },
|
|
{ "PSFE", 26, 1 },
|
|
{ "RVDE", 25, 1 },
|
|
{ "TXE0", 23, 1 },
|
|
{ "TXE1", 22, 1 },
|
|
{ "TXE2", 21, 1 },
|
|
{ "TXE3", 20, 1 },
|
|
{ "RPAM", 13, 1 },
|
|
{ "RTOS", 4, 4 },
|
|
{ "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 0x59a4, 0 },
|
|
{ "TPCP", 30, 1 },
|
|
{ "TNPP", 29, 1 },
|
|
{ "TFTP", 28, 1 },
|
|
{ "TCAP", 27, 1 },
|
|
{ "TCIP", 26, 1 },
|
|
{ "RCAP", 25, 1 },
|
|
{ "PLUP", 23, 1 },
|
|
{ "PLDN", 22, 1 },
|
|
{ "OTDD", 21, 1 },
|
|
{ "GTRP", 20, 1 },
|
|
{ "RDPE", 18, 1 },
|
|
{ "TDCE", 17, 1 },
|
|
{ "TDUE", 16, 1 },
|
|
{ "PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY", 0x59a8, 0 },
|
|
{ "TPCS", 30, 1 },
|
|
{ "TNPS", 29, 1 },
|
|
{ "TFTS", 28, 1 },
|
|
{ "TCAS", 27, 1 },
|
|
{ "TCIS", 26, 1 },
|
|
{ "RCAS", 25, 1 },
|
|
{ "PLUS", 23, 1 },
|
|
{ "PLDS", 22, 1 },
|
|
{ "OTDS", 21, 1 },
|
|
{ "RDPS", 18, 1 },
|
|
{ "TDCS", 17, 1 },
|
|
{ "TDUS", 16, 1 },
|
|
{ "PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE", 0x59ac, 0 },
|
|
{ "TPCI", 30, 1 },
|
|
{ "TNPI", 29, 1 },
|
|
{ "TFTI", 28, 1 },
|
|
{ "TCAI", 27, 1 },
|
|
{ "TCII", 26, 1 },
|
|
{ "RCAI", 25, 1 },
|
|
{ "PLUI", 23, 1 },
|
|
{ "PLDI", 22, 1 },
|
|
{ "OTDI", 21, 1 },
|
|
{ "RDPS", 18, 1 },
|
|
{ "TDCS", 17, 1 },
|
|
{ "TDUS", 16, 1 },
|
|
{ "PCIE_CORE_ROOT_COMPLEX_STATUS", 0x59b0, 0 },
|
|
{ "RLCE", 31, 1 },
|
|
{ "RLNE", 30, 1 },
|
|
{ "RLFE", 29, 1 },
|
|
{ "RCPE", 25, 1 },
|
|
{ "RCTO", 24, 1 },
|
|
{ "PINA", 23, 1 },
|
|
{ "PINB", 22, 1 },
|
|
{ "PINC", 21, 1 },
|
|
{ "PIND", 20, 1 },
|
|
{ "ALER", 19, 1 },
|
|
{ "CRSE", 18, 1 },
|
|
{ "PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY", 0x59b4, 0 },
|
|
{ "RLCS", 31, 1 },
|
|
{ "RLNS", 30, 1 },
|
|
{ "RLFS", 29, 1 },
|
|
{ "RCPS", 25, 1 },
|
|
{ "RCTS", 24, 1 },
|
|
{ "PAAS", 23, 1 },
|
|
{ "PABS", 22, 1 },
|
|
{ "PACS", 21, 1 },
|
|
{ "PADS", 20, 1 },
|
|
{ "ALES", 19, 1 },
|
|
{ "CRSS", 18, 1 },
|
|
{ "PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE", 0x59b8, 0 },
|
|
{ "RLCI", 31, 1 },
|
|
{ "RLNI", 30, 1 },
|
|
{ "RLFI", 29, 1 },
|
|
{ "RCPI", 25, 1 },
|
|
{ "RCTI", 24, 1 },
|
|
{ "PAAI", 23, 1 },
|
|
{ "PABI", 22, 1 },
|
|
{ "PACI", 21, 1 },
|
|
{ "PADI", 20, 1 },
|
|
{ "ALEI", 19, 1 },
|
|
{ "CRSI", 18, 1 },
|
|
{ "PCIE_CORE_ENDPOINT_STATUS", 0x59bc, 0 },
|
|
{ "PTOM", 31, 1 },
|
|
{ "ALEA", 29, 1 },
|
|
{ "PMC0", 23, 1 },
|
|
{ "PMC1", 22, 1 },
|
|
{ "PMC2", 21, 1 },
|
|
{ "PMC3", 20, 1 },
|
|
{ "PMC4", 19, 1 },
|
|
{ "PMC5", 18, 1 },
|
|
{ "PMC6", 17, 1 },
|
|
{ "PMC7", 16, 1 },
|
|
{ "PCIE_CORE_ENDPOINT_ERROR_SEVERITY", 0x59c0, 0 },
|
|
{ "PTOS", 31, 1 },
|
|
{ "AENS", 29, 1 },
|
|
{ "PC0S", 23, 1 },
|
|
{ "PC1S", 22, 1 },
|
|
{ "PC2S", 21, 1 },
|
|
{ "PC3S", 20, 1 },
|
|
{ "PC4S", 19, 1 },
|
|
{ "PC5S", 18, 1 },
|
|
{ "PC6S", 17, 1 },
|
|
{ "PC7S", 16, 1 },
|
|
{ "PME0", 15, 1 },
|
|
{ "PME1", 14, 1 },
|
|
{ "PME2", 13, 1 },
|
|
{ "PME3", 12, 1 },
|
|
{ "PME4", 11, 1 },
|
|
{ "PME5", 10, 1 },
|
|
{ "PME6", 9, 1 },
|
|
{ "PME7", 8, 1 },
|
|
{ "PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE", 0x59c4, 0 },
|
|
{ "PTOI", 31, 1 },
|
|
{ "AENI", 29, 1 },
|
|
{ "PC0I", 23, 1 },
|
|
{ "PC1I", 22, 1 },
|
|
{ "PC2I", 21, 1 },
|
|
{ "PC3I", 20, 1 },
|
|
{ "PC4I", 19, 1 },
|
|
{ "PC5I", 18, 1 },
|
|
{ "PC6I", 17, 1 },
|
|
{ "PC7I", 16, 1 },
|
|
{ "PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1", 0x59c8, 0 },
|
|
{ "TOAK", 31, 1 },
|
|
{ "L1RS", 23, 1 },
|
|
{ "L23S", 22, 1 },
|
|
{ "AL1S", 21, 1 },
|
|
{ "ALET", 19, 1 },
|
|
{ "PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2", 0x59cc, 0 },
|
|
{ "CPM0", 30, 2 },
|
|
{ "CPM1", 28, 2 },
|
|
{ "CPM2", 26, 2 },
|
|
{ "CPM3", 24, 2 },
|
|
{ "CPM4", 22, 2 },
|
|
{ "CPM5", 20, 2 },
|
|
{ "CPM6", 18, 2 },
|
|
{ "CPM7", 16, 2 },
|
|
{ "OPM0", 14, 2 },
|
|
{ "OPM1", 12, 2 },
|
|
{ "OPM2", 10, 2 },
|
|
{ "OPM3", 8, 2 },
|
|
{ "OPM4", 6, 2 },
|
|
{ "OPM5", 4, 2 },
|
|
{ "OPM6", 2, 2 },
|
|
{ "OPM7", 0, 2 },
|
|
{ "PCIE_CORE_GENERAL_PURPOSE_CONTROL_1", 0x59d0, 0 },
|
|
{ "PCIE_CORE_GENERAL_PURPOSE_CONTROL_2", 0x59d4, 0 },
|
|
{ "PCIE_PF_CFG", 0x1e040, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e044, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1e048, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1e440, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e444, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1e448, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1e840, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e844, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1e848, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1ec40, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1ec44, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1ec48, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f040, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f044, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1f048, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f440, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f444, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1f448, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f840, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f844, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1f848, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1fc40, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AuxPwrPMEn", 15, 1 },
|
|
{ "NoSoftReset", 14, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "INTXType", 2, 2 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1fc44, 0 },
|
|
{ "PCIE_PF_GEN_MSG", 0x1fc48, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_dbg_regs[] = {
|
|
{ "DBG_DBG0_CFG", 0x6000, 0 },
|
|
{ "ModuleSelect", 12, 8 },
|
|
{ "RegSelect", 4, 8 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "DBG_DBG0_EN", 0x6004, 0 },
|
|
{ "PortEn_PONR", 16, 1 },
|
|
{ "PortEn_POND", 12, 1 },
|
|
{ "SDRHalfWord0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "DBG_DBG1_CFG", 0x6008, 0 },
|
|
{ "ModuleSelect", 12, 8 },
|
|
{ "RegSelect", 4, 8 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "DBG_DBG1_EN", 0x600c, 0 },
|
|
{ "PortEn_PONR", 16, 1 },
|
|
{ "PortEn_POND", 12, 1 },
|
|
{ "SDRHalfWord0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "DBG_GPIO_EN", 0x6010, 0 },
|
|
{ "GPIO15_OEn", 31, 1 },
|
|
{ "GPIO14_OEn", 30, 1 },
|
|
{ "GPIO13_OEn", 29, 1 },
|
|
{ "GPIO12_OEn", 28, 1 },
|
|
{ "GPIO11_OEn", 27, 1 },
|
|
{ "GPIO10_OEn", 26, 1 },
|
|
{ "GPIO9_OEn", 25, 1 },
|
|
{ "GPIO8_OEn", 24, 1 },
|
|
{ "GPIO7_OEn", 23, 1 },
|
|
{ "GPIO6_OEn", 22, 1 },
|
|
{ "GPIO5_OEn", 21, 1 },
|
|
{ "GPIO4_OEn", 20, 1 },
|
|
{ "GPIO3_OEn", 19, 1 },
|
|
{ "GPIO2_OEn", 18, 1 },
|
|
{ "GPIO1_OEn", 17, 1 },
|
|
{ "GPIO0_OEn", 16, 1 },
|
|
{ "GPIO15_Out_Val", 15, 1 },
|
|
{ "GPIO14_Out_Val", 14, 1 },
|
|
{ "GPIO13_Out_Val", 13, 1 },
|
|
{ "GPIO12_Out_Val", 12, 1 },
|
|
{ "GPIO11_Out_Val", 11, 1 },
|
|
{ "GPIO10_Out_Val", 10, 1 },
|
|
{ "GPIO9_Out_Val", 9, 1 },
|
|
{ "GPIO8_Out_Val", 8, 1 },
|
|
{ "GPIO7_Out_Val", 7, 1 },
|
|
{ "GPIO6_Out_Val", 6, 1 },
|
|
{ "GPIO5_Out_Val", 5, 1 },
|
|
{ "GPIO4_Out_Val", 4, 1 },
|
|
{ "GPIO3_Out_Val", 3, 1 },
|
|
{ "GPIO2_Out_Val", 2, 1 },
|
|
{ "GPIO1_Out_Val", 1, 1 },
|
|
{ "GPIO0_Out_Val", 0, 1 },
|
|
{ "DBG_GPIO_IN", 0x6014, 0 },
|
|
{ "GPIO15_CHG_DET", 31, 1 },
|
|
{ "GPIO14_CHG_DET", 30, 1 },
|
|
{ "GPIO13_CHG_DET", 29, 1 },
|
|
{ "GPIO12_CHG_DET", 28, 1 },
|
|
{ "GPIO11_CHG_DET", 27, 1 },
|
|
{ "GPIO10_CHG_DET", 26, 1 },
|
|
{ "GPIO9_CHG_DET", 25, 1 },
|
|
{ "GPIO8_CHG_DET", 24, 1 },
|
|
{ "GPIO7_CHG_DET", 23, 1 },
|
|
{ "GPIO6_CHG_DET", 22, 1 },
|
|
{ "GPIO5_CHG_DET", 21, 1 },
|
|
{ "GPIO4_CHG_DET", 20, 1 },
|
|
{ "GPIO3_CHG_DET", 19, 1 },
|
|
{ "GPIO2_CHG_DET", 18, 1 },
|
|
{ "GPIO1_CHG_DET", 17, 1 },
|
|
{ "GPIO0_CHG_DET", 16, 1 },
|
|
{ "GPIO15_IN", 15, 1 },
|
|
{ "GPIO14_IN", 14, 1 },
|
|
{ "GPIO13_IN", 13, 1 },
|
|
{ "GPIO12_IN", 12, 1 },
|
|
{ "GPIO11_IN", 11, 1 },
|
|
{ "GPIO10_IN", 10, 1 },
|
|
{ "GPIO9_IN", 9, 1 },
|
|
{ "GPIO8_IN", 8, 1 },
|
|
{ "GPIO7_IN", 7, 1 },
|
|
{ "GPIO6_IN", 6, 1 },
|
|
{ "GPIO5_IN", 5, 1 },
|
|
{ "GPIO4_IN", 4, 1 },
|
|
{ "GPIO3_IN", 3, 1 },
|
|
{ "GPIO2_IN", 2, 1 },
|
|
{ "GPIO1_IN", 1, 1 },
|
|
{ "GPIO0_IN", 0, 1 },
|
|
{ "DBG_INT_ENABLE", 0x6018, 0 },
|
|
{ "IBM_FDL_FAIL_int_enbl", 25, 1 },
|
|
{ "ARM_FAIL_int_enbl", 24, 1 },
|
|
{ "ARM_ERROR_OUT_int_enbl", 23, 1 },
|
|
{ "pll_lock_lost_int_enbl", 22, 1 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "PCIe_LOCK", 18, 1 },
|
|
{ "KX_LOCK", 17, 1 },
|
|
{ "KR_LOCK", 16, 1 },
|
|
{ "GPIO15", 15, 1 },
|
|
{ "GPIO14", 14, 1 },
|
|
{ "GPIO13", 13, 1 },
|
|
{ "GPIO12", 12, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "DBG_INT_CAUSE", 0x601c, 0 },
|
|
{ "IBM_FDL_FAIL_int_cause", 25, 1 },
|
|
{ "ARM_FAIL_int_cause", 24, 1 },
|
|
{ "ARM_ERROR_OUT_int_cause", 23, 1 },
|
|
{ "pll_lock_lost_int_cause", 22, 1 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "PCIe_LOCK", 18, 1 },
|
|
{ "KX_LOCK", 17, 1 },
|
|
{ "KR_LOCK", 16, 1 },
|
|
{ "GPIO15", 15, 1 },
|
|
{ "GPIO14", 14, 1 },
|
|
{ "GPIO13", 13, 1 },
|
|
{ "GPIO12", 12, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "DBG_DBG0_RST_VALUE", 0x6020, 0 },
|
|
{ "DBG_OVERWRSERCFG_EN", 0x6024, 0 },
|
|
{ "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
|
|
{ "PCIE_OCLK_En", 20, 1 },
|
|
{ "KX_OCLK_En", 16, 1 },
|
|
{ "U_OCLK_En", 12, 1 },
|
|
{ "KR_OCLK_En", 8, 1 },
|
|
{ "M_OCLK_En", 4, 1 },
|
|
{ "C_OCLK_En", 0, 1 },
|
|
{ "DBG_PLL_LOCK", 0x602c, 0 },
|
|
{ "P_LOCK", 20, 1 },
|
|
{ "KX_LOCK", 16, 1 },
|
|
{ "U_LOCK", 12, 1 },
|
|
{ "KR_LOCK", 8, 1 },
|
|
{ "M_LOCK", 4, 1 },
|
|
{ "C_LOCK", 0, 1 },
|
|
{ "DBG_GPIO_ACT_LOW", 0x6030, 0 },
|
|
{ "P_LOCK_ACT_LOW", 21, 1 },
|
|
{ "C_LOCK_ACT_LOW", 20, 1 },
|
|
{ "M_LOCK_ACT_LOW", 19, 1 },
|
|
{ "U_LOCK_ACT_LOW", 18, 1 },
|
|
{ "KR_LOCK_ACT_LOW", 17, 1 },
|
|
{ "KX_LOCK_ACT_LOW", 16, 1 },
|
|
{ "GPIO15_ACT_LOW", 15, 1 },
|
|
{ "GPIO14_ACT_LOW", 14, 1 },
|
|
{ "GPIO13_ACT_LOW", 13, 1 },
|
|
{ "GPIO12_ACT_LOW", 12, 1 },
|
|
{ "GPIO11_ACT_LOW", 11, 1 },
|
|
{ "GPIO10_ACT_LOW", 10, 1 },
|
|
{ "GPIO9_ACT_LOW", 9, 1 },
|
|
{ "GPIO8_ACT_LOW", 8, 1 },
|
|
{ "GPIO7_ACT_LOW", 7, 1 },
|
|
{ "GPIO6_ACT_LOW", 6, 1 },
|
|
{ "GPIO5_ACT_LOW", 5, 1 },
|
|
{ "GPIO4_ACT_LOW", 4, 1 },
|
|
{ "GPIO3_ACT_LOW", 3, 1 },
|
|
{ "GPIO2_ACT_LOW", 2, 1 },
|
|
{ "GPIO1_ACT_LOW", 1, 1 },
|
|
{ "GPIO0_ACT_LOW", 0, 1 },
|
|
{ "DBG_EFUSE_BYTE0_3", 0x6034, 0 },
|
|
{ "DBG_EFUSE_BYTE4_7", 0x6038, 0 },
|
|
{ "DBG_EFUSE_BYTE8_11", 0x603c, 0 },
|
|
{ "DBG_EFUSE_BYTE12_15", 0x6040, 0 },
|
|
{ "DBG_STATIC_U_PLL_CONF", 0x6044, 0 },
|
|
{ "STATIC_U_PLL_MULT", 23, 9 },
|
|
{ "STATIC_U_PLL_PREDIV", 18, 5 },
|
|
{ "STATIC_U_PLL_RANGEA", 14, 4 },
|
|
{ "STATIC_U_PLL_RANGEB", 10, 4 },
|
|
{ "STATIC_U_PLL_TUNE", 0, 10 },
|
|
{ "DBG_STATIC_C_PLL_CONF", 0x6048, 0 },
|
|
{ "STATIC_C_PLL_MULT", 23, 9 },
|
|
{ "STATIC_C_PLL_PREDIV", 18, 5 },
|
|
{ "STATIC_C_PLL_RANGEA", 14, 4 },
|
|
{ "STATIC_C_PLL_RANGEB", 10, 4 },
|
|
{ "STATIC_C_PLL_TUNE", 0, 10 },
|
|
{ "DBG_STATIC_M_PLL_CONF", 0x604c, 0 },
|
|
{ "STATIC_M_PLL_MULT", 23, 9 },
|
|
{ "STATIC_M_PLL_PREDIV", 18, 5 },
|
|
{ "STATIC_M_PLL_RANGEA", 14, 4 },
|
|
{ "STATIC_M_PLL_RANGEB", 10, 4 },
|
|
{ "STATIC_M_PLL_TUNE", 0, 10 },
|
|
{ "DBG_STATIC_KX_PLL_CONF", 0x6050, 0 },
|
|
{ "STATIC_KX_PLL_C", 21, 8 },
|
|
{ "STATIC_KX_PLL_M", 15, 6 },
|
|
{ "STATIC_KX_PLL_N1", 11, 4 },
|
|
{ "STATIC_KX_PLL_N2", 7, 4 },
|
|
{ "STATIC_KX_PLL_N3", 3, 4 },
|
|
{ "STATIC_KX_PLL_P", 0, 3 },
|
|
{ "DBG_STATIC_KR_PLL_CONF", 0x6054, 0 },
|
|
{ "STATIC_KR_PLL_C", 21, 8 },
|
|
{ "STATIC_KR_PLL_M", 15, 6 },
|
|
{ "STATIC_KR_PLL_N1", 11, 4 },
|
|
{ "STATIC_KR_PLL_N2", 7, 4 },
|
|
{ "STATIC_KR_PLL_N3", 3, 4 },
|
|
{ "STATIC_KR_PLL_P", 0, 3 },
|
|
{ "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
|
|
{ "STATIC_M_PLL_RESET", 30, 1 },
|
|
{ "STATIC_M_PLL_SLEEP", 29, 1 },
|
|
{ "STATIC_M_PLL_BYPASS", 28, 1 },
|
|
{ "STATIC_MPLL_CLK_SEL", 27, 1 },
|
|
{ "STATIC_U_PLL_SLEEP", 26, 1 },
|
|
{ "STATIC_C_PLL_SLEEP", 25, 1 },
|
|
{ "STATIC_LVDS_CLKOUT_SEL", 23, 2 },
|
|
{ "STATIC_LVDS_CLKOUT_EN", 22, 1 },
|
|
{ "STATIC_CCLK_FREQ_SEL", 20, 2 },
|
|
{ "STATIC_UCLK_FREQ_SEL", 18, 2 },
|
|
{ "ExPHYClk_sel_en", 17, 1 },
|
|
{ "ExPHYClk_sel", 15, 2 },
|
|
{ "STATIC_U_PLL_BYPASS", 14, 1 },
|
|
{ "STATIC_C_PLL_BYPASS", 13, 1 },
|
|
{ "STATIC_KR_PLL_BYPASS", 12, 1 },
|
|
{ "STATIC_KX_PLL_BYPASS", 11, 1 },
|
|
{ "STATIC_KX_PLL_V", 7, 4 },
|
|
{ "STATIC_KR_PLL_V", 3, 4 },
|
|
{ "PSRO_sel", 0, 3 },
|
|
{ "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
|
|
{ "M_OCLK_MUXSEL", 12, 1 },
|
|
{ "C_OCLK_MUXSEL", 10, 2 },
|
|
{ "U_OCLK_MUXSEL", 8, 2 },
|
|
{ "P_OCLK_MUXSEL", 6, 2 },
|
|
{ "KX_OCLK_MUXSEL", 3, 3 },
|
|
{ "KR_OCLK_MUXSEL", 0, 3 },
|
|
{ "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
|
|
{ "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
|
|
{ "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
|
|
{ "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
|
|
{ "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
|
|
{ "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
|
|
{ "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
|
|
{ "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
|
|
{ "DBG_TRACE_COUNTER", 0x6080, 0 },
|
|
{ "Counter1", 16, 16 },
|
|
{ "Counter0", 0, 16 },
|
|
{ "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
|
|
{ "DBG_TRACE_CONF", 0x6088, 0 },
|
|
{ "dbg_trace_operate_with_trg", 5, 1 },
|
|
{ "dbg_trace_operate_en", 4, 1 },
|
|
{ "dbg_operate_indv_combined", 3, 1 },
|
|
{ "dbg_operate_order_of_trigger", 2, 1 },
|
|
{ "dbg_operate_sgl_dbl_trigger", 1, 1 },
|
|
{ "dbg_operate0_or_1", 0, 1 },
|
|
{ "DBG_TRACE_RDEN", 0x608c, 0 },
|
|
{ "RD_ADDR1", 10, 8 },
|
|
{ "RD_ADDR0", 2, 8 },
|
|
{ "Rd_en1", 1, 1 },
|
|
{ "Rd_en0", 0, 1 },
|
|
{ "DBG_TRACE_WRADDR", 0x6090, 0 },
|
|
{ "Wr_pointer_addr1", 16, 8 },
|
|
{ "Wr_pointer_addr0", 0, 8 },
|
|
{ "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
|
|
{ "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
|
|
{ "DBG_PVT_REG_CALIBRATE_CTL", 0x6100, 0 },
|
|
{ "HALT_CALIBRATE", 1, 1 },
|
|
{ "RESET_CALIBRATE", 0, 1 },
|
|
{ "DBG_PVT_REG_UPDATE_CTL", 0x6104, 0 },
|
|
{ "FAST_UPDATe", 8, 1 },
|
|
{ "FORCE_REG_IN_VALUE", 2, 1 },
|
|
{ "HALT_UPDATe", 1, 1 },
|
|
{ "DBG_PVT_REG_LAST_MEASUREMENT", 0x6108, 0 },
|
|
{ "LAST_MEASUREMENT_SELECT", 8, 2 },
|
|
{ "LAST_MEASUREMENT_RESULT_BANK_B", 4, 4 },
|
|
{ "LAST_MEASUREMENT_RESULT_BANK_A", 0, 4 },
|
|
{ "DBG_PVT_REG_DRVN", 0x610c, 0 },
|
|
{ "PVT_REG_DRVN_EN", 8, 1 },
|
|
{ "PVT_REG_DRVN_B", 4, 4 },
|
|
{ "PVT_REG_DRVN_A", 0, 4 },
|
|
{ "DBG_PVT_REG_DRVP", 0x6110, 0 },
|
|
{ "PVT_REG_DRVP_EN", 8, 1 },
|
|
{ "PVT_REG_DRVP_B", 4, 4 },
|
|
{ "PVT_REG_DRVP_A", 0, 4 },
|
|
{ "DBG_PVT_REG_TERMN", 0x6114, 0 },
|
|
{ "PVT_REG_TERMN_EN", 8, 1 },
|
|
{ "PVT_REG_TERMN_B", 4, 4 },
|
|
{ "PVT_REG_TERMN_A", 0, 4 },
|
|
{ "DBG_PVT_REG_TERMP", 0x6118, 0 },
|
|
{ "PVT_REG_TERMP_EN", 8, 1 },
|
|
{ "PVT_REG_TERMP_B", 4, 4 },
|
|
{ "PVT_REG_TERMP_A", 0, 4 },
|
|
{ "DBG_PVT_REG_THRESHOLD", 0x611c, 0 },
|
|
{ "PVT_CALIBRATION_DONE", 8, 1 },
|
|
{ "THRESHOLD_TERMP_MAX_SYNC", 7, 1 },
|
|
{ "THRESHOLD_TERMP_MIN_SYNC", 6, 1 },
|
|
{ "THRESHOLD_TERMN_MAX_SYNC", 5, 1 },
|
|
{ "THRESHOLD_TERMN_MIN_SYNC", 4, 1 },
|
|
{ "THRESHOLD_DRVP_MAX_SYNC", 3, 1 },
|
|
{ "THRESHOLD_DRVP_MIN_SYNC", 2, 1 },
|
|
{ "THRESHOLD_DRVN_MAX_SYNC", 1, 1 },
|
|
{ "THRESHOLD_DRVN_MIN_SYNC", 0, 1 },
|
|
{ "DBG_PVT_REG_IN_TERMP", 0x6120, 0 },
|
|
{ "REG_IN_TERMP_B", 4, 4 },
|
|
{ "REG_IN_TERMP_A", 0, 4 },
|
|
{ "DBG_PVT_REG_IN_TERMN", 0x6124, 0 },
|
|
{ "REG_IN_TERMN_B", 4, 4 },
|
|
{ "REG_IN_TERMN_A", 0, 4 },
|
|
{ "DBG_PVT_REG_IN_DRVP", 0x6128, 0 },
|
|
{ "REG_IN_DRVP_B", 4, 4 },
|
|
{ "REG_IN_DRVP_A", 0, 4 },
|
|
{ "DBG_PVT_REG_IN_DRVN", 0x612c, 0 },
|
|
{ "REG_IN_DRVN_B", 4, 4 },
|
|
{ "REG_IN_DRVN_A", 0, 4 },
|
|
{ "DBG_PVT_REG_OUT_TERMP", 0x6130, 0 },
|
|
{ "REG_OUT_TERMP_B", 4, 4 },
|
|
{ "REG_OUT_TERMP_A", 0, 4 },
|
|
{ "DBG_PVT_REG_OUT_TERMN", 0x6134, 0 },
|
|
{ "REG_OUT_TERMN_B", 4, 4 },
|
|
{ "REG_OUT_TERMN_A", 0, 4 },
|
|
{ "DBG_PVT_REG_OUT_DRVP", 0x6138, 0 },
|
|
{ "REG_OUT_DRVP_B", 4, 4 },
|
|
{ "REG_OUT_DRVP_A", 0, 4 },
|
|
{ "DBG_PVT_REG_OUT_DRVN", 0x613c, 0 },
|
|
{ "REG_OUT_DRVN_B", 4, 4 },
|
|
{ "REG_OUT_DRVN_A", 0, 4 },
|
|
{ "DBG_PVT_REG_HISTORY_TERMP", 0x6140, 0 },
|
|
{ "termp_b_history", 4, 4 },
|
|
{ "termp_a_history", 0, 4 },
|
|
{ "DBG_PVT_REG_HISTORY_TERMN", 0x6144, 0 },
|
|
{ "TERMN_B_HISTORY", 4, 4 },
|
|
{ "TERMN_A_HISTORY", 0, 4 },
|
|
{ "DBG_PVT_REG_HISTORY_DRVP", 0x6148, 0 },
|
|
{ "DRVP_B_HISTORY", 4, 4 },
|
|
{ "DRVP_A_HISTORY", 0, 4 },
|
|
{ "DBG_PVT_REG_HISTORY_DRVN", 0x614c, 0 },
|
|
{ "DRVN_B_HISTORY", 4, 4 },
|
|
{ "DRVN_A_HISTORY", 0, 4 },
|
|
{ "DBG_PVT_REG_SAMPLE_WAIT_CLKS", 0x6150, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_mc_regs[] = {
|
|
{ "MC_PCTL_SCFG", 0x6200, 0 },
|
|
{ "rkinf_en", 5, 1 },
|
|
{ "dual_pctl_en", 4, 1 },
|
|
{ "slave_mode", 3, 1 },
|
|
{ "loopback_en", 1, 1 },
|
|
{ "hw_low_power_en", 0, 1 },
|
|
{ "MC_PCTL_SCTL", 0x6204, 0 },
|
|
{ "MC_PCTL_STAT", 0x6208, 0 },
|
|
{ "MC_PCTL_MCMD", 0x6240, 0 },
|
|
{ "start_cmd", 31, 1 },
|
|
{ "cmd_add_del", 24, 4 },
|
|
{ "rank_sel", 20, 4 },
|
|
{ "bank_addr", 17, 3 },
|
|
{ "cmd_addr", 4, 13 },
|
|
{ "cmd_opcode", 0, 3 },
|
|
{ "MC_PCTL_POWCTL", 0x6244, 0 },
|
|
{ "MC_PCTL_POWSTAT", 0x6248, 0 },
|
|
{ "phy_calibdone", 1, 1 },
|
|
{ "power_up_done", 0, 1 },
|
|
{ "MC_PCTL_MCFG", 0x6280, 0 },
|
|
{ "tfaw_cfg", 18, 2 },
|
|
{ "pd_exit_mode", 17, 1 },
|
|
{ "pd_type", 16, 1 },
|
|
{ "pd_idle", 8, 8 },
|
|
{ "page_policy", 6, 2 },
|
|
{ "ddr3_en", 5, 1 },
|
|
{ "two_t_en", 3, 1 },
|
|
{ "bl8int_en", 2, 1 },
|
|
{ "mem_bl", 0, 1 },
|
|
{ "MC_PCTL_PPCFG", 0x6284, 0 },
|
|
{ "rpmem_dis", 1, 8 },
|
|
{ "ppmem_en", 0, 1 },
|
|
{ "MC_PCTL_MSTAT", 0x6288, 0 },
|
|
{ "MC_PCTL_ODTCFG", 0x628c, 0 },
|
|
{ "rank3_odt_default", 28, 1 },
|
|
{ "rank3_odt_write_sel", 27, 1 },
|
|
{ "rank3_odt_write_nse", 26, 1 },
|
|
{ "rank3_odt_read_sel", 25, 1 },
|
|
{ "rank3_odt_read_nsel", 24, 1 },
|
|
{ "rank2_odt_default", 20, 1 },
|
|
{ "rank2_odt_write_sel", 19, 1 },
|
|
{ "rank2_odt_write_nsel", 18, 1 },
|
|
{ "rank2_odt_read_sel", 17, 1 },
|
|
{ "rank2_odt_read_nsel", 16, 1 },
|
|
{ "rank1_odt_default", 12, 1 },
|
|
{ "rank1_odt_write_sel", 11, 1 },
|
|
{ "rank1_odt_write_nsel", 10, 1 },
|
|
{ "rank1_odt_read_sel", 9, 1 },
|
|
{ "rank1_odt_read_nsel", 8, 1 },
|
|
{ "rank0_odt_default", 4, 1 },
|
|
{ "rank0_odt_write_sel", 3, 1 },
|
|
{ "rank0_odt_write_nsel", 2, 1 },
|
|
{ "rank0_odt_read_sel", 1, 1 },
|
|
{ "rank0_odt_read_nsel", 0, 1 },
|
|
{ "MC_PCTL_DQSECFG", 0x6290, 0 },
|
|
{ "dv_alat", 20, 4 },
|
|
{ "dv_alen", 16, 2 },
|
|
{ "dse_alat", 12, 4 },
|
|
{ "dse_alen", 8, 2 },
|
|
{ "qse_alat", 4, 4 },
|
|
{ "qse_alen", 0, 2 },
|
|
{ "MC_PCTL_DTUPDES", 0x6294, 0 },
|
|
{ "dtu_rd_missing", 13, 1 },
|
|
{ "dtu_eaffl", 9, 4 },
|
|
{ "dtu_random_error", 8, 1 },
|
|
{ "dtu_error_b7", 7, 1 },
|
|
{ "dtu_err_b6", 6, 1 },
|
|
{ "dtu_err_b5", 5, 1 },
|
|
{ "dtu_err_b4", 4, 1 },
|
|
{ "dtu_err_b3", 3, 1 },
|
|
{ "dtu_err_b2", 2, 1 },
|
|
{ "dtu_err_b1", 1, 1 },
|
|
{ "dtu_err_b0", 0, 1 },
|
|
{ "MC_PCTL_DTUNA", 0x6298, 0 },
|
|
{ "MC_PCTL_DTUNE", 0x629c, 0 },
|
|
{ "MC_PCTL_DTUPRDO", 0x62a0, 0 },
|
|
{ "dtu_allbits_1", 16, 16 },
|
|
{ "dtu_allbits_0", 0, 16 },
|
|
{ "MC_PCTL_DTUPRD1", 0x62a4, 0 },
|
|
{ "dtu_allbits_3", 16, 16 },
|
|
{ "dtu_allbits_2", 0, 16 },
|
|
{ "MC_PCTL_DTUPRD2", 0x62a8, 0 },
|
|
{ "dtu_allbits_5", 16, 16 },
|
|
{ "dtu_allbits_4", 0, 16 },
|
|
{ "MC_PCTL_DTUPRD3", 0x62ac, 0 },
|
|
{ "dtu_allbits_7", 16, 16 },
|
|
{ "dtu_allbits_6", 0, 16 },
|
|
{ "MC_PCTL_DTUAWDT", 0x62b0, 0 },
|
|
{ "number_ranks", 9, 2 },
|
|
{ "row_addr_width", 6, 2 },
|
|
{ "bank_addr_width", 3, 2 },
|
|
{ "column_addr_width", 0, 2 },
|
|
{ "MC_PCTL_TOGCNT1U", 0x62c0, 0 },
|
|
{ "MC_PCTL_TINIT", 0x62c4, 0 },
|
|
{ "MC_PCTL_TRSTH", 0x62c8, 0 },
|
|
{ "MC_PCTL_TOGCNT100N", 0x62cc, 0 },
|
|
{ "MC_PCTL_TREFI", 0x62d0, 0 },
|
|
{ "MC_PCTL_TMRD", 0x62d4, 0 },
|
|
{ "MC_PCTL_TRFC", 0x62d8, 0 },
|
|
{ "MC_PCTL_TRP", 0x62dc, 0 },
|
|
{ "MC_PCTL_TRTW", 0x62e0, 0 },
|
|
{ "MC_PCTL_TAL", 0x62e4, 0 },
|
|
{ "MC_PCTL_TCL", 0x62e8, 0 },
|
|
{ "MC_PCTL_TCWL", 0x62ec, 0 },
|
|
{ "MC_PCTL_TRAS", 0x62f0, 0 },
|
|
{ "MC_PCTL_TRC", 0x62f4, 0 },
|
|
{ "MC_PCTL_TRCD", 0x62f8, 0 },
|
|
{ "MC_PCTL_TRRD", 0x62fc, 0 },
|
|
{ "MC_PCTL_TRTP", 0x6300, 0 },
|
|
{ "MC_PCTL_TWR", 0x6304, 0 },
|
|
{ "MC_PCTL_TWTR", 0x6308, 0 },
|
|
{ "MC_PCTL_TEXSR", 0x630c, 0 },
|
|
{ "MC_PCTL_TXP", 0x6310, 0 },
|
|
{ "MC_PCTL_TXPDLL", 0x6314, 0 },
|
|
{ "MC_PCTL_TZQCS", 0x6318, 0 },
|
|
{ "MC_PCTL_TZQCSI", 0x631c, 0 },
|
|
{ "MC_PCTL_TDQS", 0x6320, 0 },
|
|
{ "MC_PCTL_TCKSRE", 0x6324, 0 },
|
|
{ "MC_PCTL_TCKSRX", 0x6328, 0 },
|
|
{ "MC_PCTL_TCKE", 0x632c, 0 },
|
|
{ "MC_PCTL_TMOD", 0x6330, 0 },
|
|
{ "MC_PCTL_TRSTL", 0x6334, 0 },
|
|
{ "MC_PCTL_TZQCL", 0x6338, 0 },
|
|
{ "MC_PCTL_DWLCFG0", 0x6370, 0 },
|
|
{ "MC_PCTL_DWLCFG1", 0x6374, 0 },
|
|
{ "MC_PCTL_DWLCFG2", 0x6378, 0 },
|
|
{ "MC_PCTL_DWLCFG3", 0x637c, 0 },
|
|
{ "MC_PCTL_ECCCFG", 0x6380, 0 },
|
|
{ "inline_syn_en", 4, 1 },
|
|
{ "ecc_en", 3, 1 },
|
|
{ "ecc_intr_en", 2, 1 },
|
|
{ "MC_PCTL_ECCTST", 0x6384, 0 },
|
|
{ "MC_PCTL_ECCCLR", 0x6388, 0 },
|
|
{ "clr_ecc_log", 1, 1 },
|
|
{ "clr_ecc_intr", 0, 1 },
|
|
{ "MC_PCTL_ECCLOG", 0x638c, 0 },
|
|
{ "MC_PCTL_DTUWACTL", 0x6400, 0 },
|
|
{ "dtu_wr_rank", 30, 2 },
|
|
{ "dtu_wr_row", 13, 17 },
|
|
{ "dtu_wr_bank", 10, 3 },
|
|
{ "dtu_wr_col", 0, 10 },
|
|
{ "MC_PCTL_DTURACTL", 0x6404, 0 },
|
|
{ "dtu_rd_rank", 30, 2 },
|
|
{ "dtu_rd_row", 13, 17 },
|
|
{ "dtu_rd_bank", 10, 3 },
|
|
{ "dtu_rd_col", 0, 10 },
|
|
{ "MC_PCTL_DTUCFG", 0x6408, 0 },
|
|
{ "dtu_row_increments", 16, 7 },
|
|
{ "dtu_wr_multi_rd", 15, 1 },
|
|
{ "dtu_data_mask_en", 14, 1 },
|
|
{ "dtu_target_lane", 10, 4 },
|
|
{ "dtu_generate_random", 9, 1 },
|
|
{ "dtu_incr_banks", 8, 1 },
|
|
{ "dtu_incr_cols", 7, 1 },
|
|
{ "dtu_nalen", 1, 6 },
|
|
{ "dtu_enable", 0, 1 },
|
|
{ "MC_PCTL_DTUECTL", 0x640c, 0 },
|
|
{ "wr_multi_rd_rst", 2, 1 },
|
|
{ "run_error_reports", 1, 1 },
|
|
{ "run_dtu", 0, 1 },
|
|
{ "MC_PCTL_DTUWD0", 0x6410, 0 },
|
|
{ "dtu_wr_byte3", 24, 8 },
|
|
{ "dtu_wr_byte2", 16, 8 },
|
|
{ "dtu_wr_byte1", 8, 8 },
|
|
{ "dtu_wr_byte0", 0, 8 },
|
|
{ "MC_PCTL_DTUWD1", 0x6414, 0 },
|
|
{ "dtu_wr_byte7", 24, 8 },
|
|
{ "dtu_wr_byte6", 16, 8 },
|
|
{ "dtu_wr_byte5", 8, 8 },
|
|
{ "dtu_wr_byte4", 0, 8 },
|
|
{ "MC_PCTL_DTUWD2", 0x6418, 0 },
|
|
{ "dtu_wr_byte11", 24, 8 },
|
|
{ "dtu_wr_byte10", 16, 8 },
|
|
{ "dtu_wr_byte9", 8, 8 },
|
|
{ "dtu_wr_byte8", 0, 8 },
|
|
{ "MC_PCTL_DTUWD3", 0x641c, 0 },
|
|
{ "dtu_wr_byte15", 24, 8 },
|
|
{ "dtu_wr_byte14", 16, 8 },
|
|
{ "dtu_wr_byte13", 8, 8 },
|
|
{ "dtu_wr_byte12", 0, 8 },
|
|
{ "MC_PCTL_DTUWDM", 0x6420, 0 },
|
|
{ "MC_PCTL_DTURD0", 0x6424, 0 },
|
|
{ "dtu_rd_byte3", 24, 8 },
|
|
{ "dtu_rd_byte2", 16, 8 },
|
|
{ "dtu_rd_byte1", 8, 8 },
|
|
{ "dtu_rd_byte0", 0, 8 },
|
|
{ "MC_PCTL_DTURD1", 0x6428, 0 },
|
|
{ "dtu_rd_byte7", 24, 8 },
|
|
{ "dtu_rd_byte6", 16, 8 },
|
|
{ "dtu_rd_byte5", 8, 8 },
|
|
{ "dtu_rd_byte4", 0, 8 },
|
|
{ "MC_PCTL_DTURD2", 0x642c, 0 },
|
|
{ "dtu_rd_byte11", 24, 8 },
|
|
{ "dtu_rd_byte10", 16, 8 },
|
|
{ "dtu_rd_byte9", 8, 8 },
|
|
{ "dtu_rd_byte8", 0, 8 },
|
|
{ "MC_PCTL_DTURD3", 0x6430, 0 },
|
|
{ "dtu_rd_byte15", 24, 8 },
|
|
{ "dtu_rd_byte14", 16, 8 },
|
|
{ "dtu_rd_byte13", 8, 8 },
|
|
{ "dtu_rd_byte12", 0, 8 },
|
|
{ "MC_DTULFSRWD", 0x6434, 0 },
|
|
{ "MC_PCTL_DTULFSRRD", 0x6438, 0 },
|
|
{ "MC_PCTL_DTUEAF", 0x643c, 0 },
|
|
{ "ea_rank", 30, 2 },
|
|
{ "ea_row", 13, 17 },
|
|
{ "ea_bank", 10, 3 },
|
|
{ "ea_column", 0, 10 },
|
|
{ "MC_PCTL_PHYPVTCFG", 0x6500, 0 },
|
|
{ "pvt_upd_req_en", 15, 1 },
|
|
{ "pvt_upd_trig_pol", 14, 1 },
|
|
{ "pvt_upd_trig_type", 12, 1 },
|
|
{ "pvt_upd_done_pol", 10, 1 },
|
|
{ "pvt_upd_done_type", 8, 2 },
|
|
{ "phy_upd_req_en", 7, 1 },
|
|
{ "phy_upd_trig_pol", 6, 1 },
|
|
{ "phy_upd_trig_type", 4, 1 },
|
|
{ "phy_upd_done_pol", 2, 1 },
|
|
{ "phy_upd_done_type", 0, 2 },
|
|
{ "MC_PCTL_PHYPVTSTAT", 0x6504, 0 },
|
|
{ "i_pvt_upd_trig", 5, 1 },
|
|
{ "i_pvt_upd_done", 4, 1 },
|
|
{ "i_phy_upd_trig", 1, 1 },
|
|
{ "i_phy_upd_done", 0, 1 },
|
|
{ "MC_PCTL_PHYTUPDON", 0x6508, 0 },
|
|
{ "MC_PCTL_PHYTUPDDLY", 0x650c, 0 },
|
|
{ "MC_PCTL_PVTTUPON", 0x6510, 0 },
|
|
{ "MC_PCTL_PVTTUPDDLY", 0x6514, 0 },
|
|
{ "MC_PCTL_PHYPVTUPDI", 0x6518, 0 },
|
|
{ "MC_PCTL_PHYIOCRV1", 0x651c, 0 },
|
|
{ "byte_oe_ctl", 16, 2 },
|
|
{ "dyn_soc_odt_alat", 12, 4 },
|
|
{ "dyn_soc_odt_aten", 8, 2 },
|
|
{ "dyn_soc_odt", 2, 1 },
|
|
{ "soc_odt_en", 0, 1 },
|
|
{ "MC_PCTL_PHYTUPDWAIT", 0x6520, 0 },
|
|
{ "MC_PCTL_PVTTUPDWAIT", 0x6524, 0 },
|
|
{ "MC_DDR3PHYAC_GCR", 0x6a00, 0 },
|
|
{ "WLRANK", 8, 2 },
|
|
{ "FDEPTH", 6, 2 },
|
|
{ "LPFDEPTH", 4, 2 },
|
|
{ "LPFEN", 3, 1 },
|
|
{ "WL", 2, 1 },
|
|
{ "CAL", 1, 1 },
|
|
{ "MDLEN", 0, 1 },
|
|
{ "MC_DDR3PHYAC_RCR0", 0x6a04, 0 },
|
|
{ "OCPONR", 8, 1 },
|
|
{ "OCPOND", 7, 1 },
|
|
{ "OCOEN", 6, 1 },
|
|
{ "CKEPONR", 5, 1 },
|
|
{ "CKEPOND", 4, 1 },
|
|
{ "CKEOEN", 3, 1 },
|
|
{ "CKPONR", 2, 1 },
|
|
{ "CKPOND", 1, 1 },
|
|
{ "CKOEN", 0, 1 },
|
|
{ "MC_DDR3PHYAC_ACCR", 0x6a14, 0 },
|
|
{ "ACPONR", 8, 1 },
|
|
{ "ACPOND", 7, 1 },
|
|
{ "ACOEN", 6, 1 },
|
|
{ "CK5PONR", 5, 1 },
|
|
{ "CK5POND", 4, 1 },
|
|
{ "CK5OEN", 3, 1 },
|
|
{ "CK4PONR", 2, 1 },
|
|
{ "CK4POND", 1, 1 },
|
|
{ "CK4OEN", 0, 1 },
|
|
{ "MC_DDR3PHYAC_GSR", 0x6a18, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "INIT", 3, 1 },
|
|
{ "WL", 2, 1 },
|
|
{ "CAL", 1, 1 },
|
|
{ "ACCAL", 0, 1 },
|
|
{ "MC_DDR3PHYAC_ECSR", 0x6a1c, 0 },
|
|
{ "WLDEC", 1, 1 },
|
|
{ "WLINC", 0, 1 },
|
|
{ "MC_DDR3PHYAC_OCSR", 0x6a20, 0 },
|
|
{ "WLDEC", 1, 1 },
|
|
{ "WLINC", 0, 1 },
|
|
{ "MC_DDR3PHYAC_MDIPR", 0x6a24, 0 },
|
|
{ "MC_DDR3PHYAC_MDTPR", 0x6a28, 0 },
|
|
{ "MC_DDR3PHYAC_MDPPR0", 0x6a2c, 0 },
|
|
{ "MC_DDR3PHYAC_MDPPR1", 0x6a30, 0 },
|
|
{ "MC_DDR3PHYAC_PMBDR0", 0x6a34, 0 },
|
|
{ "MC_DDR3PHYAC_PMBDR1", 0x6a38, 0 },
|
|
{ "MC_DDR3PHYAC_ACR", 0x6a60, 0 },
|
|
{ "TSEL", 9, 1 },
|
|
{ "ISEL", 7, 2 },
|
|
{ "CALBYP", 2, 1 },
|
|
{ "SDRSELINV", 1, 1 },
|
|
{ "CKINV", 0, 1 },
|
|
{ "MC_DDR3PHYAC_PSCR", 0x6a64, 0 },
|
|
{ "MC_DDR3PHYAC_PRCR", 0x6a68, 0 },
|
|
{ "PHYINIT", 9, 1 },
|
|
{ "PHYHRST", 7, 1 },
|
|
{ "RSTCLKS", 3, 4 },
|
|
{ "PLLPD", 2, 1 },
|
|
{ "PLLRST", 1, 1 },
|
|
{ "PHYRST", 0, 1 },
|
|
{ "MC_DDR3PHYAC_PLLCR0", 0x6a6c, 0 },
|
|
{ "RSTCXKS", 4, 5 },
|
|
{ "ICPSEL", 3, 1 },
|
|
{ "TESTA", 0, 3 },
|
|
{ "MC_DDR3PHYAC_PLLCR1", 0x6a70, 0 },
|
|
{ "BYPASS", 9, 1 },
|
|
{ "BDIV", 3, 2 },
|
|
{ "TESTD", 0, 3 },
|
|
{ "MC_DDR3PHYAC_CLKENR", 0x6a78, 0 },
|
|
{ "CKCLKEN", 3, 6 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x6b00, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x6b04, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x6b08, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x6b0c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x6b1c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x6b20, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x6b24, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x6b28, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x6b2c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x6b30, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x6b34, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x6b38, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x6b3c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x6b40, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x6b44, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x6b48, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x6b4c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x6b50, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x6b54, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x6b58, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x6b5c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x6b60, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x6b64, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x6b68, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x6b6c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x6b70, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x6b74, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x6b78, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x6b7c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x6b80, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x6b84, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x6bf0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x6bf4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x6bf8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x6c00, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x6c04, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x6c08, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x6c0c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x6c1c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x6c20, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x6c24, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x6c28, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x6c2c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x6c30, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x6c34, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x6c38, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x6c3c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x6c40, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x6c44, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x6c48, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x6c4c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x6c50, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x6c54, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x6c58, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x6c5c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x6c60, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x6c64, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x6c68, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x6c6c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x6c70, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x6c74, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x6c78, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x6c7c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x6c80, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x6c84, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x6cf0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x6cf4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x6cf8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x6d00, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x6d04, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x6d08, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x6d0c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x6d1c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x6d20, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x6d24, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x6d28, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x6d2c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x6d30, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x6d34, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x6d38, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x6d3c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x6d40, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x6d44, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x6d48, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x6d4c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x6d50, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x6d54, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x6d58, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x6d5c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x6d60, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x6d64, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x6d68, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x6d6c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x6d70, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x6d74, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x6d78, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x6d7c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x6d80, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x6d84, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x6df0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x6df4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x6df8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x6e00, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x6e04, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x6e08, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x6e0c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x6e1c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x6e20, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x6e24, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x6e28, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x6e2c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x6e30, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x6e34, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x6e38, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x6e3c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x6e40, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x6e44, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x6e48, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x6e4c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x6e50, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x6e54, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x6e58, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x6e5c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x6e60, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x6e64, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x6e68, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x6e6c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x6e70, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x6e74, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x6e78, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x6e7c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x6e80, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x6e84, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x6ef0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x6ef4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x6ef8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x6f00, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x6f04, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x6f08, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x6f0c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x6f1c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x6f20, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x6f24, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x6f28, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x6f2c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x6f30, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x6f34, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x6f38, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x6f3c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x6f40, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x6f44, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x6f48, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x6f4c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x6f50, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x6f54, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x6f58, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x6f5c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x6f60, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x6f64, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x6f68, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x6f6c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x6f70, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x6f74, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x6f78, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x6f7c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x6f80, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x6f84, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x6ff0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x6ff4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x6ff8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x7000, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x7004, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x7008, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x700c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x701c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x7020, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x7024, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x7028, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x702c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x7030, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x7034, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x7038, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x703c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x7040, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x7044, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x7048, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x704c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x7050, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x7054, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x7058, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x705c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x7060, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x7064, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x7068, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x706c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x7070, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x7074, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x7078, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x707c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x7080, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x7084, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x70f0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x70f4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x70f8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x7100, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x7104, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x7108, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x710c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x711c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x7120, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x7124, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x7128, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x712c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x7130, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x7134, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x7138, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x713c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x7140, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x7144, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x7148, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x714c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x7150, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x7154, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x7158, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x715c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x7160, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x7164, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x7168, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x716c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x7170, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x7174, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x7178, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x717c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x7180, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x7184, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x71f0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x71f4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x71f8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x7200, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x7204, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x7208, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x720c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x721c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x7220, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x7224, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x7228, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x722c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x7230, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x7234, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x7238, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x723c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x7240, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x7244, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x7248, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x724c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x7250, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x7254, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x7258, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x725c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x7260, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x7264, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x7268, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x726c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x7270, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x7274, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x7278, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x727c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x7280, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x7284, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x72f0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x72f4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x72f8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_GCR", 0x7300, 0 },
|
|
{ "PONR", 6, 1 },
|
|
{ "POND", 5, 1 },
|
|
{ "RDBDVT", 4, 1 },
|
|
{ "WDBDVT", 3, 1 },
|
|
{ "RDSDVT", 2, 1 },
|
|
{ "WDSDVT", 1, 1 },
|
|
{ "WLSDVT", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_WDSDR", 0x7304, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDPR", 0x7308, 0 },
|
|
{ "MC_DDR3PHYDATX8_WLDR", 0x730c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR0", 0x731c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR1", 0x7320, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR2", 0x7324, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR3", 0x7328, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR4", 0x732c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR5", 0x7330, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR6", 0x7334, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR7", 0x7338, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDR8", 0x733c, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDMR", 0x7340, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDSDR", 0x7344, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR0", 0x7348, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR1", 0x734c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR2", 0x7350, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR3", 0x7354, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR4", 0x7358, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR5", 0x735c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR6", 0x7360, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDR7", 0x7364, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDMR", 0x7368, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR0", 0x736c, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR1", 0x7370, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR2", 0x7374, 0 },
|
|
{ "MC_DDR3PHYDATX8_PMBDR3", 0x7378, 0 },
|
|
{ "MC_DDR3PHYDATX8_WDBDPR", 0x737c, 0 },
|
|
{ "MC_DDR3PHYDATX8_RDBDPR", 0x7380, 0 },
|
|
{ "MC_DDR3PHYDATX8_GSR", 0x7384, 0 },
|
|
{ "WLERR", 4, 1 },
|
|
{ "WLDONE", 3, 1 },
|
|
{ "WLCAL", 2, 1 },
|
|
{ "Read", 1, 1 },
|
|
{ "RDQSCAL", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_ACR", 0x73f0, 0 },
|
|
{ "PHYHRST", 9, 1 },
|
|
{ "WLSTEP", 8, 1 },
|
|
{ "SDRSELINV", 2, 1 },
|
|
{ "DDRSELINV", 1, 1 },
|
|
{ "DSINV", 0, 1 },
|
|
{ "MC_DDR3PHYDATX8_RSR", 0x73f4, 0 },
|
|
{ "WLRANK", 9, 1 },
|
|
{ "RANK", 0, 2 },
|
|
{ "MC_DDR3PHYDATX8_CLKENR", 0x73f8, 0 },
|
|
{ "DTOSEL", 8, 2 },
|
|
{ "HDRCLKEN", 2, 1 },
|
|
{ "SDRCLKEN", 1, 1 },
|
|
{ "DDRCLKEN", 0, 1 },
|
|
{ "MC_PVT_REG_CALIBRATE_CTL", 0x7400, 0 },
|
|
{ "HALT_CALIBRATE", 1, 1 },
|
|
{ "RESET_CALIBRATE", 0, 1 },
|
|
{ "MC_PVT_REG_UPDATE_CTL", 0x7404, 0 },
|
|
{ "FAST_UPDATe", 8, 1 },
|
|
{ "FORCE_REG_IN_VALUE", 2, 1 },
|
|
{ "HALT_UPDATe", 1, 1 },
|
|
{ "MC_PVT_REG_LAST_MEASUREMENT", 0x7408, 0 },
|
|
{ "LAST_MEASUREMENT_SELECT", 8, 2 },
|
|
{ "LAST_MEASUREMENT_RESULT_BANK_B", 4, 4 },
|
|
{ "LAST_MEASUREMENT_RESULT_BANK_A", 0, 4 },
|
|
{ "MC_PVT_REG_DRVN", 0x740c, 0 },
|
|
{ "PVT_REG_DRVN_EN", 8, 1 },
|
|
{ "PVT_REG_DRVN_B", 4, 4 },
|
|
{ "PVT_REG_DRVN_A", 0, 4 },
|
|
{ "MC_PVT_REG_DRVP", 0x7410, 0 },
|
|
{ "PVT_REG_DRVP_EN", 8, 1 },
|
|
{ "PVT_REG_DRVP_B", 4, 4 },
|
|
{ "PVT_REG_DRVP_A", 0, 4 },
|
|
{ "MC_PVT_REG_TERMN", 0x7414, 0 },
|
|
{ "PVT_REG_TERMN_EN", 8, 1 },
|
|
{ "PVT_REG_TERMN_B", 4, 4 },
|
|
{ "PVT_REG_TERMN_A", 0, 4 },
|
|
{ "MC_PVT_REG_TERMP", 0x7418, 0 },
|
|
{ "PVT_REG_TERMP_EN", 8, 1 },
|
|
{ "PVT_REG_TERMP_B", 4, 4 },
|
|
{ "PVT_REG_TERMP_A", 0, 4 },
|
|
{ "MC_PVT_REG_THRESHOLD", 0x741c, 0 },
|
|
{ "PVT_CALIBRATION_DONE", 8, 1 },
|
|
{ "THRESHOLD_TERMP_MAX_SYNC", 7, 1 },
|
|
{ "THRESHOLD_TERMP_MIN_SYNC", 6, 1 },
|
|
{ "THRESHOLD_TERMN_MAX_SYNC", 5, 1 },
|
|
{ "THRESHOLD_TERMN_MIN_SYNC", 4, 1 },
|
|
{ "THRESHOLD_DRVP_MAX_SYNC", 3, 1 },
|
|
{ "THRESHOLD_DRVP_MIN_SYNC", 2, 1 },
|
|
{ "THRESHOLD_DRVN_MAX_SYNC", 1, 1 },
|
|
{ "THRESHOLD_DRVN_MIN_SYNC", 0, 1 },
|
|
{ "MC_PVT_REG_IN_TERMP", 0x7420, 0 },
|
|
{ "REG_IN_TERMP_B", 4, 4 },
|
|
{ "REG_IN_TERMP_A", 0, 4 },
|
|
{ "MC_PVT_REG_IN_TERMN", 0x7424, 0 },
|
|
{ "REG_IN_TERMN_B", 4, 4 },
|
|
{ "REG_IN_TERMN_A", 0, 4 },
|
|
{ "MC_PVT_REG_IN_DRVP", 0x7428, 0 },
|
|
{ "REG_IN_DRVP_B", 4, 4 },
|
|
{ "REG_IN_DRVP_A", 0, 4 },
|
|
{ "MC_PVT_REG_IN_DRVN", 0x742c, 0 },
|
|
{ "REG_IN_DRVN_B", 4, 4 },
|
|
{ "REG_IN_DRVN_A", 0, 4 },
|
|
{ "MC_PVT_REG_OUT_TERMP", 0x7430, 0 },
|
|
{ "REG_OUT_TERMP_B", 4, 4 },
|
|
{ "REG_OUT_TERMP_A", 0, 4 },
|
|
{ "MC_PVT_REG_OUT_TERMN", 0x7434, 0 },
|
|
{ "REG_OUT_TERMN_B", 4, 4 },
|
|
{ "REG_OUT_TERMN_A", 0, 4 },
|
|
{ "MC_PVT_REG_OUT_DRVP", 0x7438, 0 },
|
|
{ "REG_OUT_DRVP_B", 4, 4 },
|
|
{ "REG_OUT_DRVP_A", 0, 4 },
|
|
{ "MC_PVT_REG_OUT_DRVN", 0x743c, 0 },
|
|
{ "REG_OUT_DRVN_B", 4, 4 },
|
|
{ "REG_OUT_DRVN_A", 0, 4 },
|
|
{ "MC_PVT_REG_HISTORY_TERMP", 0x7440, 0 },
|
|
{ "termp_b_history", 4, 4 },
|
|
{ "termp_a_history", 0, 4 },
|
|
{ "MC_PVT_REG_HISTORY_TERMN", 0x7444, 0 },
|
|
{ "TERMN_B_HISTORY", 4, 4 },
|
|
{ "TERMN_A_HISTORY", 0, 4 },
|
|
{ "MC_PVT_REG_HISTORY_DRVP", 0x7448, 0 },
|
|
{ "DRVP_B_HISTORY", 4, 4 },
|
|
{ "DRVP_A_HISTORY", 0, 4 },
|
|
{ "MC_PVT_REG_HISTORY_DRVN", 0x744c, 0 },
|
|
{ "DRVN_B_HISTORY", 4, 4 },
|
|
{ "DRVN_A_HISTORY", 0, 4 },
|
|
{ "MC_PVT_REG_SAMPLE_WAIT_CLKS", 0x7450, 0 },
|
|
{ "MC_DDRPHY_RST_CTRL", 0x7500, 0 },
|
|
{ "DDRIO_ENABLE", 1, 1 },
|
|
{ "PHY_RST_N", 0, 1 },
|
|
{ "MC_PERFORMANCE_CTRL", 0x7504, 0 },
|
|
{ "STALL_CHK_BIT", 2, 1 },
|
|
{ "DDR3_BRC_MODE", 1, 1 },
|
|
{ "RMW_PERF_CTRL", 0, 1 },
|
|
{ "MC_ECC_CTRL", 0x7508, 0 },
|
|
{ "ECC_BYPASS_BIST", 1, 1 },
|
|
{ "ECC_DISABLE", 0, 1 },
|
|
{ "MC_PAR_ENABLE", 0x750c, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 3, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 2, 1 },
|
|
{ "PERR_REG_INT_ENABLE", 1, 1 },
|
|
{ "PERR_BLK_INT_ENABLE", 0, 1 },
|
|
{ "MC_PAR_CAUSE", 0x7510, 0 },
|
|
{ "ECC_UE_PAR_CAUSE", 3, 1 },
|
|
{ "ECC_CE_PAR_CAUSE", 2, 1 },
|
|
{ "FIFOR_PAR_CAUSE", 1, 1 },
|
|
{ "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
|
|
{ "MC_INT_ENABLE", 0x7514, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "MC_INT_CAUSE", 0x7518, 0 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "MC_ECC_STATUS", 0x751c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "MC_PHY_CTRL", 0x7520, 0 },
|
|
{ "MC_STATIC_CFG_STATUS", 0x7524, 0 },
|
|
{ "STATIC_MODE", 9, 1 },
|
|
{ "STATIC_DEN", 6, 3 },
|
|
{ "STATIC_ORG", 5, 1 },
|
|
{ "STATIC_RKS", 4, 1 },
|
|
{ "STATIC_WIDTH", 1, 3 },
|
|
{ "STATIC_SLOW", 0, 1 },
|
|
{ "MC_CORE_PCTL_STAT", 0x7528, 0 },
|
|
{ "MC_DEBUG_CNT", 0x752c, 0 },
|
|
{ "WDATA_OCNT", 8, 5 },
|
|
{ "RDATA_OCNT", 0, 5 },
|
|
{ "MC_BONUS", 0x7530, 0 },
|
|
{ "MC_BIST_CMD", 0x7600, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "MC_BIST_CMD_ADDR", 0x7604, 0 },
|
|
{ "MC_BIST_CMD_LEN", 0x7608, 0 },
|
|
{ "MC_BIST_DATA_PATTERN", 0x760c, 0 },
|
|
{ "MC_BIST_USER_WDATA0", 0x7614, 0 },
|
|
{ "MC_BIST_USER_WDATA1", 0x7618, 0 },
|
|
{ "MC_BIST_USER_WDATA2", 0x761c, 0 },
|
|
{ "MC_BIST_NUM_ERR", 0x7680, 0 },
|
|
{ "MC_BIST_ERR_FIRST_ADDR", 0x7684, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x7688, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x768c, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x7690, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x7694, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x7698, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x769c, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76a0, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76a4, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76a8, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76ac, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76b0, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76b4, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76b8, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76bc, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76c0, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76c4, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76c8, 0 },
|
|
{ "MC_BIST_STATUS_RDATA", 0x76cc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_ma_regs[] = {
|
|
{ "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_LE_DEBUG_CNT", 0x7784, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_CIM_DEBUG_CNT", 0x7788, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_HMA_DEBUG_CNT", 0x7798, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_EDRAM0_BAR", 0x77c0, 0 },
|
|
{ "EDRAM0_BASE", 16, 12 },
|
|
{ "EDRAM0_SIZE", 0, 12 },
|
|
{ "MA_EDRAM1_BAR", 0x77c4, 0 },
|
|
{ "EDRAM1_BASE", 16, 12 },
|
|
{ "EDRAM1_SIZE", 0, 12 },
|
|
{ "MA_EXT_MEMORY_BAR", 0x77c8, 0 },
|
|
{ "EXT_MEM_BASE", 16, 12 },
|
|
{ "EXT_MEM_SIZE", 0, 12 },
|
|
{ "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
|
|
{ "HMA_BASE", 16, 12 },
|
|
{ "HMA_SIZE", 0, 12 },
|
|
{ "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
|
|
{ "BRC_MODE", 2, 1 },
|
|
{ "EXT_MEM_PAGE_SIZE", 0, 2 },
|
|
{ "MA_ARB_CTRL", 0x77d4, 0 },
|
|
{ "DIS_PAGE_HINT", 1, 1 },
|
|
{ "DIS_ADV_ARB", 0, 1 },
|
|
{ "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
|
|
{ "HMA_ENABLE", 3, 1 },
|
|
{ "EXT_MEM_ENABLE", 2, 1 },
|
|
{ "EDRAM1_ENABLE", 1, 1 },
|
|
{ "EDRAM0_ENABLE", 0, 1 },
|
|
{ "MA_INT_ENABLE", 0x77dc, 0 },
|
|
{ "MEM_PERR_INT_ENABLE", 1, 1 },
|
|
{ "MEM_WRAP_INT_ENABLE", 0, 1 },
|
|
{ "MA_INT_CAUSE", 0x77e0, 0 },
|
|
{ "MEM_PERR_INT_CAUSE", 1, 1 },
|
|
{ "MEM_WRAP_INT_CAUSE", 0, 1 },
|
|
{ "MA_INT_WRAP_STATUS", 0x77e4, 0 },
|
|
{ "MEM_WRAP_ADDRESS", 4, 28 },
|
|
{ "MEM_WRAP_CLIENT_NUM", 0, 4 },
|
|
{ "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
|
|
{ "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
|
|
{ "MA_PARITY_ERROR_ENABLE", 0x77f0, 0 },
|
|
{ "TP_DMARBT_PAR_ERROR_EN", 31, 1 },
|
|
{ "LOGIC_FIFO_PAR_ERROR_EN", 30, 1 },
|
|
{ "ARB3_PAR_WRQUEUE_ERROR_EN", 29, 1 },
|
|
{ "ARB2_PAR_WRQUEUE_ERROR_EN", 28, 1 },
|
|
{ "ARB1_PAR_WRQUEUE_ERROR_EN", 27, 1 },
|
|
{ "ARB0_PAR_WRQUEUE_ERROR_EN", 26, 1 },
|
|
{ "ARB3_PAR_RDQUEUE_ERROR_EN", 25, 1 },
|
|
{ "ARB2_PAR_RDQUEUE_ERROR_EN", 24, 1 },
|
|
{ "ARB1_PAR_RDQUEUE_ERROR_EN", 23, 1 },
|
|
{ "ARB0_PAR_RDQUEUE_ERROR_EN", 22, 1 },
|
|
{ "CL10_PAR_WRQUEUE_ERROR_EN", 21, 1 },
|
|
{ "CL9_PAR_WRQUEUE_ERROR_EN", 20, 1 },
|
|
{ "CL8_PAR_WRQUEUE_ERROR_EN", 19, 1 },
|
|
{ "CL7_PAR_WRQUEUE_ERROR_EN", 18, 1 },
|
|
{ "CL6_PAR_WRQUEUE_ERROR_EN", 17, 1 },
|
|
{ "CL5_PAR_WRQUEUE_ERROR_EN", 16, 1 },
|
|
{ "CL4_PAR_WRQUEUE_ERROR_EN", 15, 1 },
|
|
{ "CL3_PAR_WRQUEUE_ERROR_EN", 14, 1 },
|
|
{ "CL2_PAR_WRQUEUE_ERROR_EN", 13, 1 },
|
|
{ "CL1_PAR_WRQUEUE_ERROR_EN", 12, 1 },
|
|
{ "CL0_PAR_WRQUEUE_ERROR_EN", 11, 1 },
|
|
{ "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 },
|
|
{ "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 },
|
|
{ "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 },
|
|
{ "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 },
|
|
{ "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 },
|
|
{ "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 },
|
|
{ "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 },
|
|
{ "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 },
|
|
{ "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 },
|
|
{ "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 },
|
|
{ "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
|
|
{ "MA_PARITY_ERROR_STATUS", 0x77f4, 0 },
|
|
{ "TP_DMARBT_PAR_ERROR", 31, 1 },
|
|
{ "LOGIC_FIFO_PAR_ERROR", 30, 1 },
|
|
{ "ARB3_PAR_WRQUEUE_ERROR", 29, 1 },
|
|
{ "ARB2_PAR_WRQUEUE_ERROR", 28, 1 },
|
|
{ "ARB1_PAR_WRQUEUE_ERROR", 27, 1 },
|
|
{ "ARB0_PAR_WRQUEUE_ERROR", 26, 1 },
|
|
{ "ARB3_PAR_RDQUEUE_ERROR", 25, 1 },
|
|
{ "ARB2_PAR_RDQUEUE_ERROR", 24, 1 },
|
|
{ "ARB1_PAR_RDQUEUE_ERROR", 23, 1 },
|
|
{ "ARB0_PAR_RDQUEUE_ERROR", 22, 1 },
|
|
{ "CL10_PAR_WRQUEUE_ERROR", 21, 1 },
|
|
{ "CL9_PAR_WRQUEUE_ERROR", 20, 1 },
|
|
{ "CL8_PAR_WRQUEUE_ERROR", 19, 1 },
|
|
{ "CL7_PAR_WRQUEUE_ERROR", 18, 1 },
|
|
{ "CL6_PAR_WRQUEUE_ERROR", 17, 1 },
|
|
{ "CL5_PAR_WRQUEUE_ERROR", 16, 1 },
|
|
{ "CL4_PAR_WRQUEUE_ERROR", 15, 1 },
|
|
{ "CL3_PAR_WRQUEUE_ERROR", 14, 1 },
|
|
{ "CL2_PAR_WRQUEUE_ERROR", 13, 1 },
|
|
{ "CL1_PAR_WRQUEUE_ERROR", 12, 1 },
|
|
{ "CL0_PAR_WRQUEUE_ERROR", 11, 1 },
|
|
{ "CL10_PAR_RDQUEUE_ERROR", 10, 1 },
|
|
{ "CL9_PAR_RDQUEUE_ERROR", 9, 1 },
|
|
{ "CL8_PAR_RDQUEUE_ERROR", 8, 1 },
|
|
{ "CL7_PAR_RDQUEUE_ERROR", 7, 1 },
|
|
{ "CL6_PAR_RDQUEUE_ERROR", 6, 1 },
|
|
{ "CL5_PAR_RDQUEUE_ERROR", 5, 1 },
|
|
{ "CL4_PAR_RDQUEUE_ERROR", 4, 1 },
|
|
{ "CL3_PAR_RDQUEUE_ERROR", 3, 1 },
|
|
{ "CL2_PAR_RDQUEUE_ERROR", 2, 1 },
|
|
{ "CL1_PAR_RDQUEUE_ERROR", 1, 1 },
|
|
{ "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
|
|
{ "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
|
|
{ "BONUS_REG", 6, 26 },
|
|
{ "COHERANCY_CMD_TYPE", 4, 2 },
|
|
{ "COHERANCY_THREAD_NUM", 1, 3 },
|
|
{ "COHERANCY_ENABLE", 0, 1 },
|
|
{ "MA_ERROR_ENABLE", 0x77fc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_edc_0_regs[] = {
|
|
{ "EDC_REF", 0x7900, 0 },
|
|
{ "EDC_INST_NUM", 18, 1 },
|
|
{ "ENABLE_PERF", 17, 1 },
|
|
{ "ECC_BYPASS", 16, 1 },
|
|
{ "RefFreq", 0, 16 },
|
|
{ "EDC_BIST_CMD", 0x7904, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "EDC_BIST_CMD_ADDR", 0x7908, 0 },
|
|
{ "EDC_BIST_CMD_LEN", 0x790c, 0 },
|
|
{ "EDC_BIST_DATA_PATTERN", 0x7910, 0 },
|
|
{ "EDC_BIST_USER_WDATA0", 0x7914, 0 },
|
|
{ "EDC_BIST_USER_WDATA1", 0x7918, 0 },
|
|
{ "EDC_BIST_USER_WDATA2", 0x791c, 0 },
|
|
{ "EDC_BIST_NUM_ERR", 0x7920, 0 },
|
|
{ "EDC_BIST_ERR_FIRST_ADDR", 0x7924, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7928, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x792c, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7930, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7934, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7938, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x793c, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7940, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7944, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7948, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x794c, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7950, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7954, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7958, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x795c, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7960, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7964, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x7968, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x796c, 0 },
|
|
{ "EDC_PAR_ENABLE", 0x7970, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 2, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_INT_ENABLE", 0x7974, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_INT_CAUSE", 0x7978, 0 },
|
|
{ "ECC_UE_PAR_CAUSE", 5, 1 },
|
|
{ "ECC_CE_PAR_CAUSE", 4, 1 },
|
|
{ "PERR_PAR_CAUSE", 3, 1 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "EDC_ECC_STATUS", 0x797c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_edc_1_regs[] = {
|
|
{ "EDC_REF", 0x7980, 0 },
|
|
{ "EDC_INST_NUM", 18, 1 },
|
|
{ "ENABLE_PERF", 17, 1 },
|
|
{ "ECC_BYPASS", 16, 1 },
|
|
{ "RefFreq", 0, 16 },
|
|
{ "EDC_BIST_CMD", 0x7984, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "EDC_BIST_CMD_ADDR", 0x7988, 0 },
|
|
{ "EDC_BIST_CMD_LEN", 0x798c, 0 },
|
|
{ "EDC_BIST_DATA_PATTERN", 0x7990, 0 },
|
|
{ "EDC_BIST_USER_WDATA0", 0x7994, 0 },
|
|
{ "EDC_BIST_USER_WDATA1", 0x7998, 0 },
|
|
{ "EDC_BIST_USER_WDATA2", 0x799c, 0 },
|
|
{ "EDC_BIST_NUM_ERR", 0x79a0, 0 },
|
|
{ "EDC_BIST_ERR_FIRST_ADDR", 0x79a4, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79a8, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79ac, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79b0, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79b4, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79b8, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79bc, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79c0, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79c4, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79c8, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79cc, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79d0, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79d4, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79d8, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79dc, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79e0, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79e4, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79e8, 0 },
|
|
{ "EDC_BIST_STATUS_RDATA", 0x79ec, 0 },
|
|
{ "EDC_PAR_ENABLE", 0x79f0, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 2, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_INT_ENABLE", 0x79f4, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_INT_CAUSE", 0x79f8, 0 },
|
|
{ "ECC_UE_PAR_CAUSE", 5, 1 },
|
|
{ "ECC_CE_PAR_CAUSE", 4, 1 },
|
|
{ "PERR_PAR_CAUSE", 3, 1 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "EDC_ECC_STATUS", 0x79fc, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_hma_regs[] = {
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_cim_regs[] = {
|
|
{ "CIM_BOOT_CFG", 0x7b00, 0 },
|
|
{ "BootAddr", 8, 24 },
|
|
{ "uPGen", 2, 6 },
|
|
{ "BootSdram", 1, 1 },
|
|
{ "uPCRst", 0, 1 },
|
|
{ "CIM_BOOT_LEN", 0x7bf0, 0 },
|
|
{ "BootLen", 4, 28 },
|
|
{ "CIM_FLASH_BASE_ADDR", 0x7b04, 0 },
|
|
{ "FlashBaseAddr", 6, 18 },
|
|
{ "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 },
|
|
{ "FlashAddrSize", 4, 20 },
|
|
{ "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 },
|
|
{ "EEPROMBaseAddr", 6, 18 },
|
|
{ "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 },
|
|
{ "EEPROMAddrSize", 4, 20 },
|
|
{ "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 },
|
|
{ "SdramBaseAddr", 6, 26 },
|
|
{ "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 },
|
|
{ "SdramAddrSize", 4, 28 },
|
|
{ "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 },
|
|
{ "ExtMem2BaseAddr", 6, 26 },
|
|
{ "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 },
|
|
{ "ExtMem2AddrSize", 4, 28 },
|
|
{ "CIM_UP_SPARE_INT", 0x7b24, 0 },
|
|
{ "TDebugInt", 4, 1 },
|
|
{ "BootVecSel", 3, 1 },
|
|
{ "uPSpareInt", 0, 3 },
|
|
{ "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
|
|
{ "TieQOutParErrIntEn", 20, 1 },
|
|
{ "TieQInParErrIntEn", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "Timer1IntEn", 3, 1 },
|
|
{ "Timer0IntEn", 2, 1 },
|
|
{ "PrefDropIntEn", 1, 1 },
|
|
{ "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
|
|
{ "TieQOutParErrInt", 20, 1 },
|
|
{ "TieQInParErrInt", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "Timer1Int", 3, 1 },
|
|
{ "Timer0Int", 2, 1 },
|
|
{ "PrefDropInt", 1, 1 },
|
|
{ "uPAccNonZero", 0, 1 },
|
|
{ "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
|
|
{ "EEPROMWRIntEn", 30, 1 },
|
|
{ "TimeOutMAIntEn", 29, 1 },
|
|
{ "TimeOutIntEn", 28, 1 },
|
|
{ "RspOvrLookupIntEn", 27, 1 },
|
|
{ "ReqOvrLookupIntEn", 26, 1 },
|
|
{ "BlkWrPlIntEn", 25, 1 },
|
|
{ "BlkRdPlIntEn", 24, 1 },
|
|
{ "SglWrPlIntEn", 23, 1 },
|
|
{ "SglRdPlIntEn", 22, 1 },
|
|
{ "BlkWrCtlIntEn", 21, 1 },
|
|
{ "BlkRdCtlIntEn", 20, 1 },
|
|
{ "SglWrCtlIntEn", 19, 1 },
|
|
{ "SglRdCtlIntEn", 18, 1 },
|
|
{ "BlkWrEEPROMIntEn", 17, 1 },
|
|
{ "BlkRdEEPROMIntEn", 16, 1 },
|
|
{ "SglWrEEPROMIntEn", 15, 1 },
|
|
{ "SglRdEEPROMIntEn", 14, 1 },
|
|
{ "BlkWrFlashIntEn", 13, 1 },
|
|
{ "BlkRdFlashIntEn", 12, 1 },
|
|
{ "SglWrFlashIntEn", 11, 1 },
|
|
{ "SglRdFlashIntEn", 10, 1 },
|
|
{ "BlkWrBootIntEn", 9, 1 },
|
|
{ "BlkRdBootIntEn", 8, 1 },
|
|
{ "SglWrBootIntEn", 7, 1 },
|
|
{ "SglRdBootIntEn", 6, 1 },
|
|
{ "IllWrBEIntEn", 5, 1 },
|
|
{ "IllRdBEIntEn", 4, 1 },
|
|
{ "IllRdIntEn", 3, 1 },
|
|
{ "IllWrIntEn", 2, 1 },
|
|
{ "IllTransIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
|
|
{ "EEPROMWRInt", 30, 1 },
|
|
{ "TimeOutMAInt", 29, 1 },
|
|
{ "TimeOutInt", 28, 1 },
|
|
{ "RspOvrLookupInt", 27, 1 },
|
|
{ "ReqOvrLookupInt", 26, 1 },
|
|
{ "BlkWrPlInt", 25, 1 },
|
|
{ "BlkRdPlInt", 24, 1 },
|
|
{ "SglWrPlInt", 23, 1 },
|
|
{ "SglRdPlInt", 22, 1 },
|
|
{ "BlkWrCtlInt", 21, 1 },
|
|
{ "BlkRdCtlInt", 20, 1 },
|
|
{ "SglWrCtlInt", 19, 1 },
|
|
{ "SglRdCtlInt", 18, 1 },
|
|
{ "BlkWrEEPROMInt", 17, 1 },
|
|
{ "BlkRdEEPROMInt", 16, 1 },
|
|
{ "SglWrEEPROMInt", 15, 1 },
|
|
{ "SglRdEEPROMInt", 14, 1 },
|
|
{ "BlkWrFlashInt", 13, 1 },
|
|
{ "BlkRdFlashInt", 12, 1 },
|
|
{ "SglWrFlashInt", 11, 1 },
|
|
{ "SglRdFlashInt", 10, 1 },
|
|
{ "BlkWrBootInt", 9, 1 },
|
|
{ "BlkRdBootInt", 8, 1 },
|
|
{ "SglWrBootInt", 7, 1 },
|
|
{ "SglRdBootInt", 6, 1 },
|
|
{ "IllWrBEInt", 5, 1 },
|
|
{ "IllRdBEInt", 4, 1 },
|
|
{ "IllRdInt", 3, 1 },
|
|
{ "IllWrInt", 2, 1 },
|
|
{ "IllTransInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_UP_INT_ENABLE", 0x7b38, 0 },
|
|
{ "TieQOutParErrIntEn", 20, 1 },
|
|
{ "TieQInParErrIntEn", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "MstPlIntEn", 4, 1 },
|
|
{ "Timer1IntEn", 3, 1 },
|
|
{ "Timer0IntEn", 2, 1 },
|
|
{ "PrefDropIntEn", 1, 1 },
|
|
{ "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
|
|
{ "TieQOutParErrInt", 20, 1 },
|
|
{ "TieQInParErrInt", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "MstPlInt", 4, 1 },
|
|
{ "Timer1Int", 3, 1 },
|
|
{ "Timer0Int", 2, 1 },
|
|
{ "PrefDropInt", 1, 1 },
|
|
{ "uPAccNonZero", 0, 1 },
|
|
{ "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
|
|
{ "EEPROMWRIntEn", 30, 1 },
|
|
{ "TimeOutMAIntEn", 29, 1 },
|
|
{ "TimeOutIntEn", 28, 1 },
|
|
{ "RspOvrLookupIntEn", 27, 1 },
|
|
{ "ReqOvrLookupIntEn", 26, 1 },
|
|
{ "BlkWrPlIntEn", 25, 1 },
|
|
{ "BlkRdPlIntEn", 24, 1 },
|
|
{ "SglWrPlIntEn", 23, 1 },
|
|
{ "SglRdPlIntEn", 22, 1 },
|
|
{ "BlkWrCtlIntEn", 21, 1 },
|
|
{ "BlkRdCtlIntEn", 20, 1 },
|
|
{ "SglWrCtlIntEn", 19, 1 },
|
|
{ "SglRdCtlIntEn", 18, 1 },
|
|
{ "BlkWrEEPROMIntEn", 17, 1 },
|
|
{ "BlkRdEEPROMIntEn", 16, 1 },
|
|
{ "SglWrEEPROMIntEn", 15, 1 },
|
|
{ "SglRdEEPROMIntEn", 14, 1 },
|
|
{ "BlkWrFlashIntEn", 13, 1 },
|
|
{ "BlkRdFlashIntEn", 12, 1 },
|
|
{ "SglWrFlashIntEn", 11, 1 },
|
|
{ "SglRdFlashIntEn", 10, 1 },
|
|
{ "BlkWrBootIntEn", 9, 1 },
|
|
{ "BlkRdBootIntEn", 8, 1 },
|
|
{ "SglWrBootIntEn", 7, 1 },
|
|
{ "SglRdBootIntEn", 6, 1 },
|
|
{ "IllWrBEIntEn", 5, 1 },
|
|
{ "IllRdBEIntEn", 4, 1 },
|
|
{ "IllRdIntEn", 3, 1 },
|
|
{ "IllWrIntEn", 2, 1 },
|
|
{ "IllTransIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
|
|
{ "EEPROMWRInt", 30, 1 },
|
|
{ "TimeOutMAInt", 29, 1 },
|
|
{ "TimeOutInt", 28, 1 },
|
|
{ "RspOvrLookupInt", 27, 1 },
|
|
{ "ReqOvrLookupInt", 26, 1 },
|
|
{ "BlkWrPlInt", 25, 1 },
|
|
{ "BlkRdPlInt", 24, 1 },
|
|
{ "SglWrPlInt", 23, 1 },
|
|
{ "SglRdPlInt", 22, 1 },
|
|
{ "BlkWrCtlInt", 21, 1 },
|
|
{ "BlkRdCtlInt", 20, 1 },
|
|
{ "SglWrCtlInt", 19, 1 },
|
|
{ "SglRdCtlInt", 18, 1 },
|
|
{ "BlkWrEEPROMInt", 17, 1 },
|
|
{ "BlkRdEEPROMInt", 16, 1 },
|
|
{ "SglWrEEPROMInt", 15, 1 },
|
|
{ "SglRdEEPROMInt", 14, 1 },
|
|
{ "BlkWrFlashInt", 13, 1 },
|
|
{ "BlkRdFlashInt", 12, 1 },
|
|
{ "SglWrFlashInt", 11, 1 },
|
|
{ "SglRdFlashInt", 10, 1 },
|
|
{ "BlkWrBootInt", 9, 1 },
|
|
{ "BlkRdBootInt", 8, 1 },
|
|
{ "SglWrBootInt", 7, 1 },
|
|
{ "SglRdBootInt", 6, 1 },
|
|
{ "IllWrBEInt", 5, 1 },
|
|
{ "IllRdBEInt", 4, 1 },
|
|
{ "IllRdInt", 3, 1 },
|
|
{ "IllWrInt", 2, 1 },
|
|
{ "IllTransInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
|
|
{ "OBQSelect", 4, 1 },
|
|
{ "IBQSelect", 3, 1 },
|
|
{ "QueNumSelect", 0, 3 },
|
|
{ "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
|
|
{ "QueSize", 24, 6 },
|
|
{ "QueBase", 16, 6 },
|
|
{ "QueDbg8BEn", 9, 1 },
|
|
{ "QueFullThrsh", 0, 9 },
|
|
{ "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
|
|
{ "HostBusy", 17, 1 },
|
|
{ "HostWrite", 16, 1 },
|
|
{ "HostAddr", 0, 16 },
|
|
{ "CIM_HOST_ACC_DATA", 0x7b54, 0 },
|
|
{ "CIM_CDEBUGDATA", 0x7b58, 0 },
|
|
{ "CDebugDataH", 16, 16 },
|
|
{ "CDebugDataL", 0, 16 },
|
|
{ "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
|
|
{ "IbqDbgAddr", 16, 12 },
|
|
{ "IbqDbgWr", 2, 1 },
|
|
{ "IbqDbgBusy", 1, 1 },
|
|
{ "IbqDbgEn", 0, 1 },
|
|
{ "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
|
|
{ "ObqDbgAddr", 16, 12 },
|
|
{ "ObqDbgWr", 2, 1 },
|
|
{ "ObqDbgBusy", 1, 1 },
|
|
{ "ObqDbgEn", 0, 1 },
|
|
{ "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
|
|
{ "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
|
|
{ "CIM_DEBUGCFG", 0x7b70, 0 },
|
|
{ "POLADbgRdPtr", 23, 9 },
|
|
{ "PILADbgRdPtr", 14, 9 },
|
|
{ "LAMaskTrig", 13, 1 },
|
|
{ "LADbgEn", 12, 1 },
|
|
{ "LAFillOnce", 11, 1 },
|
|
{ "LAMaskStop", 10, 1 },
|
|
{ "DebugSelH", 5, 5 },
|
|
{ "DebugSelL", 0, 5 },
|
|
{ "CIM_DEBUGSTS", 0x7b74, 0 },
|
|
{ "LAReset", 31, 1 },
|
|
{ "POLADbgWrPtr", 16, 9 },
|
|
{ "PILADbgWrPtr", 0, 9 },
|
|
{ "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
|
|
{ "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
|
|
{ "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
|
|
{ "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
|
|
{ "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
|
|
{ "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
|
|
{ "Timer1En", 4, 1 },
|
|
{ "Timer0En", 3, 1 },
|
|
{ "TimerEn", 1, 1 },
|
|
{ "CIM_GLB_TIMER", 0x7bf8, 0 },
|
|
{ "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
|
|
{ "CIM_TIMER0", 0x7c00, 0 },
|
|
{ "CIM_TIMER1", 0x7c04, 0 },
|
|
{ "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
|
|
{ "DAddrTimeOut", 2, 30 },
|
|
{ "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
|
|
{ "DAddrIllegal", 2, 30 },
|
|
{ "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
|
|
{ "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
|
|
{ "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
|
|
{ "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
|
|
{ "CIM_PERR_INJECT", 0x7c20, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "CIM_PERR_ENABLE", 0x7c24, 0 },
|
|
{ "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
|
|
{ "CIM_MA_TIMER_EN", 0x7c2c, 0 },
|
|
{ "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 },
|
|
{ "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
|
|
{ "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_tp_regs[] = {
|
|
{ "TP_IN_CONFIG", 0x7d00, 0 },
|
|
{ "TcpOptParserDisCh3", 27, 1 },
|
|
{ "TcpOptParserDisCh2", 26, 1 },
|
|
{ "TcpOptParserDisCh1", 25, 1 },
|
|
{ "TcpOptParserDisCh0", 24, 1 },
|
|
{ "CrcPassPrt3", 23, 1 },
|
|
{ "CrcPassPrt2", 22, 1 },
|
|
{ "CrcPassPrt1", 21, 1 },
|
|
{ "CrcPassPrt0", 20, 1 },
|
|
{ "VepaMode", 19, 1 },
|
|
{ "FipUpEn", 18, 1 },
|
|
{ "FcoeUpEn", 17, 1 },
|
|
{ "FcoeEnable", 16, 1 },
|
|
{ "IPv6Enable", 15, 1 },
|
|
{ "NICMode", 14, 1 },
|
|
{ "EChecksumCheckTCP", 13, 1 },
|
|
{ "EChecksumCheckIP", 12, 1 },
|
|
{ "EReportUdpHdrLen", 11, 1 },
|
|
{ "ECPL", 10, 1 },
|
|
{ "VnTagEnable", 9, 1 },
|
|
{ "EEthernet", 8, 1 },
|
|
{ "CChecksumCheckTCP", 6, 1 },
|
|
{ "CChecksumCheckIP", 5, 1 },
|
|
{ "CTag", 4, 1 },
|
|
{ "CCPL", 3, 1 },
|
|
{ "CEthernet", 1, 1 },
|
|
{ "CTunnel", 0, 1 },
|
|
{ "TP_OUT_CONFIG", 0x7d04, 0 },
|
|
{ "PortQfcEn", 28, 4 },
|
|
{ "EPktDistChn3", 23, 1 },
|
|
{ "EPktDistChn2", 22, 1 },
|
|
{ "EPktDistChn1", 21, 1 },
|
|
{ "EPktDistChn0", 20, 1 },
|
|
{ "TtlMode", 19, 1 },
|
|
{ "EQfcDmac", 18, 1 },
|
|
{ "ELpbkIncMpsStat", 17, 1 },
|
|
{ "IPIDSplitMode", 16, 1 },
|
|
{ "VLANExtEnablePort3", 15, 1 },
|
|
{ "VLANExtEnablePort2", 14, 1 },
|
|
{ "VLANExtEnablePort1", 13, 1 },
|
|
{ "VLANExtEnablePort0", 12, 1 },
|
|
{ "EChecksumInsertTCP", 11, 1 },
|
|
{ "EChecksumInsertIP", 10, 1 },
|
|
{ "ECPL", 8, 1 },
|
|
{ "EPriority", 7, 1 },
|
|
{ "EEthernet", 6, 1 },
|
|
{ "CChecksumInsertTCP", 5, 1 },
|
|
{ "CChecksumInsertIP", 4, 1 },
|
|
{ "CCPL", 2, 1 },
|
|
{ "CEthernet", 0, 1 },
|
|
{ "TP_GLOBAL_CONFIG", 0x7d08, 0 },
|
|
{ "SYNCookieParams", 26, 6 },
|
|
{ "RXFlowControlDisable", 25, 1 },
|
|
{ "TXPacingEnable", 24, 1 },
|
|
{ "AttackFilterEnable", 23, 1 },
|
|
{ "SYNCookieNoOptions", 22, 1 },
|
|
{ "ProtectedMode", 21, 1 },
|
|
{ "PingDrop", 20, 1 },
|
|
{ "FragmentDrop", 19, 1 },
|
|
{ "FiveTupleLookup", 17, 2 },
|
|
{ "OfdMpsStats", 16, 1 },
|
|
{ "DontFragment", 15, 1 },
|
|
{ "IPIdentSplit", 14, 1 },
|
|
{ "IPChecksumOffload", 13, 1 },
|
|
{ "UDPChecksumOffload", 12, 1 },
|
|
{ "TCPChecksumOffload", 11, 1 },
|
|
{ "RssLoopbackEnable", 10, 1 },
|
|
{ "TCAMServerUse", 8, 2 },
|
|
{ "IPTTL", 0, 8 },
|
|
{ "TP_DB_CONFIG", 0x7d0c, 0 },
|
|
{ "DBMaxOpCnt", 24, 8 },
|
|
{ "CxMaxOpCntDisable", 23, 1 },
|
|
{ "CxMaxOpCnt", 16, 7 },
|
|
{ "TxMaxOpCntDisable", 15, 1 },
|
|
{ "TxMaxOpCnt", 8, 7 },
|
|
{ "RxMaxOpCntDisable", 7, 1 },
|
|
{ "RxMaxOpCnt", 0, 7 },
|
|
{ "TP_CMM_TCB_BASE", 0x7d10, 0 },
|
|
{ "TP_CMM_MM_BASE", 0x7d14, 0 },
|
|
{ "TP_CMM_TIMER_BASE", 0x7d18, 0 },
|
|
{ "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
|
|
{ "RxPoolSize", 16, 16 },
|
|
{ "TxPoolSize", 0, 16 },
|
|
{ "TP_PMM_TX_BASE", 0x7d20, 0 },
|
|
{ "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
|
|
{ "TP_PMM_RX_BASE", 0x7d28, 0 },
|
|
{ "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
|
|
{ "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
|
|
{ "PMRxNumChn", 31, 1 },
|
|
{ "PMRxMaxPage", 0, 21 },
|
|
{ "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
|
|
{ "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
|
|
{ "PMTxNumChn", 30, 2 },
|
|
{ "PMTxMaxPage", 0, 21 },
|
|
{ "TP_TCP_OPTIONS", 0x7d40, 0 },
|
|
{ "MTUDefault", 16, 16 },
|
|
{ "MTUEnable", 10, 1 },
|
|
{ "SACKTx", 9, 1 },
|
|
{ "SACKRx", 8, 1 },
|
|
{ "SACKMode", 4, 2 },
|
|
{ "WindowScaleMode", 2, 2 },
|
|
{ "TimestampsMode", 0, 2 },
|
|
{ "TP_DACK_CONFIG", 0x7d44, 0 },
|
|
{ "AutoState3", 30, 2 },
|
|
{ "AutoState2", 28, 2 },
|
|
{ "AutoState1", 26, 2 },
|
|
{ "ByteThreshold", 8, 18 },
|
|
{ "MSSThreshold", 4, 3 },
|
|
{ "AutoCareful", 2, 1 },
|
|
{ "AutoEnable", 1, 1 },
|
|
{ "Mode", 0, 1 },
|
|
{ "TP_PC_CONFIG", 0x7d48, 0 },
|
|
{ "CMCacheDisable", 31, 1 },
|
|
{ "EnableOcspiFull", 30, 1 },
|
|
{ "EnableFLMErrorDDP", 29, 1 },
|
|
{ "LockTid", 28, 1 },
|
|
{ "DisableInvPend", 27, 1 },
|
|
{ "EnableFilterCount", 26, 1 },
|
|
{ "RddpCongEn", 25, 1 },
|
|
{ "EnableOnFlyPDU", 24, 1 },
|
|
{ "EnableMinRcvWnd", 23, 1 },
|
|
{ "EnableMaxRcvWnd", 22, 1 },
|
|
{ "TxDataAckRateEnable", 21, 1 },
|
|
{ "TxDeferEnable", 20, 1 },
|
|
{ "RxCongestionMode", 19, 1 },
|
|
{ "HearbeatOnceDACK", 18, 1 },
|
|
{ "HearbeatOnceHeap", 17, 1 },
|
|
{ "HearbeatDACK", 16, 1 },
|
|
{ "TxCongestionMode", 15, 1 },
|
|
{ "AcceptLatestRcvAdv", 14, 1 },
|
|
{ "DisableSYNData", 13, 1 },
|
|
{ "DisableWindowPSH", 12, 1 },
|
|
{ "DisableFINOldData", 11, 1 },
|
|
{ "EnableFLMError", 10, 1 },
|
|
{ "EnableOptMtu", 9, 1 },
|
|
{ "FilterPeerFIN", 8, 1 },
|
|
{ "EnableFeedbackSend", 7, 1 },
|
|
{ "EnableRDMAError", 6, 1 },
|
|
{ "EnableDDPFlowControl", 5, 1 },
|
|
{ "DisableHeldFIN", 4, 1 },
|
|
{ "EnableOfdoVLAN", 3, 1 },
|
|
{ "DisableTimeWait", 2, 1 },
|
|
{ "EnableVlanCheck", 1, 1 },
|
|
{ "TxDataAckPageEnable", 0, 1 },
|
|
{ "TP_PC_CONFIG2", 0x7d4c, 0 },
|
|
{ "EnableMtuVfMode", 31, 1 },
|
|
{ "EnableMibVfMode", 30, 1 },
|
|
{ "DisableLbkCheck", 29, 1 },
|
|
{ "EnableUrgDdpOff", 28, 1 },
|
|
{ "EnableFilterLpbk", 27, 1 },
|
|
{ "DisableTblMmgr", 26, 1 },
|
|
{ "CngRecSndNxt", 25, 1 },
|
|
{ "EnableLbkChn", 24, 1 },
|
|
{ "EnableLroEcn", 23, 1 },
|
|
{ "EnablePcmdCheck", 22, 1 },
|
|
{ "EnableELbkAFull", 21, 1 },
|
|
{ "EnableCLbkAFull", 20, 1 },
|
|
{ "EnableOespiFull", 19, 1 },
|
|
{ "DisableHitCheck", 18, 1 },
|
|
{ "EnableRssErrCheck", 17, 1 },
|
|
{ "DisableNewPshFlag", 16, 1 },
|
|
{ "EnableRddpRcvAdvClr", 15, 1 },
|
|
{ "EnableTxDataArpMiss", 14, 1 },
|
|
{ "EnableArpMiss", 13, 1 },
|
|
{ "EnableRstPaws", 12, 1 },
|
|
{ "EnableIPv6RSS", 11, 1 },
|
|
{ "EnableNonOfdHybRss", 10, 1 },
|
|
{ "EnableUDP4TupRss", 9, 1 },
|
|
{ "EnableRxPktTmstpRss", 8, 1 },
|
|
{ "EnableEPCMDAFull", 7, 1 },
|
|
{ "EnableCPCMDAFull", 6, 1 },
|
|
{ "EnableEHdrAFull", 5, 1 },
|
|
{ "EnableCHdrAFull", 4, 1 },
|
|
{ "EnableEMacAFull", 3, 1 },
|
|
{ "EnableNonOfdTidRss", 2, 1 },
|
|
{ "EnableNonOfdTcbRss", 1, 1 },
|
|
{ "EnableTnlOfdClosed", 0, 1 },
|
|
{ "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
|
|
{ "TimerBackoffIndex3", 24, 8 },
|
|
{ "TimerBackoffIndex2", 16, 8 },
|
|
{ "TimerBackoffIndex1", 8, 8 },
|
|
{ "TimerBackoffIndex0", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
|
|
{ "TimerBackoffIndex7", 24, 8 },
|
|
{ "TimerBackoffIndex6", 16, 8 },
|
|
{ "TimerBackoffIndex5", 8, 8 },
|
|
{ "TimerBackoffIndex4", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
|
|
{ "TimerBackoffIndex11", 24, 8 },
|
|
{ "TimerBackoffIndex10", 16, 8 },
|
|
{ "TimerBackoffIndex9", 8, 8 },
|
|
{ "TimerBackoffIndex8", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
|
|
{ "TimerBackoffIndex15", 24, 8 },
|
|
{ "TimerBackoffIndex14", 16, 8 },
|
|
{ "TimerBackoffIndex13", 8, 8 },
|
|
{ "TimerBackoffIndex12", 0, 8 },
|
|
{ "TP_PARA_REG0", 0x7d60, 0 },
|
|
{ "InitCwndIdle", 27, 1 },
|
|
{ "InitCwnd", 24, 3 },
|
|
{ "DupAckThresh", 20, 4 },
|
|
{ "CplErrEnable", 12, 1 },
|
|
{ "FastTnlCnt", 11, 1 },
|
|
{ "FastTblCnt", 10, 1 },
|
|
{ "TpTcamKey", 9, 1 },
|
|
{ "SwsMode", 8, 1 },
|
|
{ "TsmpMode", 6, 2 },
|
|
{ "ByteCountLimit", 4, 2 },
|
|
{ "SwsShove", 3, 1 },
|
|
{ "TblTimer", 2, 1 },
|
|
{ "RxtPace", 1, 1 },
|
|
{ "SwsTimer", 0, 1 },
|
|
{ "TP_PARA_REG1", 0x7d64, 0 },
|
|
{ "InitRwnd", 16, 16 },
|
|
{ "InitialSSThresh", 0, 16 },
|
|
{ "TP_PARA_REG2", 0x7d68, 0 },
|
|
{ "MaxRxData", 16, 16 },
|
|
{ "RxCoalesceSize", 0, 16 },
|
|
{ "TP_PARA_REG3", 0x7d6c, 0 },
|
|
{ "EnableTnlCngLpbk", 31, 1 },
|
|
{ "EnableTnlCngFifo", 30, 1 },
|
|
{ "EnableTnlCngHdr", 29, 1 },
|
|
{ "EnableTnlCngSge", 28, 1 },
|
|
{ "RxMacCheck", 27, 1 },
|
|
{ "RxSynFilter", 26, 1 },
|
|
{ "CngCtrlECN", 25, 1 },
|
|
{ "RxDdpOffInit", 24, 1 },
|
|
{ "TunnelCngDrop3", 23, 1 },
|
|
{ "TunnelCngDrop2", 22, 1 },
|
|
{ "TunnelCngDrop1", 21, 1 },
|
|
{ "TunnelCngDrop0", 20, 1 },
|
|
{ "TxDataAckIdx", 16, 4 },
|
|
{ "RxFragEnable", 12, 3 },
|
|
{ "TxPaceFixedStrict", 11, 1 },
|
|
{ "TxPaceAutoStrict", 10, 1 },
|
|
{ "TxPaceFixed", 9, 1 },
|
|
{ "TxPaceAuto", 8, 1 },
|
|
{ "RxChnTunnel", 7, 1 },
|
|
{ "RxUrgTunnel", 6, 1 },
|
|
{ "RxUrgMode", 5, 1 },
|
|
{ "TxUrgMode", 4, 1 },
|
|
{ "CngCtrlMode", 2, 2 },
|
|
{ "RxCoalesceEnable", 1, 1 },
|
|
{ "RxCoalescePshEn", 0, 1 },
|
|
{ "TP_PARA_REG4", 0x7d70, 0 },
|
|
{ "HighSpeedCfg", 24, 8 },
|
|
{ "NewRenoCfg", 16, 8 },
|
|
{ "TahoeCfg", 8, 8 },
|
|
{ "RenoCfg", 0, 8 },
|
|
{ "TP_PARA_REG5", 0x7d74, 0 },
|
|
{ "IndicateSize", 16, 16 },
|
|
{ "MaxProxySize", 12, 4 },
|
|
{ "EnableReadPdu", 11, 1 },
|
|
{ "EnableReadAhead", 10, 1 },
|
|
{ "EmptyRqEnable", 9, 1 },
|
|
{ "SchdEnable", 8, 1 },
|
|
{ "RearmDdpOffset", 4, 1 },
|
|
{ "ResetDdpOffset", 3, 1 },
|
|
{ "OnFlyDDPEnable", 2, 1 },
|
|
{ "DackTimerSpin", 1, 1 },
|
|
{ "PushTimerEnable", 0, 1 },
|
|
{ "TP_PARA_REG6", 0x7d78, 0 },
|
|
{ "TxPDUSizeAdj", 24, 8 },
|
|
{ "LimitedTransmit", 20, 4 },
|
|
{ "EnableCSav", 19, 1 },
|
|
{ "EnableDeferPDU", 18, 1 },
|
|
{ "EnableFlush", 17, 1 },
|
|
{ "EnableBytePersist", 16, 1 },
|
|
{ "DisableTmoCng", 15, 1 },
|
|
{ "EnableReadAhead", 14, 1 },
|
|
{ "AllowExeption", 13, 1 },
|
|
{ "EnableDeferACK", 12, 1 },
|
|
{ "EnableESnd", 11, 1 },
|
|
{ "EnableCSnd", 10, 1 },
|
|
{ "EnablePDUE", 9, 1 },
|
|
{ "EnablePDUC", 8, 1 },
|
|
{ "EnableBUFI", 7, 1 },
|
|
{ "EnableBUFE", 6, 1 },
|
|
{ "EnableDefer", 5, 1 },
|
|
{ "EnableClearRxmtOos", 4, 1 },
|
|
{ "DisablePDUCng", 3, 1 },
|
|
{ "DisablePDUTimeout", 2, 1 },
|
|
{ "DisablePDURxmt", 1, 1 },
|
|
{ "DisablePDUxmt", 0, 1 },
|
|
{ "TP_PARA_REG7", 0x7d7c, 0 },
|
|
{ "PMMaxXferLen1", 16, 16 },
|
|
{ "PMMaxXferLen0", 0, 16 },
|
|
{ "TP_ENG_CONFIG", 0x7d80, 0 },
|
|
{ "TableLatencyDone", 28, 4 },
|
|
{ "TableLatencyStart", 24, 4 },
|
|
{ "EngineLatencyDelta", 16, 4 },
|
|
{ "EngineLatencyMmgr", 12, 4 },
|
|
{ "EngineLatencyWireIp6", 8, 4 },
|
|
{ "EngineLatencyWire", 4, 4 },
|
|
{ "EngineLatencyBase", 0, 4 },
|
|
{ "TP_ERR_CONFIG", 0x7d8c, 0 },
|
|
{ "TnlErrorPing", 30, 1 },
|
|
{ "TnlErrorCsum", 29, 1 },
|
|
{ "TnlErrorCsumIP", 28, 1 },
|
|
{ "TnlErrorTcpOpt", 25, 1 },
|
|
{ "TnlErrorPktLen", 24, 1 },
|
|
{ "TnlErrorTcpHdrLen", 23, 1 },
|
|
{ "TnlErrorIpHdrLen", 22, 1 },
|
|
{ "TnlErrorEthHdrLen", 21, 1 },
|
|
{ "TnlErrorAttack", 20, 1 },
|
|
{ "TnlErrorFrag", 19, 1 },
|
|
{ "TnlErrorIpVer", 18, 1 },
|
|
{ "TnlErrorMac", 17, 1 },
|
|
{ "TnlErrorAny", 16, 1 },
|
|
{ "DropErrorPing", 14, 1 },
|
|
{ "DropErrorCsum", 13, 1 },
|
|
{ "DropErrorCsumIP", 12, 1 },
|
|
{ "DropErrorTcpOpt", 9, 1 },
|
|
{ "DropErrorPktLen", 8, 1 },
|
|
{ "DropErrorTcpHdrLen", 7, 1 },
|
|
{ "DropErrorIpHdrLen", 6, 1 },
|
|
{ "DropErrorEthHdrLen", 5, 1 },
|
|
{ "DropErrorAttack", 4, 1 },
|
|
{ "DropErrorFrag", 3, 1 },
|
|
{ "DropErrorIpVer", 2, 1 },
|
|
{ "DropErrorMac", 1, 1 },
|
|
{ "DropErrorAny", 0, 1 },
|
|
{ "TP_TIMER_RESOLUTION", 0x7d90, 0 },
|
|
{ "TimerResolution", 16, 8 },
|
|
{ "TimestampResolution", 8, 8 },
|
|
{ "DelayedACKResolution", 0, 8 },
|
|
{ "TP_MSL", 0x7d94, 0 },
|
|
{ "TP_RXT_MIN", 0x7d98, 0 },
|
|
{ "TP_RXT_MAX", 0x7d9c, 0 },
|
|
{ "TP_PERS_MIN", 0x7da0, 0 },
|
|
{ "TP_PERS_MAX", 0x7da4, 0 },
|
|
{ "TP_KEEP_IDLE", 0x7da8, 0 },
|
|
{ "TP_KEEP_INTVL", 0x7dac, 0 },
|
|
{ "TP_INIT_SRTT", 0x7db0, 0 },
|
|
{ "MaxRtt", 16, 16 },
|
|
{ "InitSrtt", 0, 16 },
|
|
{ "TP_DACK_TIMER", 0x7db4, 0 },
|
|
{ "TP_FINWAIT2_TIMER", 0x7db8, 0 },
|
|
{ "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
|
|
{ "TP_SHIFT_CNT", 0x7dc0, 0 },
|
|
{ "SynShiftMax", 24, 8 },
|
|
{ "RxtShiftMaxR1", 20, 4 },
|
|
{ "RxtShiftMaxR2", 16, 4 },
|
|
{ "PerShiftBackoffMax", 12, 4 },
|
|
{ "PerShiftMax", 8, 4 },
|
|
{ "KeepaliveMaxR1", 4, 4 },
|
|
{ "KeepaliveMaxR2", 0, 4 },
|
|
{ "TP_TM_CONFIG", 0x7dc4, 0 },
|
|
{ "TP_TIME_LO", 0x7dc8, 0 },
|
|
{ "TP_TIME_HI", 0x7dcc, 0 },
|
|
{ "TP_PORT_MTU_0", 0x7dd0, 0 },
|
|
{ "Port1MTUValue", 16, 16 },
|
|
{ "Port0MTUValue", 0, 16 },
|
|
{ "TP_PORT_MTU_1", 0x7dd4, 0 },
|
|
{ "Port3MTUValue", 16, 16 },
|
|
{ "Port2MTUValue", 0, 16 },
|
|
{ "TP_PACE_TABLE", 0x7dd8, 0 },
|
|
{ "TP_CCTRL_TABLE", 0x7ddc, 0 },
|
|
{ "RowIndex", 16, 16 },
|
|
{ "RowValue", 0, 16 },
|
|
{ "TP_MTU_TABLE", 0x7de4, 0 },
|
|
{ "MTUIndex", 24, 8 },
|
|
{ "MTUWidth", 16, 4 },
|
|
{ "MTUValue", 0, 14 },
|
|
{ "TP_ULP_TABLE", 0x7de8, 0 },
|
|
{ "ULPType7Field", 28, 4 },
|
|
{ "ULPType6Field", 24, 4 },
|
|
{ "ULPType5Field", 20, 4 },
|
|
{ "ULPType4Field", 16, 4 },
|
|
{ "ULPType3Field", 12, 4 },
|
|
{ "ULPType2Field", 8, 4 },
|
|
{ "ULPType1Field", 4, 4 },
|
|
{ "ULPType0Field", 0, 4 },
|
|
{ "TP_RSS_LKP_TABLE", 0x7dec, 0 },
|
|
{ "LkpTblRowVld", 31, 1 },
|
|
{ "LkpTblRowIdx", 20, 10 },
|
|
{ "LkpTblQueue1", 10, 10 },
|
|
{ "LkpTblQueue0", 0, 10 },
|
|
{ "TP_RSS_CONFIG", 0x7df0, 0 },
|
|
{ "TNL4tupEnIpv6", 31, 1 },
|
|
{ "TNL2tupEnIpv6", 30, 1 },
|
|
{ "TNL4tupEnIpv4", 29, 1 },
|
|
{ "TNL2tupEnIpv4", 28, 1 },
|
|
{ "TNLTcpSel", 27, 1 },
|
|
{ "TNLIp6Sel", 26, 1 },
|
|
{ "TNLVrtSel", 25, 1 },
|
|
{ "TNLMapEn", 24, 1 },
|
|
{ "OFDHashSave", 19, 1 },
|
|
{ "OFDVrtSel", 18, 1 },
|
|
{ "OFDMapEn", 17, 1 },
|
|
{ "OFDLkpEn", 16, 1 },
|
|
{ "SYN4tupEnIpv6", 15, 1 },
|
|
{ "SYN2tupEnIpv6", 14, 1 },
|
|
{ "SYN4tupEnIpv4", 13, 1 },
|
|
{ "SYN2tupEnIpv4", 12, 1 },
|
|
{ "SYNIp6Sel", 11, 1 },
|
|
{ "SYNVrtSel", 10, 1 },
|
|
{ "SYNMapEn", 9, 1 },
|
|
{ "SYNLkpEn", 8, 1 },
|
|
{ "ChannelEnable", 7, 1 },
|
|
{ "PortEnable", 6, 1 },
|
|
{ "TNLAllLookup", 5, 1 },
|
|
{ "VirtEnable", 4, 1 },
|
|
{ "CongestionEnable", 3, 1 },
|
|
{ "HashToeplitz", 2, 1 },
|
|
{ "UdpEnable", 1, 1 },
|
|
{ "Disable", 0, 1 },
|
|
{ "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "MaskFilter", 16, 11 },
|
|
{ "UseWireCh", 0, 1 },
|
|
{ "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "RRCPLMapEn", 20, 1 },
|
|
{ "RRCPLQueWidth", 16, 4 },
|
|
{ "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "UseWireCh", 0, 1 },
|
|
{ "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
|
|
{ "VfRdRg", 25, 1 },
|
|
{ "VfRdEn", 24, 1 },
|
|
{ "VfPerrEn", 23, 1 },
|
|
{ "KeyPerrEn", 22, 1 },
|
|
{ "DisableVlan", 21, 1 },
|
|
{ "EnableUp0", 20, 1 },
|
|
{ "HashDelay", 16, 4 },
|
|
{ "VfWrAddr", 8, 7 },
|
|
{ "KeyMode", 6, 2 },
|
|
{ "VfWrEn", 5, 1 },
|
|
{ "KeyWrEn", 4, 1 },
|
|
{ "KeyWrAddr", 0, 4 },
|
|
{ "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
|
|
{ "ChnCount3", 31, 1 },
|
|
{ "ChnCount2", 30, 1 },
|
|
{ "ChnCount1", 29, 1 },
|
|
{ "ChnCount0", 28, 1 },
|
|
{ "ChnUndFlow3", 27, 1 },
|
|
{ "ChnUndFlow2", 26, 1 },
|
|
{ "ChnUndFlow1", 25, 1 },
|
|
{ "ChnUndFlow0", 24, 1 },
|
|
{ "ChnOvrFlow3", 23, 1 },
|
|
{ "ChnOvrFlow2", 22, 1 },
|
|
{ "ChnOvrFlow1", 21, 1 },
|
|
{ "ChnOvrFlow0", 20, 1 },
|
|
{ "RstChn3", 19, 1 },
|
|
{ "RstChn2", 18, 1 },
|
|
{ "RstChn1", 17, 1 },
|
|
{ "RstChn0", 16, 1 },
|
|
{ "UpdVld", 15, 1 },
|
|
{ "Xoff", 14, 1 },
|
|
{ "UpdChn3", 13, 1 },
|
|
{ "UpdChn2", 12, 1 },
|
|
{ "UpdChn1", 11, 1 },
|
|
{ "UpdChn0", 10, 1 },
|
|
{ "Queue", 0, 10 },
|
|
{ "TP_LA_TABLE_0", 0x7e10, 0 },
|
|
{ "VirtPort1Table", 16, 16 },
|
|
{ "VirtPort0Table", 0, 16 },
|
|
{ "TP_LA_TABLE_1", 0x7e14, 0 },
|
|
{ "VirtPort3Table", 16, 16 },
|
|
{ "VirtPort2Table", 0, 16 },
|
|
{ "TP_TM_PIO_ADDR", 0x7e18, 0 },
|
|
{ "TP_TM_PIO_DATA", 0x7e1c, 0 },
|
|
{ "TP_MOD_CONFIG", 0x7e24, 0 },
|
|
{ "RxChannelWeight1", 24, 8 },
|
|
{ "RXChannelWeight0", 16, 8 },
|
|
{ "TimerMode", 8, 8 },
|
|
{ "TxChannelXoffEn", 0, 4 },
|
|
{ "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
|
|
{ "RX_MOD_WEIGHT", 24, 8 },
|
|
{ "TX_MOD_WEIGHT", 16, 8 },
|
|
{ "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
|
|
{ "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
|
|
{ "RX_MOD_RATE_LIMIT_INC", 24, 8 },
|
|
{ "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_INC", 8, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
|
|
{ "TP_PIO_ADDR", 0x7e40, 0 },
|
|
{ "TP_PIO_DATA", 0x7e44, 0 },
|
|
{ "TP_RESET", 0x7e4c, 0 },
|
|
{ "FlstInitEnable", 1, 1 },
|
|
{ "TPReset", 0, 1 },
|
|
{ "TP_MIB_INDEX", 0x7e50, 0 },
|
|
{ "TP_MIB_DATA", 0x7e54, 0 },
|
|
{ "TP_SYNC_TIME_HI", 0x7e58, 0 },
|
|
{ "TP_SYNC_TIME_LO", 0x7e5c, 0 },
|
|
{ "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
|
|
{ "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
|
|
{ "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
|
|
{ "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
|
|
{ "TP_INT_ENABLE", 0x7e70, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutTcpFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "CmOpExtFifoPerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_INT_CAUSE", 0x7e74, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutTcpFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "CmOpExtFifoPerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_PER_ENABLE", 0x7e78, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutTcpFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "CmOpExtFifoPerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
|
|
{ "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
|
|
{ "FreeRxPageChn", 28, 1 },
|
|
{ "FreeRxPageCount", 0, 21 },
|
|
{ "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
|
|
{ "FreeTxPageChn", 28, 2 },
|
|
{ "FreeTxPageCount", 0, 21 },
|
|
{ "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
|
|
{ "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
|
|
{ "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
|
|
{ "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
|
|
{ "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
|
|
{ "TP_MOD_POP_CNT", 0x7ea0, 0 },
|
|
{ "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
|
|
{ "TimerSeparator", 16, 16 },
|
|
{ "DisableTimeFreeze", 0, 1 },
|
|
{ "TP_DEBUG_FLAGS", 0x7eac, 0 },
|
|
{ "RxTimerDackFirst", 26, 1 },
|
|
{ "RxTimerDack", 25, 1 },
|
|
{ "RxTimerHeartbeat", 24, 1 },
|
|
{ "RxPawsDrop", 23, 1 },
|
|
{ "RxUrgDataDrop", 22, 1 },
|
|
{ "RxFutureData", 21, 1 },
|
|
{ "RxRcvRxmData", 20, 1 },
|
|
{ "RxRcvOooDataFin", 19, 1 },
|
|
{ "RxRcvOooData", 18, 1 },
|
|
{ "RxRcvWndZero", 17, 1 },
|
|
{ "RxRcvWndLtMss", 16, 1 },
|
|
{ "TxDupAckInc", 11, 1 },
|
|
{ "TxRxmUrg", 10, 1 },
|
|
{ "TxRxmFin", 9, 1 },
|
|
{ "TxRxmSyn", 8, 1 },
|
|
{ "TxRxmNewReno", 7, 1 },
|
|
{ "TxRxmFast", 6, 1 },
|
|
{ "TxRxmTimer", 5, 1 },
|
|
{ "TxRxmTimerKeepalive", 4, 1 },
|
|
{ "TxRxmTimerPersist", 3, 1 },
|
|
{ "TxRcvAdvShrunk", 2, 1 },
|
|
{ "TxRcvAdvZero", 1, 1 },
|
|
{ "TxRcvAdvLtMss", 0, 1 },
|
|
{ "TP_RX_SCHED", 0x7eb0, 0 },
|
|
{ "CommitReset1", 31, 1 },
|
|
{ "CommitReset0", 30, 1 },
|
|
{ "ForceCong1", 29, 1 },
|
|
{ "ForceCong0", 28, 1 },
|
|
{ "EnableLpbkFull1", 26, 2 },
|
|
{ "EnableLpbkFull0", 24, 2 },
|
|
{ "EnableFifoFull1", 22, 2 },
|
|
{ "EnablePcmdFull1", 20, 2 },
|
|
{ "EnableHdrFull1", 18, 2 },
|
|
{ "EnableFifoFull0", 16, 2 },
|
|
{ "EnablePcmdFull0", 14, 2 },
|
|
{ "EnableHdrFull0", 12, 2 },
|
|
{ "CommitLimit1", 6, 6 },
|
|
{ "CommitLimit0", 0, 6 },
|
|
{ "TP_TX_SCHED", 0x7eb4, 0 },
|
|
{ "CommitReset3", 31, 1 },
|
|
{ "CommitReset2", 30, 1 },
|
|
{ "CommitReset1", 29, 1 },
|
|
{ "CommitReset0", 28, 1 },
|
|
{ "ForceCong3", 27, 1 },
|
|
{ "ForceCong2", 26, 1 },
|
|
{ "ForceCong1", 25, 1 },
|
|
{ "ForceCong0", 24, 1 },
|
|
{ "CommitLimit3", 18, 6 },
|
|
{ "CommitLimit2", 12, 6 },
|
|
{ "CommitLimit1", 6, 6 },
|
|
{ "CommitLimit0", 0, 6 },
|
|
{ "TP_FX_SCHED", 0x7eb8, 0 },
|
|
{ "TxChnXoff3", 19, 1 },
|
|
{ "TxChnXoff2", 18, 1 },
|
|
{ "TxChnXoff1", 17, 1 },
|
|
{ "TxChnXoff0", 16, 1 },
|
|
{ "TxModXoff7", 15, 1 },
|
|
{ "TxModXoff6", 14, 1 },
|
|
{ "TxModXoff5", 13, 1 },
|
|
{ "TxModXoff4", 12, 1 },
|
|
{ "TxModXoff3", 11, 1 },
|
|
{ "TxModXoff2", 10, 1 },
|
|
{ "TxModXoff1", 9, 1 },
|
|
{ "TxModXoff0", 8, 1 },
|
|
{ "RxChnXoff3", 7, 1 },
|
|
{ "RxChnXoff2", 6, 1 },
|
|
{ "RxChnXoff1", 5, 1 },
|
|
{ "RxChnXoff0", 4, 1 },
|
|
{ "RxModXoff1", 1, 1 },
|
|
{ "RxModXoff0", 0, 1 },
|
|
{ "TP_TX_ORATE", 0x7ebc, 0 },
|
|
{ "OfdRate3", 24, 8 },
|
|
{ "OfdRate2", 16, 8 },
|
|
{ "OfdRate1", 8, 8 },
|
|
{ "OfdRate0", 0, 8 },
|
|
{ "TP_IX_SCHED0", 0x7ec0, 0 },
|
|
{ "TP_IX_SCHED1", 0x7ec4, 0 },
|
|
{ "TP_IX_SCHED2", 0x7ec8, 0 },
|
|
{ "TP_IX_SCHED3", 0x7ecc, 0 },
|
|
{ "TP_TX_TRATE", 0x7ed0, 0 },
|
|
{ "TnlRate3", 24, 8 },
|
|
{ "TnlRate2", 16, 8 },
|
|
{ "TnlRate1", 8, 8 },
|
|
{ "TnlRate0", 0, 8 },
|
|
{ "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
|
|
{ "DbgLaOpcEnable", 24, 8 },
|
|
{ "DbgLaWhlf", 23, 1 },
|
|
{ "DbgLaWptr", 16, 7 },
|
|
{ "DbgLaMode", 14, 2 },
|
|
{ "DbgLaFatalFreeze", 13, 1 },
|
|
{ "DbgLaEnable", 12, 1 },
|
|
{ "DbgLaRptr", 0, 7 },
|
|
{ "TP_DBG_LA_DATAL", 0x7ed8, 0 },
|
|
{ "TP_DBG_LA_DATAH", 0x7edc, 0 },
|
|
{ "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
|
|
{ "WriteEnable", 31, 1 },
|
|
{ "TcamEnable", 10, 1 },
|
|
{ "BlockSelect", 8, 2 },
|
|
{ "LineAddress", 1, 7 },
|
|
{ "RequestDone", 0, 1 },
|
|
{ "TP_PROTOCOL_DATA0", 0x7eec, 0 },
|
|
{ "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
|
|
{ "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
|
|
{ "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
|
|
{ "TP_PROTOCOL_DATA4", 0x7efc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_ulp_tx_regs[] = {
|
|
{ "ULP_TX_CONFIG", 0x8dc0, 0 },
|
|
{ "stag_mix_enable", 2, 1 },
|
|
{ "stagf_fix_disable", 1, 1 },
|
|
{ "extra_tag_insertion_enable", 0, 1 },
|
|
{ "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_TX_INT_ENABLE", 0x8dc8, 0 },
|
|
{ "Pbl_bound_err_ch3", 31, 1 },
|
|
{ "Pbl_bound_err_ch2", 30, 1 },
|
|
{ "Pbl_bound_err_ch1", 29, 1 },
|
|
{ "Pbl_bound_err_ch0", 28, 1 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "imm_data_perr_set_ch3", 3, 1 },
|
|
{ "imm_data_perr_set_ch2", 2, 1 },
|
|
{ "imm_data_perr_set_ch1", 1, 1 },
|
|
{ "imm_data_perr_set_ch0", 0, 1 },
|
|
{ "ULP_TX_INT_CAUSE", 0x8dcc, 0 },
|
|
{ "Pbl_bound_err_ch3", 31, 1 },
|
|
{ "Pbl_bound_err_ch2", 30, 1 },
|
|
{ "Pbl_bound_err_ch1", 29, 1 },
|
|
{ "Pbl_bound_err_ch0", 28, 1 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "imm_data_perr_set_ch3", 3, 1 },
|
|
{ "imm_data_perr_set_ch2", 2, 1 },
|
|
{ "imm_data_perr_set_ch1", 1, 1 },
|
|
{ "imm_data_perr_set_ch0", 0, 1 },
|
|
{ "ULP_TX_PERR_ENABLE", 0x8dd0, 0 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "imm_data_perr_set_ch3", 3, 1 },
|
|
{ "imm_data_perr_set_ch2", 2, 1 },
|
|
{ "imm_data_perr_set_ch1", 1, 1 },
|
|
{ "imm_data_perr_set_ch0", 0, 1 },
|
|
{ "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
|
|
{ "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
|
|
{ "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
|
|
{ "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
|
|
{ "ULP_TX_CPL_ERR_OFFSET", 0x8de4, 0 },
|
|
{ "ULP_TX_CPL_ERR_MASK_L", 0x8de8, 0 },
|
|
{ "ULP_TX_CPL_ERR_MASK_H", 0x8dec, 0 },
|
|
{ "ULP_TX_CPL_ERR_VALUE_L", 0x8df0, 0 },
|
|
{ "ULP_TX_CPL_ERR_VALUE_H", 0x8df4, 0 },
|
|
{ "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
|
|
{ "Ch3Size1", 24, 8 },
|
|
{ "Ch2Size1", 16, 8 },
|
|
{ "Ch1Size1", 8, 8 },
|
|
{ "Ch0Size1", 0, 8 },
|
|
{ "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
|
|
{ "Ch3Size2", 24, 8 },
|
|
{ "Ch2Size2", 16, 8 },
|
|
{ "Ch1Size2", 8, 8 },
|
|
{ "Ch0Size2", 0, 8 },
|
|
{ "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
|
|
{ "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
|
|
{ "ULP_TX_ULP2TP_BIST_CMD", 0x8e30, 0 },
|
|
{ "ULP_TX_ULP2TP_BIST_ERROR_CNT", 0x8e34, 0 },
|
|
{ "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 },
|
|
{ "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_1", 0x8e40, 0 },
|
|
{ "ULP_TX_FPGA_CMD_2", 0x8e44, 0 },
|
|
{ "ULP_TX_FPGA_CMD_3", 0x8e48, 0 },
|
|
{ "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_5", 0x8e50, 0 },
|
|
{ "ULP_TX_FPGA_CMD_6", 0x8e54, 0 },
|
|
{ "ULP_TX_FPGA_CMD_7", 0x8e58, 0 },
|
|
{ "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_9", 0x8e60, 0 },
|
|
{ "ULP_TX_FPGA_CMD_10", 0x8e64, 0 },
|
|
{ "ULP_TX_FPGA_CMD_11", 0x8e68, 0 },
|
|
{ "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_13", 0x8e70, 0 },
|
|
{ "ULP_TX_FPGA_CMD_14", 0x8e74, 0 },
|
|
{ "ULP_TX_FPGA_CMD_15", 0x8e78, 0 },
|
|
{ "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
|
|
{ "ERR_CH3", 12, 4 },
|
|
{ "ERR_CH2", 8, 4 },
|
|
{ "ERR_CH1", 4, 4 },
|
|
{ "ERR_CH0", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
|
|
{ "CLR_DROP", 16, 4 },
|
|
{ "CLR_CH3", 12, 4 },
|
|
{ "CLR_CH2", 8, 4 },
|
|
{ "CLR_CH1", 4, 4 },
|
|
{ "CLR_CH0", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_DROP_CNT", 0x8eb8, 0 },
|
|
{ "DROP_CH3", 12, 4 },
|
|
{ "DROP_CH2", 8, 4 },
|
|
{ "DROP_CH1", 4, 4 },
|
|
{ "DROP_CH0", 0, 4 },
|
|
{ "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_1", 0x8edc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_2", 0x8eec, 0 },
|
|
{ "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_3", 0x8efc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_4", 0x8f00, 0 },
|
|
{ "ULP_TX_LA_RDDATA_4", 0x8f04, 0 },
|
|
{ "ULP_TX_LA_WRPTR_4", 0x8f08, 0 },
|
|
{ "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_5", 0x8f10, 0 },
|
|
{ "ULP_TX_LA_RDDATA_5", 0x8f14, 0 },
|
|
{ "ULP_TX_LA_WRPTR_5", 0x8f18, 0 },
|
|
{ "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_6", 0x8f20, 0 },
|
|
{ "ULP_TX_LA_RDDATA_6", 0x8f24, 0 },
|
|
{ "ULP_TX_LA_WRPTR_6", 0x8f28, 0 },
|
|
{ "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_7", 0x8f30, 0 },
|
|
{ "ULP_TX_LA_RDDATA_7", 0x8f34, 0 },
|
|
{ "ULP_TX_LA_WRPTR_7", 0x8f38, 0 },
|
|
{ "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_8", 0x8f40, 0 },
|
|
{ "ULP_TX_LA_RDDATA_8", 0x8f44, 0 },
|
|
{ "ULP_TX_LA_WRPTR_8", 0x8f48, 0 },
|
|
{ "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_9", 0x8f50, 0 },
|
|
{ "ULP_TX_LA_RDDATA_9", 0x8f54, 0 },
|
|
{ "ULP_TX_LA_WRPTR_9", 0x8f58, 0 },
|
|
{ "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_10", 0x8f60, 0 },
|
|
{ "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
|
|
{ "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
|
|
{ "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_pm_rx_regs[] = {
|
|
{ "PM_RX_CFG", 0x8fc0, 0 },
|
|
{ "ch1_output", 27, 5 },
|
|
{ "strobe1", 16, 1 },
|
|
{ "ch1_input", 11, 5 },
|
|
{ "ch2_input", 6, 5 },
|
|
{ "ch3_input", 1, 5 },
|
|
{ "strobe0", 0, 1 },
|
|
{ "PM_RX_MODE", 0x8fc4, 0 },
|
|
{ "use_bundle_len", 4, 1 },
|
|
{ "stat_to_ch", 3, 1 },
|
|
{ "stat_from_ch", 1, 2 },
|
|
{ "prefetch_enable", 0, 1 },
|
|
{ "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
|
|
{ "PM_RX_STAT_COUNT", 0x8fcc, 0 },
|
|
{ "PM_RX_STAT_LSB", 0x8fd0, 0 },
|
|
{ "PM_RX_STAT_MSB", 0x8fd4, 0 },
|
|
{ "PM_RX_INT_ENABLE", 0x8fd8, 0 },
|
|
{ "zero_e_cmd_error", 22, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
|
|
{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
|
|
{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
|
|
{ "iespi0_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_Rx_framing_error", 16, 1 },
|
|
{ "iespi2_Rx_framing_error", 15, 1 },
|
|
{ "iespi3_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "iespi2_Tx_framing_error", 11, 1 },
|
|
{ "iespi3_Tx_framing_error", 10, 1 },
|
|
{ "ocspi0_Rx_framing_error", 9, 1 },
|
|
{ "ocspi1_Rx_framing_error", 8, 1 },
|
|
{ "ocspi0_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_Tx_framing_error", 6, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ocspi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "iespi_par_error", 1, 1 },
|
|
{ "e_pcmd_par_error", 0, 1 },
|
|
{ "PM_RX_INT_CAUSE", 0x8fdc, 0 },
|
|
{ "zero_e_cmd_error", 22, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
|
|
{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
|
|
{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
|
|
{ "iespi0_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_Rx_framing_error", 16, 1 },
|
|
{ "iespi2_Rx_framing_error", 15, 1 },
|
|
{ "iespi3_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "iespi2_Tx_framing_error", 11, 1 },
|
|
{ "iespi3_Tx_framing_error", 10, 1 },
|
|
{ "ocspi0_Rx_framing_error", 9, 1 },
|
|
{ "ocspi1_Rx_framing_error", 8, 1 },
|
|
{ "ocspi0_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_Tx_framing_error", 6, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ocspi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "iespi_par_error", 1, 1 },
|
|
{ "e_pcmd_par_error", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_pm_tx_regs[] = {
|
|
{ "PM_TX_CFG", 0x8fe0, 0 },
|
|
{ "ch1_output", 27, 5 },
|
|
{ "ch2_output", 22, 5 },
|
|
{ "ch3_output", 17, 5 },
|
|
{ "strobe1", 16, 1 },
|
|
{ "ch1_input", 11, 5 },
|
|
{ "ch2_input", 6, 5 },
|
|
{ "ch3_input", 1, 5 },
|
|
{ "strobe0", 0, 1 },
|
|
{ "PM_TX_MODE", 0x8fe4, 0 },
|
|
{ "cong_thresh3", 25, 7 },
|
|
{ "cong_thresh2", 18, 7 },
|
|
{ "cong_thresh1", 11, 7 },
|
|
{ "cong_thresh0", 4, 7 },
|
|
{ "use_bundle_len", 3, 1 },
|
|
{ "stat_channel", 1, 2 },
|
|
{ "prefetch_enable", 0, 1 },
|
|
{ "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
|
|
{ "PM_TX_STAT_COUNT", 0x8fec, 0 },
|
|
{ "PM_TX_STAT_LSB", 0x8ff0, 0 },
|
|
{ "PM_TX_STAT_MSB", 0x8ff4, 0 },
|
|
{ "PM_TX_INT_ENABLE", 0x8ff8, 0 },
|
|
{ "pcmd_len_ovfl0", 31, 1 },
|
|
{ "pcmd_len_ovfl1", 30, 1 },
|
|
{ "pcmd_len_ovfl2", 29, 1 },
|
|
{ "zero_c_cmd_erro", 28, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 27, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 26, 1 },
|
|
{ "icspi2_fifo2x_Rx_framing_error", 25, 1 },
|
|
{ "icspi3_fifo2x_Rx_framing_error", 24, 1 },
|
|
{ "icspi0_Rx_framing_error", 23, 1 },
|
|
{ "icspi1_Rx_framing_error", 22, 1 },
|
|
{ "icspi2_Rx_framing_error", 21, 1 },
|
|
{ "icspi3_Rx_framing_error", 20, 1 },
|
|
{ "icspi0_Tx_framing_error", 19, 1 },
|
|
{ "icspi1_Tx_framing_error", 18, 1 },
|
|
{ "icspi2_Tx_framing_error", 17, 1 },
|
|
{ "icspi3_Tx_framing_error", 16, 1 },
|
|
{ "oespi0_Rx_framing_error", 15, 1 },
|
|
{ "oespi1_Rx_framing_error", 14, 1 },
|
|
{ "oespi2_Rx_framing_error", 13, 1 },
|
|
{ "oespi3_Rx_framing_error", 12, 1 },
|
|
{ "oespi0_Tx_framing_error", 11, 1 },
|
|
{ "oespi1_Tx_framing_error", 10, 1 },
|
|
{ "oespi2_Tx_framing_error", 9, 1 },
|
|
{ "oespi3_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "oespi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "icspi_par_error", 1, 1 },
|
|
{ "c_pcmd_par_error", 0, 1 },
|
|
{ "PM_TX_INT_CAUSE", 0x8ffc, 0 },
|
|
{ "pcmd_len_ovfl0", 31, 1 },
|
|
{ "pcmd_len_ovfl1", 30, 1 },
|
|
{ "pcmd_len_ovfl2", 29, 1 },
|
|
{ "zero_c_cmd_error", 28, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 27, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 26, 1 },
|
|
{ "icspi2_fifo2x_Rx_framing_error", 25, 1 },
|
|
{ "icspi3_fifo2x_Rx_framing_error", 24, 1 },
|
|
{ "icspi0_Rx_framing_error", 23, 1 },
|
|
{ "icspi1_Rx_framing_error", 22, 1 },
|
|
{ "icspi2_Rx_framing_error", 21, 1 },
|
|
{ "icspi3_Rx_framing_error", 20, 1 },
|
|
{ "icspi0_Tx_framing_error", 19, 1 },
|
|
{ "icspi1_Tx_framing_error", 18, 1 },
|
|
{ "icspi2_Tx_framing_error", 17, 1 },
|
|
{ "icspi3_Tx_framing_error", 16, 1 },
|
|
{ "oespi0_Rx_framing_error", 15, 1 },
|
|
{ "oespi1_Rx_framing_error", 14, 1 },
|
|
{ "oespi2_Rx_framing_error", 13, 1 },
|
|
{ "oespi3_Rx_framing_error", 12, 1 },
|
|
{ "oespi0_Tx_framing_error", 11, 1 },
|
|
{ "oespi1_Tx_framing_error", 10, 1 },
|
|
{ "oespi2_Tx_framing_error", 9, 1 },
|
|
{ "oespi3_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "oespi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "icspi_par_error", 1, 1 },
|
|
{ "c_pcmd_par_error", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_mps_regs[] = {
|
|
{ "MPS_CMN_CTL", 0x9000, 0 },
|
|
{ "Detect8023", 3, 1 },
|
|
{ "VFDirectAccess", 2, 1 },
|
|
{ "NumPorts", 0, 2 },
|
|
{ "MPS_INT_ENABLE", 0x9004, 0 },
|
|
{ "StatIntEnb", 5, 1 },
|
|
{ "TxIntEnb", 4, 1 },
|
|
{ "RxIntEnb", 3, 1 },
|
|
{ "TrcIntEnb", 2, 1 },
|
|
{ "ClsIntEnb", 1, 1 },
|
|
{ "PLIntEnb", 0, 1 },
|
|
{ "MPS_INT_CAUSE", 0x9008, 0 },
|
|
{ "StatInt", 5, 1 },
|
|
{ "TxInt", 4, 1 },
|
|
{ "RxInt", 3, 1 },
|
|
{ "TrcInt", 2, 1 },
|
|
{ "ClsInt", 1, 1 },
|
|
{ "PLInt", 0, 1 },
|
|
{ "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
|
|
{ "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
|
|
{ "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
|
|
{ "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
|
|
{ "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
|
|
{ "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
|
|
{ "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
|
|
{ "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
|
|
{ "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
|
|
{ "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
|
|
{ "MPS_WOL_CTL_MODE", 0x9058, 0 },
|
|
{ "MPS_FPGA_DEBUG", 0x9060, 0 },
|
|
{ "LPBK_EN", 8, 1 },
|
|
{ "CH_MAP3", 6, 2 },
|
|
{ "CH_MAP2", 4, 2 },
|
|
{ "CH_MAP1", 2, 2 },
|
|
{ "CH_MAP0", 0, 2 },
|
|
{ "MPS_DEBUG_CTL", 0x9068, 0 },
|
|
{ "DbgModeCtl_H", 11, 1 },
|
|
{ "DbgSel_H", 6, 5 },
|
|
{ "DbgModeCtl_L", 5, 1 },
|
|
{ "DbgSel_L", 0, 5 },
|
|
{ "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
|
|
{ "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
|
|
{ "MPS_TOP_SPARE", 0x9074, 0 },
|
|
{ "TopSpare", 8, 24 },
|
|
{ "oVlanSelLpbk3", 7, 1 },
|
|
{ "oVlanSelLpbk2", 6, 1 },
|
|
{ "oVlanSelLpbk1", 5, 1 },
|
|
{ "oVlanSelLpbk0", 4, 1 },
|
|
{ "oVlanSelMac3", 3, 1 },
|
|
{ "oVlanSelMac2", 2, 1 },
|
|
{ "oVlanSelMac1", 1, 1 },
|
|
{ "oVlanSelMac0", 0, 1 },
|
|
{ "MPS_BUILD_REVISION", 0x90fc, 0 },
|
|
{ "MPS_PORT_CTL", 0x20000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x20004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x20008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x2000c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x20010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x20014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x20018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x2001c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x20020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x20024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x20028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x2002c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_CTL", 0x22000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x22004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x22008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x2200c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x22010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x22014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x22018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x2201c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x22020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x22024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x22028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x2202c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_CTL", 0x24000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x24004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x24008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x2400c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x24010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x24014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x24018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x2401c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x24020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x24024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x24028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x2402c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_CTL", 0x26000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x26004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x26008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x2600c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x26010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x26014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x26018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x2601c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x26020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x26024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x26028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x2602c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PF_CTL", 0x1e2c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1e6c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1eac0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1eec0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1f2c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1f6c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1fac0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1fec0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_RX_CTL", 0x11000, 0 },
|
|
{ "FILT_VLAN_SEL", 17, 1 },
|
|
{ "CBA_EN", 16, 1 },
|
|
{ "BLK_SNDR", 12, 4 },
|
|
{ "CMPRS", 8, 4 },
|
|
{ "SNF", 0, 8 },
|
|
{ "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
|
|
{ "CTL_P3", 12, 4 },
|
|
{ "CTL_P2", 8, 4 },
|
|
{ "CTL_P1", 4, 4 },
|
|
{ "CTL_P0", 0, 4 },
|
|
{ "MPS_RX_PG_FL", 0x11008, 0 },
|
|
{ "RST", 16, 1 },
|
|
{ "CNT", 0, 16 },
|
|
{ "MPS_RX_PKT_FL", 0x1100c, 0 },
|
|
{ "RST", 16, 1 },
|
|
{ "CNT", 0, 16 },
|
|
{ "MPS_RX_PG_RSV0", 0x11010, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV1", 0x11014, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV2", 0x11018, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV3", 0x1101c, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV4", 0x11020, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV5", 0x11024, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV6", 0x11028, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_RSV7", 0x1102c, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 11 },
|
|
{ "ALLOC", 0, 11 },
|
|
{ "MPS_RX_PG_SHR_BG0", 0x11030, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 11 },
|
|
{ "BORW", 0, 11 },
|
|
{ "MPS_RX_PG_SHR_BG1", 0x11034, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 11 },
|
|
{ "BORW", 0, 11 },
|
|
{ "MPS_RX_PG_SHR_BG2", 0x11038, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 11 },
|
|
{ "BORW", 0, 11 },
|
|
{ "MPS_RX_PG_SHR_BG3", 0x1103c, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 11 },
|
|
{ "BORW", 0, 11 },
|
|
{ "MPS_RX_PG_SHR0", 0x11040, 0 },
|
|
{ "QUOTA", 16, 11 },
|
|
{ "USED", 0, 11 },
|
|
{ "MPS_RX_PG_SHR1", 0x11044, 0 },
|
|
{ "QUOTA", 16, 11 },
|
|
{ "USED", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 11 },
|
|
{ "MPS_RX_OCH_CTL", 0x11058, 0 },
|
|
{ "DROP_WT", 27, 5 },
|
|
{ "TRUNC_WT", 22, 5 },
|
|
{ "DRAIN", 13, 5 },
|
|
{ "DROP", 8, 5 },
|
|
{ "STOP", 0, 5 },
|
|
{ "MPS_RX_LPBK_BP0", 0x1105c, 0 },
|
|
{ "MPS_RX_LPBK_BP1", 0x11060, 0 },
|
|
{ "MPS_RX_LPBK_BP2", 0x11064, 0 },
|
|
{ "MPS_RX_LPBK_BP3", 0x11068, 0 },
|
|
{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
|
|
{ "MPS_RX_CHMN_CNT", 0x11070, 0 },
|
|
{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
|
|
{ "FF", 23, 1 },
|
|
{ "PGMO", 22, 1 },
|
|
{ "PGME", 21, 1 },
|
|
{ "CHMN", 20, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PSMX", 17, 1 },
|
|
{ "PGLL", 16, 1 },
|
|
{ "PGFL", 15, 1 },
|
|
{ "PKTQ", 14, 1 },
|
|
{ "PKFL", 13, 1 },
|
|
{ "PPM3", 12, 1 },
|
|
{ "PPM2", 11, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "SPMX", 8, 1 },
|
|
{ "CDL3", 7, 1 },
|
|
{ "CDL2", 6, 1 },
|
|
{ "CDL1", 5, 1 },
|
|
{ "CDL0", 4, 1 },
|
|
{ "CDM3", 3, 1 },
|
|
{ "CDM2", 2, 1 },
|
|
{ "CDM1", 1, 1 },
|
|
{ "CDM0", 0, 1 },
|
|
{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
|
|
{ "FF", 23, 1 },
|
|
{ "PGMO", 22, 1 },
|
|
{ "PGME", 21, 1 },
|
|
{ "CHMN", 20, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PSMX", 17, 1 },
|
|
{ "PGLL", 16, 1 },
|
|
{ "PGFL", 15, 1 },
|
|
{ "PKTQ", 14, 1 },
|
|
{ "PKFL", 13, 1 },
|
|
{ "PPM3", 12, 1 },
|
|
{ "PPM2", 11, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "SPMX", 8, 1 },
|
|
{ "CDL3", 7, 1 },
|
|
{ "CDL2", 6, 1 },
|
|
{ "CDL1", 5, 1 },
|
|
{ "CDL0", 4, 1 },
|
|
{ "CDM3", 3, 1 },
|
|
{ "CDM2", 2, 1 },
|
|
{ "CDM1", 1, 1 },
|
|
{ "CDM0", 0, 1 },
|
|
{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
|
|
{ "FF", 23, 1 },
|
|
{ "PGMO", 22, 1 },
|
|
{ "PGME", 21, 1 },
|
|
{ "CHMN", 20, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PSMX", 17, 1 },
|
|
{ "PGLL", 16, 1 },
|
|
{ "PGFL", 15, 1 },
|
|
{ "PKTQ", 14, 1 },
|
|
{ "PKFL", 13, 1 },
|
|
{ "PPM3", 12, 1 },
|
|
{ "PPM2", 11, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "SPMX", 8, 1 },
|
|
{ "CDL3", 7, 1 },
|
|
{ "CDL2", 6, 1 },
|
|
{ "CDL1", 5, 1 },
|
|
{ "CDL0", 4, 1 },
|
|
{ "CDM3", 3, 1 },
|
|
{ "CDM2", 2, 1 },
|
|
{ "CDM1", 1, 1 },
|
|
{ "CDM0", 0, 1 },
|
|
{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
|
|
{ "INT_ERR_INT", 8, 5 },
|
|
{ "PG_TH_INT7", 7, 1 },
|
|
{ "PG_TH_INT6", 6, 1 },
|
|
{ "PG_TH_INT5", 5, 1 },
|
|
{ "PG_TH_INT4", 4, 1 },
|
|
{ "PG_TH_INT3", 3, 1 },
|
|
{ "PG_TH_INT2", 2, 1 },
|
|
{ "PG_TH_INT1", 1, 1 },
|
|
{ "PG_TH_INT0", 0, 1 },
|
|
{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
|
|
{ "INT_ERR_INT", 8, 5 },
|
|
{ "PG_TH_INT7", 7, 1 },
|
|
{ "PG_TH_INT6", 6, 1 },
|
|
{ "PG_TH_INT5", 5, 1 },
|
|
{ "PG_TH_INT4", 4, 1 },
|
|
{ "PG_TH_INT3", 3, 1 },
|
|
{ "PG_TH_INT2", 2, 1 },
|
|
{ "PG_TH_INT1", 1, 1 },
|
|
{ "PG_TH_INT0", 0, 1 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0", 0x1108c, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1", 0x11090, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2", 0x11094, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3", 0x11098, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
|
|
{ "ETYPE", 16, 16 },
|
|
{ "OPCODE", 0, 16 },
|
|
{ "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
|
|
{ "ETYPE", 16, 16 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
|
|
{ "MPS_RX_PT_ARB0", 0x110a8, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB1", 0x110ac, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB2", 0x110b0, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB3", 0x110b4, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB4", 0x110b8, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_PF_OUT_EN", 0x110bc, 0 },
|
|
{ "MPS_BMC_MTU", 0x110c0, 0 },
|
|
{ "MPS_BMC_PKT_CNT", 0x110c4, 0 },
|
|
{ "MPS_BMC_BYTE_CNT", 0x110c8, 0 },
|
|
{ "MPS_PFVF_ATRB_CTL", 0x110cc, 0 },
|
|
{ "RD_WRN", 31, 1 },
|
|
{ "PFVF", 0, 8 },
|
|
{ "MPS_PFVF_ATRB", 0x110d0, 0 },
|
|
{ "PF", 28, 3 },
|
|
{ "OFF", 18, 1 },
|
|
{ "NV_DROP", 17, 1 },
|
|
{ "MODE", 16, 1 },
|
|
{ "MTU", 0, 14 },
|
|
{ "MPS_PFVF_ATRB_FLTR0", 0x110d4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR1", 0x110d8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR2", 0x110dc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR3", 0x110e0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR4", 0x110e4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR5", 0x110e8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR6", 0x110ec, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR7", 0x110f0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR8", 0x110f4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR9", 0x110f8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR10", 0x110fc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR11", 0x11100, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR12", 0x11104, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR13", 0x11108, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR14", 0x1110c, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR15", 0x11110, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_RPLC_MAP_CTL", 0x11114, 0 },
|
|
{ "RD_WRN", 31, 1 },
|
|
{ "ADDR", 0, 10 },
|
|
{ "MPS_PF_RPLCT_MAP", 0x11118, 0 },
|
|
{ "MPS_VF_RPLCT_MAP0", 0x1111c, 0 },
|
|
{ "MPS_VF_RPLCT_MAP1", 0x11120, 0 },
|
|
{ "MPS_VF_RPLCT_MAP2", 0x11124, 0 },
|
|
{ "MPS_VF_RPLCT_MAP3", 0x11128, 0 },
|
|
{ "MPS_MEM_DBG_CTL", 0x1112c, 0 },
|
|
{ "PKD", 17, 1 },
|
|
{ "PGD", 16, 1 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MPS_PKD_MEM_DATA0", 0x11130, 0 },
|
|
{ "MPS_PKD_MEM_DATA1", 0x11134, 0 },
|
|
{ "MPS_PKD_MEM_DATA2", 0x11138, 0 },
|
|
{ "MPS_PGD_MEM_DATA", 0x1113c, 0 },
|
|
{ "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
|
|
{ "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
|
|
{ "MPS_RX_SE_CNT_IN0", 0x11148, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN1", 0x1114c, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN2", 0x11150, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN3", 0x11154, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN4", 0x11158, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN5", 0x1115c, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN6", 0x11160, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN7", 0x11164, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_OUT01", 0x11168, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_RX_SPI_ERR", 0x11170, 0 },
|
|
{ "LEN_ERR", 21, 4 },
|
|
{ "ERR", 0, 21 },
|
|
{ "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
|
|
{ "ST3", 24, 8 },
|
|
{ "ST2", 16, 8 },
|
|
{ "ST1", 8, 8 },
|
|
{ "ST0", 0, 8 },
|
|
{ "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
|
|
{ "ST_NCSI", 23, 9 },
|
|
{ "ST_TP", 0, 23 },
|
|
{ "MPS_RX_DBG_CTL", 0x1117c, 0 },
|
|
{ "OUT_DBG_CHNL", 8, 3 },
|
|
{ "DBG_PKD_QSEL", 7, 1 },
|
|
{ "DBG_CDS_INV", 6, 1 },
|
|
{ "IN_DBG_PORT", 3, 3 },
|
|
{ "IN_DBG_CHNL", 0, 3 },
|
|
{ "MPS_RX_CLS_DROP_CNT0", 0x11180, 0 },
|
|
{ "LPBK_CNT0", 16, 16 },
|
|
{ "MAC_CNT0", 0, 16 },
|
|
{ "MPS_RX_CLS_DROP_CNT1", 0x11184, 0 },
|
|
{ "LPBK_CNT1", 16, 16 },
|
|
{ "MAC_CNT1", 0, 16 },
|
|
{ "MPS_RX_CLS_DROP_CNT2", 0x11188, 0 },
|
|
{ "LPBK_CNT2", 16, 16 },
|
|
{ "MAC_CNT2", 0, 16 },
|
|
{ "MPS_RX_CLS_DROP_CNT3", 0x1118c, 0 },
|
|
{ "LPBK_CNT3", 16, 16 },
|
|
{ "MAC_CNT3", 0, 16 },
|
|
{ "MPS_RX_SPARE", 0x11190, 0 },
|
|
{ "MPS_PORT_RX_CTL", 0x20100, 0 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x20104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x20108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x2010c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x20110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x20114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x20118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x2011c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x20120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x20124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x20128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x2012c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x20130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x20134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x20138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x2013c, 0 },
|
|
{ "MPS_PORT_RX_CTL", 0x22100, 0 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x22104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x22108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x2210c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x22110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x22114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x22118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x2211c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x22120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x22124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x22128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x2212c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x22130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x22134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x22138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x2213c, 0 },
|
|
{ "MPS_PORT_RX_CTL", 0x24100, 0 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x24104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x24108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x2410c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x24110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x24114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x24118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x2411c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x24120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x24124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x24128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x2412c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x24130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x24134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x24138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x2413c, 0 },
|
|
{ "MPS_PORT_RX_CTL", 0x26100, 0 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x26104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x26108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x2610c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x26110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x26114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x26118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x2611c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x26120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x26124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x26128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x2612c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x26130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x26134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x26138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x2613c, 0 },
|
|
{ "MPS_TX_PRTY_SEL", 0x9400, 0 },
|
|
{ "Ch4_Prty", 20, 3 },
|
|
{ "Ch3_Prty", 16, 3 },
|
|
{ "Ch2_Prty", 12, 3 },
|
|
{ "Ch1_Prty", 8, 3 },
|
|
{ "Ch0_Prty", 4, 3 },
|
|
{ "TP_Source", 2, 2 },
|
|
{ "NCSI_Source", 0, 2 },
|
|
{ "MPS_TX_INT_ENABLE", 0x9404, 0 },
|
|
{ "PortErr", 16, 1 },
|
|
{ "FRMERR", 15, 1 },
|
|
{ "SECNTERR", 14, 1 },
|
|
{ "BUBBLE", 13, 1 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
|
|
{ "PortErr", 16, 1 },
|
|
{ "FRMERR", 15, 1 },
|
|
{ "SECNTERR", 14, 1 },
|
|
{ "BUBBLE", 13, 1 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_PERR_INJECT", 0x9414, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_TX_SE_CNT_TP01", 0x9418, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_TP23", 0x941c, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_MAC01", 0x9420, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_MAC23", 0x9424, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 },
|
|
{ "Bubble", 16, 8 },
|
|
{ "Spi", 8, 8 },
|
|
{ "SeCnt", 0, 8 },
|
|
{ "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 },
|
|
{ "Bubble", 8, 8 },
|
|
{ "SeCnt", 0, 8 },
|
|
{ "MPS_TX_PORT_ERR", 0x9430, 0 },
|
|
{ "Lpbkpt3", 7, 1 },
|
|
{ "Lpbkpt2", 6, 1 },
|
|
{ "Lpbkpt1", 5, 1 },
|
|
{ "Lpbkpt0", 4, 1 },
|
|
{ "pt3", 3, 1 },
|
|
{ "pt2", 2, 1 },
|
|
{ "pt1", 1, 1 },
|
|
{ "pt0", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
|
|
{ "SOPCh1", 31, 1 },
|
|
{ "EOPCh1", 30, 1 },
|
|
{ "SizeCh1", 27, 3 },
|
|
{ "ErrCh1", 26, 1 },
|
|
{ "FullCh1", 25, 1 },
|
|
{ "ValidCh1", 24, 1 },
|
|
{ "DataCh1", 16, 8 },
|
|
{ "SOPCh0", 15, 1 },
|
|
{ "EOPCh0", 14, 1 },
|
|
{ "SizeCh0", 11, 3 },
|
|
{ "ErrCh0", 10, 1 },
|
|
{ "FullCh0", 9, 1 },
|
|
{ "ValidCh0", 8, 1 },
|
|
{ "DataCh0", 0, 8 },
|
|
{ "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
|
|
{ "SOPCh3", 31, 1 },
|
|
{ "EOPCh3", 30, 1 },
|
|
{ "SizeCh3", 27, 3 },
|
|
{ "ErrCh3", 26, 1 },
|
|
{ "FullCh3", 25, 1 },
|
|
{ "ValidCh3", 24, 1 },
|
|
{ "DataCh3", 16, 8 },
|
|
{ "SOPCh2", 15, 1 },
|
|
{ "EOPCh2", 14, 1 },
|
|
{ "SizeCh2", 11, 3 },
|
|
{ "ErrCh2", 10, 1 },
|
|
{ "FullCh2", 9, 1 },
|
|
{ "ValidCh2", 8, 1 },
|
|
{ "DataCh2", 0, 8 },
|
|
{ "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
|
|
{ "SOPPt1", 31, 1 },
|
|
{ "EOPPt1", 30, 1 },
|
|
{ "SizePt1", 27, 3 },
|
|
{ "ErrPt1", 26, 1 },
|
|
{ "FullPt1", 25, 1 },
|
|
{ "ValidPt1", 24, 1 },
|
|
{ "DataPt1", 16, 8 },
|
|
{ "SOPPt0", 15, 1 },
|
|
{ "EOPPt0", 14, 1 },
|
|
{ "SizePt0", 11, 3 },
|
|
{ "ErrPt0", 10, 1 },
|
|
{ "FullPt0", 9, 1 },
|
|
{ "ValidPt0", 8, 1 },
|
|
{ "DataPt0", 0, 8 },
|
|
{ "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
|
|
{ "SOPPt3", 31, 1 },
|
|
{ "EOPPt3", 30, 1 },
|
|
{ "SizePt3", 27, 3 },
|
|
{ "ErrPt3", 26, 1 },
|
|
{ "FullPt3", 25, 1 },
|
|
{ "ValidPt3", 24, 1 },
|
|
{ "DataPt3", 16, 8 },
|
|
{ "SOPPt2", 15, 1 },
|
|
{ "EOPPt2", 14, 1 },
|
|
{ "SizePt2", 11, 3 },
|
|
{ "ErrPt2", 10, 1 },
|
|
{ "FullPt2", 9, 1 },
|
|
{ "ValidPt2", 8, 1 },
|
|
{ "DataPt2", 0, 8 },
|
|
{ "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
|
|
{ "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
|
|
{ "SubPrtH", 11, 5 },
|
|
{ "PortH", 8, 3 },
|
|
{ "SubPrtL", 3, 5 },
|
|
{ "PortL", 0, 3 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x20190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x20194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x20198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x2019c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x201a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x201a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x201ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x201b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x201b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x201b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x201c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x201c8, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x22190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x22194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x22198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x2219c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x221a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x221a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x221ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x221b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x221b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x221b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x221c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x221c8, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x24190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x24194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x24198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x2419c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x241a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x241a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x241ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x241b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x241b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x241b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x241c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x241c8, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x26190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x26194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x26198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x2619c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x261a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x261a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x261ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x261b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x261b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x261b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x261c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x261c8, 0 },
|
|
{ "MPS_TRC_CFG", 0x9800, 0 },
|
|
{ "TrcFifoEmpty", 4, 1 },
|
|
{ "TrcIgnoreDropInput", 3, 1 },
|
|
{ "TrcKeepDuplicates", 2, 1 },
|
|
{ "TrcEn", 1, 1 },
|
|
{ "TrcMultiFilter", 0, 1 },
|
|
{ "MPS_TRC_RSS_HASH", 0x9804, 0 },
|
|
{ "MPS_TRC_RSS_CONTROL", 0x9808, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 },
|
|
{ "TfInvertMatch", 24, 1 },
|
|
{ "TfPktTooLarge", 23, 1 },
|
|
{ "TfEn", 22, 1 },
|
|
{ "TfPort", 18, 4 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 },
|
|
{ "TfInvertMatch", 24, 1 },
|
|
{ "TfPktTooLarge", 23, 1 },
|
|
{ "TfEn", 22, 1 },
|
|
{ "TfPort", 18, 4 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 },
|
|
{ "TfInvertMatch", 24, 1 },
|
|
{ "TfPktTooLarge", 23, 1 },
|
|
{ "TfEn", 22, 1 },
|
|
{ "TfPort", 18, 4 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 },
|
|
{ "TfInvertMatch", 24, 1 },
|
|
{ "TfPktTooLarge", 23, 1 },
|
|
{ "TfEn", 22, 1 },
|
|
{ "TfPort", 18, 4 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9840, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9844, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9848, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x984c, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_PERR_INJECT", 0x9850, 0 },
|
|
{ "MemSel", 1, 4 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_INT_ENABLE", 0x9858, 0 },
|
|
{ "PLErrEnb", 9, 1 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_INT_CAUSE", 0x985c, 0 },
|
|
{ "PLErrEnb", 9, 1 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_TIMESTAMP_L", 0x9860, 0 },
|
|
{ "MPS_TRC_TIMESTAMP_H", 0x9864, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
|
|
{ "MPS_STAT_CTL", 0x9600, 0 },
|
|
{ "CountVFinPF", 1, 1 },
|
|
{ "LpbkErrStat", 0, 1 },
|
|
{ "MPS_STAT_INT_ENABLE", 0x9608, 0 },
|
|
{ "MPS_STAT_INT_CAUSE", 0x960c, 0 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
|
|
{ "Rxbg", 20, 1 },
|
|
{ "Rxvf", 18, 2 },
|
|
{ "Txvf", 16, 2 },
|
|
{ "Rxpf", 13, 3 },
|
|
{ "Txpf", 11, 2 },
|
|
{ "Rxport", 7, 4 },
|
|
{ "Lbport", 4, 3 },
|
|
{ "Txport", 0, 4 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
|
|
{ "Rxbg", 20, 1 },
|
|
{ "Rxvf", 18, 2 },
|
|
{ "Txvf", 16, 2 },
|
|
{ "Rxpf", 13, 3 },
|
|
{ "Txpf", 11, 2 },
|
|
{ "Rxport", 7, 4 },
|
|
{ "Lbport", 4, 3 },
|
|
{ "Txport", 0, 4 },
|
|
{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
|
|
{ "Rxbg", 20, 1 },
|
|
{ "Rxvf", 18, 2 },
|
|
{ "Txvf", 16, 2 },
|
|
{ "Rxpf", 13, 3 },
|
|
{ "Txpf", 11, 2 },
|
|
{ "Rxport", 7, 4 },
|
|
{ "Lbport", 4, 3 },
|
|
{ "Txport", 0, 4 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_INJECT", 0x9634, 0 },
|
|
{ "MemSel", 1, 7 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
|
|
{ "SubPrtH", 5, 5 },
|
|
{ "SubPrtL", 0, 5 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x20400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x20404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x20408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x2040c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x20410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x20414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x20418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x2041c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x20420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x20424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x20428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x2042c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x20430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x20434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x20438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x2043c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x20440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x20444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x20448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x2044c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x20450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x20454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x20458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x2045c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x20460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x20464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x20468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x2046c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x20470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x20474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x20478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x2047c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x20480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x20484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x20488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x2048c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x20490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x20494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x20498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x2049c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x204a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x204a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x204a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x204ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x204b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x204b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x204c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x204c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x204c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x204cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x204d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x204d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x204d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x204dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x204e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x204e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x204e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x204ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x204f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x204f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x204f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x204fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x20500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x20504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x20508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x2050c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x20510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x20514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x20518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x2051c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x20520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x20524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES", 0x20528, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x20540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x20544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x20548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x2054c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x20550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x20554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x20558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x2055c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x20560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x20564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x20568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x2056c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x20570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x20574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x20578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x2057c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x20580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x20584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x20588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x2058c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x20590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x20594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x20598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x2059c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x205a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x205a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x205a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x205ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x205b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x205b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x205b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x205bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x205c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x205c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x205c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x205cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x205d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x205d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x205d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x205dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x205e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x205e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x205e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x205ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x205f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x205f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x205f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x205fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x20600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x20604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x20608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x2060c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x20610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x20614, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x22400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x22404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x22408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x2240c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x22410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x22414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x22418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x2241c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x22420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x22424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x22428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x2242c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x22430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x22434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x22438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x2243c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x22440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x22444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x22448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x2244c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x22450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x22454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x22458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x2245c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x22460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x22464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x22468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x2246c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x22470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x22474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x22478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x2247c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x22480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x22484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x22488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x2248c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x22490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x22494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x22498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x2249c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x224a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x224a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x224a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x224ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x224b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x224b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x224c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x224c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x224c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x224cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x224d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x224d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x224d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x224dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x224e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x224e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x224e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x224ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x224f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x224f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x224f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x224fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x22500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x22504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x22508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x2250c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x22510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x22514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x22518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x2251c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x22520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x22524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES", 0x22528, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x22540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x22544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x22548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x2254c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x22550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x22554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x22558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x2255c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x22560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x22564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x22568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x2256c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x22570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x22574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x22578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x2257c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x22580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x22584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x22588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x2258c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x22590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x22594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x22598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x2259c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x225a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x225a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x225a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x225ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x225b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x225b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x225b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x225bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x225c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x225c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x225c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x225cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x225d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x225d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x225d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x225dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x225e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x225e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x225e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x225ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x225f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x225f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x225f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x225fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x22600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x22604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x22608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x2260c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x22610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x22614, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x24400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x24404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x24408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x2440c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x24410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x24414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x24418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x2441c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x24420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x24424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x24428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x2442c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x24430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x24434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x24438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x2443c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x24440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x24444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x24448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x2444c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x24450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x24454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x24458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x2445c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x24460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x24464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x24468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x2446c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x24470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x24474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x24478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x2447c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x24480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x24484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x24488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x2448c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x24490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x24494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x24498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x2449c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x244a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x244a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x244a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x244ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x244b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x244b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x244c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x244c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x244c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x244cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x244d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x244d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x244d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x244dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x244e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x244e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x244e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x244ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x244f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x244f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x244f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x244fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x24500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x24504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x24508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x2450c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x24510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x24514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x24518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x2451c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x24520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x24524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES", 0x24528, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x24540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x24544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x24548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x2454c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x24550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x24554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x24558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x2455c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x24560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x24564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x24568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x2456c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x24570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x24574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x24578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x2457c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x24580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x24584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x24588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x2458c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x24590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x24594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x24598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x2459c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x245a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x245a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x245a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x245ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x245b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x245b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x245b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x245bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x245c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x245c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x245c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x245cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x245d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x245d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x245d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x245dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x245e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x245e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x245e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x245ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x245f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x245f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x245f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x245fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x24600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x24604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x24608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x2460c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x24610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x24614, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x26400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x26404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x26408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x2640c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x26410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x26414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x26418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x2641c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x26420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x26424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x26428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x2642c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x26430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x26434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x26438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x2643c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x26440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x26444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x26448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x2644c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x26450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x26454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x26458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x2645c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x26460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x26464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x26468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x2646c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x26470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x26474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x26478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x2647c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x26480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x26484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x26488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x2648c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x26490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x26494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x26498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x2649c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x264a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x264a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x264a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x264ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x264b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x264b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x264c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x264c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x264c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x264cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x264d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x264d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x264d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x264dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x264e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x264e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x264e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x264ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x264f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x264f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x264f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x264fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x26500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x26504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x26508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x2650c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x26510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x26514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x26518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x2651c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x26520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x26524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES", 0x26528, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x26540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x26544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x26548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x2654c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x26550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x26554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x26558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x2655c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x26560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x26564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x26568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x2656c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x26570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x26574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x26578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x2657c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x26580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x26584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x26588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x2658c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x26590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x26594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x26598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x2659c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x265a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x265a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x265a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x265ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x265b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x265b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x265b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x265bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x265c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x265c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x265c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x265cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x265d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x265d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x265d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x265dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x265e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x265e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x265e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x265ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x265f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x265f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x265f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x265fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x26600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x26604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x26608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x2660c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x26610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x26614, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2020c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2021c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2022c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2023c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2024c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2025c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2026c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2027c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2028c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2029c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x202fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x20300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2220c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2221c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2222c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2223c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2224c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2225c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2226c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2227c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2228c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2229c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x222fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x22300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2420c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2421c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2422c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2423c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2424c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2425c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2426c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2427c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2428c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2429c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x242fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x24300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2620c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2621c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2622c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2623c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2624c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2625c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2626c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2627c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2628c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x2629c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x262fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x26300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x20304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x20308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x2030c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x20310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x20314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x20318, 0 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x22304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x22308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x2230c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x22310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x22314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x22318, 0 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x24304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x24308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x2430c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x24310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x24314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x24318, 0 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x26304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x26308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x2630c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x26310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x26314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x26318, 0 },
|
|
{ "MPS_CLS_CTL", 0xd000, 0 },
|
|
{ "MemWriteFault", 4, 1 },
|
|
{ "MemWriteWaiting", 3, 1 },
|
|
{ "CimNoPromiscuous", 2, 1 },
|
|
{ "HypervisorOnly", 1, 1 },
|
|
{ "VlanClsEn", 0, 1 },
|
|
{ "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
|
|
{ "PlWeight", 16, 5 },
|
|
{ "CimWeight", 8, 5 },
|
|
{ "LpbkWeight", 0, 5 },
|
|
{ "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
|
|
{ "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_CLS_BMC_VLAN", 0xd018, 0 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
|
|
{ "MemSel", 1, 2 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_INT_ENABLE", 0xd024, 0 },
|
|
{ "PLErrEnb", 3, 1 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_INT_CAUSE", 0xd028, 0 },
|
|
{ "PLErrEnb", 3, 1 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
|
|
{ "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
|
|
{ "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
|
|
{ "Cls_Priority", 24, 3 },
|
|
{ "Cls_Replicate", 23, 1 },
|
|
{ "Cls_Index", 14, 9 },
|
|
{ "Cls_VF", 7, 7 },
|
|
{ "Cls_VF_Vld", 6, 1 },
|
|
{ "Cls_PF", 3, 3 },
|
|
{ "Cls_Match", 0, 3 },
|
|
{ "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
|
|
{ "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_SRAM_L", 0xe000, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe008, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe010, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe018, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe020, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe028, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe030, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe038, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe040, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe048, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe050, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe058, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe060, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe068, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe070, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe078, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe080, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe088, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe090, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe098, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe100, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe108, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe110, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe118, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe120, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe128, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe130, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe138, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe140, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe148, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe150, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe158, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe160, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe168, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe170, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe178, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe180, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe188, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe190, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe198, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe200, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe208, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe210, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe218, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe220, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe228, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe230, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe238, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe240, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe248, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe250, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe258, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe260, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe268, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe270, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe278, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe280, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe288, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe290, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe298, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe300, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe308, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe310, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe318, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe320, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe328, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe330, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe338, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe340, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe348, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe350, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe358, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe360, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe368, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe370, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe378, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe380, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe388, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe390, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe398, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe400, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe408, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe410, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe418, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe420, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe428, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe430, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe438, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe440, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe448, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe450, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe458, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe460, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe468, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe470, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe478, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe480, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe488, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe490, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe498, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe500, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe508, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe510, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe518, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe520, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe528, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe530, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe538, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe540, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe548, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe550, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe558, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe560, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe568, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe570, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe578, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe580, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe588, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe590, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe598, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe600, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe608, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe610, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe618, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe620, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe628, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe630, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe638, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe640, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe648, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe650, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe658, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe660, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe668, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe670, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe678, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe680, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe688, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe690, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe698, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe700, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe708, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe710, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe718, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe720, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe728, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe730, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe738, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe740, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe748, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe750, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe758, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe760, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe768, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe770, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe778, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe780, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe788, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe790, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe798, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe800, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe808, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe810, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe818, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe820, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe828, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe830, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe838, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe840, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe848, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe850, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe858, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe860, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe868, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe870, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe878, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe880, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe888, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe890, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe898, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe900, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe908, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe910, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe918, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe920, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe928, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe930, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe938, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe940, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe948, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe950, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe958, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe960, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe968, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe970, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe978, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe980, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe988, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe990, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe998, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_H", 0xe004, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe00c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe014, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe01c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe024, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe02c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe034, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe03c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe044, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe04c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe054, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe05c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe064, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe06c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe074, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe07c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe084, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe08c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe094, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe09c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe104, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe10c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe114, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe11c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe124, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe12c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe134, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe13c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe144, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe14c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe154, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe15c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe164, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe16c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe174, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe17c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe184, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe18c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe194, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe19c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe204, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe20c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe214, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe21c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe224, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe22c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe234, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe23c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe244, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe24c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe254, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe25c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe264, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe26c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe274, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe27c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe284, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe28c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe294, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe29c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe304, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe30c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe314, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe31c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe324, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe32c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe334, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe33c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe344, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe34c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe354, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe35c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe364, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe36c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe374, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe37c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe384, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe38c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe394, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe39c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe404, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe40c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe414, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe41c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe424, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe42c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe434, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe43c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe444, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe44c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe454, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe45c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe464, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe46c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe474, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe47c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe484, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe48c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe494, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe49c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe504, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe50c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe514, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe51c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe524, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe52c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe534, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe53c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe544, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe54c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe554, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe55c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe564, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe56c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe574, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe57c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe584, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe58c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe594, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe59c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe604, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe60c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe614, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe61c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe624, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe62c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe634, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe63c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe644, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe64c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe654, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe65c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe664, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe66c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe674, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe67c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe684, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe68c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe694, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe69c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe704, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe70c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe714, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe71c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe724, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe72c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe734, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe73c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe744, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe74c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe754, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe75c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe764, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe76c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe774, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe77c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe784, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe78c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe794, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe79c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe804, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe80c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe814, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe81c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe824, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe82c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe834, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe83c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe844, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe84c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe854, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe85c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe864, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe86c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe874, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe87c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe884, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe88c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe894, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe89c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe904, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe90c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe914, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe91c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe924, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe92c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe934, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe93c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe944, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe94c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe954, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe95c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe964, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe96c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe974, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe97c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe984, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe98c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe994, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe99c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf000, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf010, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf020, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf030, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf040, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf050, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf060, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf070, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf080, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf090, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf100, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf110, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf120, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf130, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf140, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf150, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf160, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf170, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf180, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf190, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf200, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf210, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf220, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf230, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf240, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf250, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf260, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf270, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf280, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf290, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf300, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf310, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf320, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf330, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf340, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf350, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf360, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf370, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf380, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf390, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf400, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf410, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf420, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf430, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf440, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf450, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf460, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf470, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf480, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf490, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf500, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf510, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf520, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf530, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf540, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf550, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf560, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf570, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf580, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf590, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf600, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf610, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf620, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf630, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf640, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf650, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf660, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf670, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf680, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf690, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf700, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf710, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf720, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf730, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf740, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf750, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf760, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf770, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf780, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf790, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf800, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf810, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf820, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf830, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf840, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf850, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf860, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf870, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf880, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf890, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf900, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf910, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf920, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf930, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf940, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf950, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf960, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf970, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf980, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf990, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfaa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfab0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfac0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfad0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfae0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfaf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfba0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbe0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfca0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfce0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfda0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfde0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfea0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfeb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfec0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfed0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfee0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfef0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffe0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfff0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10000, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10010, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10020, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10030, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10040, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10050, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10060, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10070, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10080, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10090, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10100, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10110, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10120, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10130, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10140, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10150, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10160, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10170, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10180, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10190, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10200, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10210, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10220, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10230, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10240, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10250, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10260, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10270, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10280, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10290, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10300, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10310, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10320, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10330, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10340, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10350, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10360, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10370, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10380, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10390, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10400, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10410, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10420, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10430, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10440, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10450, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10460, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10470, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10480, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10490, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10500, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10510, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10520, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10530, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10540, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10550, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10560, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10570, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10580, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10590, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10600, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10610, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10620, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10630, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10640, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10650, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10660, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10670, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10680, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10690, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10700, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10710, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10720, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10730, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10740, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10750, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10760, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10770, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10780, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10790, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10800, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10810, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10820, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10830, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10840, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10850, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10860, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10870, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10880, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10890, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10900, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10910, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10920, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10930, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10940, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10950, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10960, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10970, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10980, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10990, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10aa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ab0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ac0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ad0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ae0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10af0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ba0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10be0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ca0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ce0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10da0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10db0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10dc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10dd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10de0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10df0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ea0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10eb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ec0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ed0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ee0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ef0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fe0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ff0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf004, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf014, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf024, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf034, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf044, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf054, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf064, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf074, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf084, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf094, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf104, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf114, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf124, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf134, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf144, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf154, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf164, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf174, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf184, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf194, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf204, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf214, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf224, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf234, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf244, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf254, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf264, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf274, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf284, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf294, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf304, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf314, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf324, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf334, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf344, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf354, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf364, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf374, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf384, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf394, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf404, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf414, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf424, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf434, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf444, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf454, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf464, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf474, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf484, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf494, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf504, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf514, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf524, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf534, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf544, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf554, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf564, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf574, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf584, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf594, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf604, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf614, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf624, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf634, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf644, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf654, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf664, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf674, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf684, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf694, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf704, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf714, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf724, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf734, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf744, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf754, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf764, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf774, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf784, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf794, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf804, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf814, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf824, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf834, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf844, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf854, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf864, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf874, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf884, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf894, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf904, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf914, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf924, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf934, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf944, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf954, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf964, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf974, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf984, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf994, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfaa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfab4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfac4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfad4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfae4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfaf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfba4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbe4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfca4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfce4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfda4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfde4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfea4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfeb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfec4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfed4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfee4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfef4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffe4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfff4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10004, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10014, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10024, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10034, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10044, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10054, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10064, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10074, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10084, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10094, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10104, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10114, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10124, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10134, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10144, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10154, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10164, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10174, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10184, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10194, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10204, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10214, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10224, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10234, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10244, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10254, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10264, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10274, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10284, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10294, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10304, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10314, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10324, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10334, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10344, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10354, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10364, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10374, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10384, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10394, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10404, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10414, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10424, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10434, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10444, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10454, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10464, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10474, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10484, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10494, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10504, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10514, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10524, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10534, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10544, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10554, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10564, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10574, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10584, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10594, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10604, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10614, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10624, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10634, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10644, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10654, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10664, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10674, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10684, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10694, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10704, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10714, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10724, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10734, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10744, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10754, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10764, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10774, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10784, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10794, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10804, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10814, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10824, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10834, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10844, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10854, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10864, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10874, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10884, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10894, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10904, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10914, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10924, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10934, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10944, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10954, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10964, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10974, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10984, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10994, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10aa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ab4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ac4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ad4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ae4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10af4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ba4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10be4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ca4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ce4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10da4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10db4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10dc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10dd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10de4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10df4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ea4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10eb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ec4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ed4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ee4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ef4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fe4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ff4, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf008, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf018, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf028, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf038, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf048, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf058, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf068, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf078, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf088, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf098, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf108, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf118, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf128, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf138, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf148, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf158, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf168, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf178, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf188, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf198, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf208, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf218, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf228, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf238, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf248, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf258, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf268, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf278, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf288, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf298, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf308, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf318, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf328, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf338, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf348, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf358, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf368, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf378, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf388, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf398, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf408, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf418, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf428, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf438, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf448, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf458, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf468, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf478, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf488, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf498, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf508, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf518, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf528, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf538, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf548, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf558, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf568, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf578, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf588, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf598, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf608, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf618, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf628, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf638, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf648, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf658, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf668, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf678, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf688, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf698, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf708, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf718, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf728, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf738, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf748, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf758, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf768, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf778, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf788, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf798, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf808, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf818, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf828, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf838, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf848, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf858, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf868, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf878, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf888, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf898, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf908, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf918, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf928, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf938, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf948, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf958, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf968, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf978, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf988, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf998, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfaa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfab8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfac8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfad8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfae8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfaf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfba8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbe8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfca8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfce8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfda8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfde8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfea8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfeb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfec8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfed8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfee8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfef8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffe8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfff8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10008, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10018, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10028, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10038, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10048, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10058, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10068, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10078, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10088, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10098, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10108, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10118, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10128, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10138, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10148, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10158, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10168, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10178, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10188, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10198, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10208, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10218, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10228, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10238, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10248, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10258, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10268, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10278, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10288, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10298, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10308, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10318, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10328, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10338, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10348, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10358, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10368, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10378, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10388, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10398, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10408, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10418, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10428, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10438, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10448, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10458, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10468, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10478, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10488, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10498, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10508, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10518, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10528, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10538, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10548, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10558, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10568, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10578, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10588, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10598, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10608, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10618, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10628, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10638, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10648, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10658, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10668, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10678, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10688, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10698, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10708, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10718, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10728, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10738, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10748, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10758, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10768, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10778, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10788, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10798, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10808, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10818, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10828, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10838, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10848, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10858, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10868, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10878, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10888, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10898, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10908, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10918, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10928, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10938, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10948, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10958, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10968, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10978, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10988, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10998, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10aa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ab8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ac8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ad8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ae8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10af8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ba8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10be8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ca8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ce8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10da8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10db8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10dc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10dd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10de8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10df8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ea8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10eb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ec8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ed8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ee8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ef8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fe8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ff8, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf00c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf01c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf02c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf03c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf04c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf05c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf06c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf07c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf08c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf09c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf10c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf11c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf12c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf13c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf14c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf15c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf16c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf17c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf18c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf19c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf20c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf21c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf22c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf23c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf24c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf25c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf26c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf27c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf28c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf29c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf30c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf31c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf32c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf33c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf34c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf35c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf36c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf37c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf38c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf39c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf40c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf41c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf42c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf43c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf44c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf45c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf46c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf47c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf48c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf49c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf50c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf51c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf52c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf53c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf54c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf55c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf56c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf57c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf58c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf59c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf60c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf61c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf62c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf63c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf64c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf65c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf66c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf67c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf68c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf69c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf70c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf71c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf72c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf73c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf74c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf75c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf76c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf77c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf78c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf79c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf80c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf81c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf82c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf83c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf84c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf85c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf86c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf87c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf88c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf89c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf90c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf91c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf92c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf93c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf94c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf95c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf96c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf97c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf98c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf99c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfaac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfabc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfacc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfadc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfaec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfafc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfccc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfddc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfeac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfebc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfecc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfedc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfeec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfefc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfffc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1000c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1001c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1002c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1003c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1004c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1005c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1006c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1007c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1008c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1009c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1010c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1011c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1012c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1013c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1014c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1015c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1016c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1017c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1018c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1019c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1020c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1021c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1022c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1023c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1024c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1025c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1026c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1027c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1028c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1029c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1030c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1031c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1032c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1033c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1034c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1035c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1036c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1037c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1038c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1039c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1040c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1041c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1042c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1043c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1044c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1045c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1046c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1047c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1048c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1049c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1050c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1051c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1052c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1053c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1054c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1055c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1056c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1057c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1058c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1059c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1060c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1061c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1062c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1063c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1064c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1065c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1066c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1067c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1068c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1069c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1070c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1071c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1072c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1073c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1074c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1075c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1076c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1077c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1078c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1079c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1080c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1081c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1082c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1083c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1084c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1085c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1086c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1087c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1088c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1089c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1090c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1091c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1092c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1093c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1094c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1095c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1096c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1097c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1098c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1099c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10aac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10abc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10acc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10adc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10aec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10afc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ccc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ddc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10eac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ebc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ecc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10edc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10eec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10efc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ffc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_cpl_switch_regs[] = {
|
|
{ "CPL_SWITCH_CNTRL", 0x19040, 0 },
|
|
{ "cpl_pkt_tid", 8, 24 },
|
|
{ "cim_truncate_enable", 5, 1 },
|
|
{ "cim_to_up_full_size", 4, 1 },
|
|
{ "cpu_no_enable", 3, 1 },
|
|
{ "switch_table_enable", 2, 1 },
|
|
{ "sge_enable", 1, 1 },
|
|
{ "cim_enable", 0, 1 },
|
|
{ "CPL_SWITCH_TBL_IDX", 0x19044, 0 },
|
|
{ "CPL_SWITCH_TBL_DATA", 0x19048, 0 },
|
|
{ "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 },
|
|
{ "zero_cmd_ch1", 8, 8 },
|
|
{ "zero_cmd_ch0", 0, 8 },
|
|
{ "CPL_INTR_ENABLE", 0x19050, 0 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_INTR_CAUSE", 0x19054, 0 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_MAP_TBL_IDX", 0x19058, 0 },
|
|
{ "CPL_MAP_TBL_DATA", 0x1905c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_smb_regs[] = {
|
|
{ "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
|
|
{ "MacroCntCfg", 8, 5 },
|
|
{ "MicroCntCfg", 0, 8 },
|
|
{ "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
|
|
{ "SMB_MST_CTL_CFG", 0x19068, 0 },
|
|
{ "MstFifoDbg", 31, 1 },
|
|
{ "MstFifoDbgClr", 30, 1 },
|
|
{ "MstRxByteCfg", 12, 6 },
|
|
{ "MstTxByteCfg", 6, 6 },
|
|
{ "MstReset", 1, 1 },
|
|
{ "MstCtlEn", 0, 1 },
|
|
{ "SMB_MST_CTL_STS", 0x1906c, 0 },
|
|
{ "MstRxByteCnt", 12, 6 },
|
|
{ "MstTxByteCnt", 6, 6 },
|
|
{ "MstBusySts", 0, 1 },
|
|
{ "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
|
|
{ "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
|
|
{ "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
|
|
{ "SMB_SLV_CTL_CFG", 0x1907c, 0 },
|
|
{ "SlvFifoDbg", 31, 1 },
|
|
{ "SlvFifoDbgClr", 30, 1 },
|
|
{ "SlvCrcOutBitInv", 21, 1 },
|
|
{ "SlvCrcOutBitRev", 20, 1 },
|
|
{ "SlvCrcInBitRev", 19, 1 },
|
|
{ "SlvCrcPreset", 11, 8 },
|
|
{ "SlvAddrCfg", 4, 7 },
|
|
{ "SlvAlrtSet", 2, 1 },
|
|
{ "SlvReset", 1, 1 },
|
|
{ "SlvCtlEn", 0, 1 },
|
|
{ "SMB_SLV_CTL_STS", 0x19080, 0 },
|
|
{ "SlvFifoTxCnt", 12, 6 },
|
|
{ "SlvFifoCnt", 6, 6 },
|
|
{ "SlvAlrtSts", 2, 1 },
|
|
{ "SlvBusySts", 0, 1 },
|
|
{ "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
|
|
{ "SMB_INT_ENABLE", 0x1908c, 0 },
|
|
{ "MstTxFifoParEn", 21, 1 },
|
|
{ "MstRxFifoParEn", 20, 1 },
|
|
{ "SlvFifoParEn", 19, 1 },
|
|
{ "SlvUnExpBusStopEn", 18, 1 },
|
|
{ "SlvUnExpBusStartEn", 17, 1 },
|
|
{ "SlvCommandCodeInvEn", 16, 1 },
|
|
{ "SlvByteCntErrEn", 15, 1 },
|
|
{ "SlvUnExpAckMstEn", 14, 1 },
|
|
{ "SlvUnExpNackMstEn", 13, 1 },
|
|
{ "SlvNoBusStopEn", 12, 1 },
|
|
{ "SlvNoRepStartEn", 11, 1 },
|
|
{ "SlvRxAddrIntEn", 10, 1 },
|
|
{ "SlvRxPecErrIntEn", 9, 1 },
|
|
{ "SlvPrepToArpIntEn", 8, 1 },
|
|
{ "SlvTimeOutIntEn", 7, 1 },
|
|
{ "SlvErrIntEn", 6, 1 },
|
|
{ "SlvDoneIntEn", 5, 1 },
|
|
{ "SlvRxRdyIntEn", 4, 1 },
|
|
{ "MstTimeOutIntEn", 3, 1 },
|
|
{ "MstNAckIntEn", 2, 1 },
|
|
{ "MstLostArbIntEn", 1, 1 },
|
|
{ "MstDoneIntEn", 0, 1 },
|
|
{ "SMB_INT_CAUSE", 0x19090, 0 },
|
|
{ "MstTxFifoParInt", 21, 1 },
|
|
{ "MstRxFifoParInt", 20, 1 },
|
|
{ "SlvFifoParInt", 19, 1 },
|
|
{ "SlvUnExpBusStopInt", 18, 1 },
|
|
{ "SlvUnExpBusStartInt", 17, 1 },
|
|
{ "SlvCommandCodeInvInt", 16, 1 },
|
|
{ "SlvByteCntErrInt", 15, 1 },
|
|
{ "SlvUnExpAckMstInt", 14, 1 },
|
|
{ "SlvUnExpNackMstInt", 13, 1 },
|
|
{ "SlvNoBusStopInt", 12, 1 },
|
|
{ "SlvNoRepStartInt", 11, 1 },
|
|
{ "SlvRxAddrInt", 10, 1 },
|
|
{ "SlvRxPecErrInt", 9, 1 },
|
|
{ "SlvPrepToArpInt", 8, 1 },
|
|
{ "SlvTimeOutInt", 7, 1 },
|
|
{ "SlvErrInt", 6, 1 },
|
|
{ "SlvDoneInt", 5, 1 },
|
|
{ "SlvRxRdyInt", 4, 1 },
|
|
{ "MstTimeOutInt", 3, 1 },
|
|
{ "MstNAckInt", 2, 1 },
|
|
{ "MstLostArbInt", 1, 1 },
|
|
{ "MstDoneInt", 0, 1 },
|
|
{ "SMB_DEBUG_DATA", 0x19094, 0 },
|
|
{ "DebugDataH", 16, 16 },
|
|
{ "DebugDataL", 0, 16 },
|
|
{ "SMB_PERR_EN", 0x19098, 0 },
|
|
{ "MstTxFifoPerrEn", 2, 1 },
|
|
{ "MstRxFifoPerrEn", 1, 1 },
|
|
{ "SlvFifoPerrEn", 0, 1 },
|
|
{ "SMB_PERR_INJ", 0x1909c, 0 },
|
|
{ "MstTxInjDataErr", 3, 1 },
|
|
{ "MstRxInjDataErr", 2, 1 },
|
|
{ "SlvInjDataErr", 1, 1 },
|
|
{ "FifoInjDataErrEn", 0, 1 },
|
|
{ "SMB_SLV_ARP_CTL", 0x190a0, 0 },
|
|
{ "ArpCommandCode", 2, 8 },
|
|
{ "ArpAddrRes", 1, 1 },
|
|
{ "ArpAddrVal", 0, 1 },
|
|
{ "SMB_ARP_UDID0", 0x190a4, 0 },
|
|
{ "SMB_ARP_UDID1", 0x190a8, 0 },
|
|
{ "SubsystemVendorID", 16, 16 },
|
|
{ "SubsystemDeviceID", 0, 16 },
|
|
{ "SMB_ARP_UDID2", 0x190ac, 0 },
|
|
{ "DeviceID", 16, 16 },
|
|
{ "Interface", 0, 16 },
|
|
{ "SMB_ARP_UDID3", 0x190b0, 0 },
|
|
{ "DeviceCap", 24, 8 },
|
|
{ "VersionID", 16, 8 },
|
|
{ "VendorID", 0, 16 },
|
|
{ "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
|
|
{ "AuxAddr0Val", 6, 1 },
|
|
{ "AuxAddr0", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
|
|
{ "AuxAddr1Val", 6, 1 },
|
|
{ "AuxAddr1", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
|
|
{ "AuxAddr2Val", 6, 1 },
|
|
{ "AuxAddr2", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
|
|
{ "AuxAddr3Val", 6, 1 },
|
|
{ "AuxAddr3", 0, 6 },
|
|
{ "SMB_COMMAND_CODE0", 0x190c4, 0 },
|
|
{ "SMB_COMMAND_CODE1", 0x190c8, 0 },
|
|
{ "SMB_COMMAND_CODE2", 0x190cc, 0 },
|
|
{ "SMB_COMMAND_CODE3", 0x190d0, 0 },
|
|
{ "SMB_COMMAND_CODE4", 0x190d4, 0 },
|
|
{ "SMB_COMMAND_CODE5", 0x190d8, 0 },
|
|
{ "SMB_COMMAND_CODE6", 0x190dc, 0 },
|
|
{ "SMB_COMMAND_CODE7", 0x190e0, 0 },
|
|
{ "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
|
|
{ "MacroCntClkCfg", 8, 5 },
|
|
{ "MicroCntClkCfg", 0, 8 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_i2cm_regs[] = {
|
|
{ "I2CM_CFG", 0x190f0, 0 },
|
|
{ "I2CM_DATA", 0x190f4, 0 },
|
|
{ "I2CM_OP", 0x190f8, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Ack", 30, 1 },
|
|
{ "Cont", 1, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_mi_regs[] = {
|
|
{ "MI_CFG", 0x19100, 0 },
|
|
{ "T4_St", 14, 1 },
|
|
{ "ClkDiv", 5, 8 },
|
|
{ "St", 3, 2 },
|
|
{ "PreEn", 2, 1 },
|
|
{ "MDIInv", 1, 1 },
|
|
{ "MDIO_1P2V_Sel", 0, 1 },
|
|
{ "MI_ADDR", 0x19104, 0 },
|
|
{ "PhyAddr", 5, 5 },
|
|
{ "RegAddr", 0, 5 },
|
|
{ "MI_DATA", 0x19108, 0 },
|
|
{ "MI_OP", 0x1910c, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "St", 3, 2 },
|
|
{ "Inc", 2, 1 },
|
|
{ "Op", 0, 2 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_uart_regs[] = {
|
|
{ "UART_CONFIG", 0x19110, 0 },
|
|
{ "StopBits", 22, 2 },
|
|
{ "Parity", 20, 2 },
|
|
{ "DataBits", 16, 4 },
|
|
{ "ClkDiv", 0, 12 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_pmu_regs[] = {
|
|
{ "PMU_PART_CG_PWRMODE", 0x19120, 0 },
|
|
{ "TPPartCGEn", 14, 1 },
|
|
{ "PDPPartCGEn", 13, 1 },
|
|
{ "PCIePartCGEn", 12, 1 },
|
|
{ "EDC1PartCGEn", 11, 1 },
|
|
{ "MCPartCGEn", 10, 1 },
|
|
{ "EDC0PartCGEn", 9, 1 },
|
|
{ "LEPartCGEn", 8, 1 },
|
|
{ "InitPowerMode", 0, 2 },
|
|
{ "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
|
|
{ "HWWakeUpEn", 5, 1 },
|
|
{ "Port3SleepMode", 4, 1 },
|
|
{ "Port2SleepMode", 3, 1 },
|
|
{ "Port1SleepMode", 2, 1 },
|
|
{ "Port0SleepMode", 1, 1 },
|
|
{ "WakeUp", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_ulp_rx_regs[] = {
|
|
{ "ULP_RX_CTL", 0x19150, 0 },
|
|
{ "PCMD1Threshold", 24, 8 },
|
|
{ "PCMD0Threshold", 16, 8 },
|
|
{ "disable_0B_STAG_ERR", 14, 1 },
|
|
{ "RDMA_0b_wr_opcode", 10, 4 },
|
|
{ "RDMA_0b_wr_pass", 9, 1 },
|
|
{ "STAG_RQE", 8, 1 },
|
|
{ "RDMA_State_En", 7, 1 },
|
|
{ "Crc1_En", 6, 1 },
|
|
{ "RDMA_0b_wr_cqe", 5, 1 },
|
|
{ "PCIE_Atrb_En", 4, 1 },
|
|
{ "RDMA_permissive_mode", 3, 1 },
|
|
{ "PagePodME", 2, 1 },
|
|
{ "IscsiTagTcb", 1, 1 },
|
|
{ "TddpTagTcb", 0, 1 },
|
|
{ "ULP_RX_INT_ENABLE", 0x19154, 0 },
|
|
{ "ENABLE_CTX_1", 24, 1 },
|
|
{ "ENABLE_CTX_0", 23, 1 },
|
|
{ "ENABLE_FF", 22, 1 },
|
|
{ "ENABLE_APF_1", 21, 1 },
|
|
{ "ENABLE_APF_0", 20, 1 },
|
|
{ "ENABLE_AF_1", 19, 1 },
|
|
{ "ENABLE_AF_0", 18, 1 },
|
|
{ "ENABLE_DDPDF_1", 17, 1 },
|
|
{ "ENABLE_DDPMF_1", 16, 1 },
|
|
{ "ENABLE_MEMRF_1", 15, 1 },
|
|
{ "ENABLE_PRSDF_1", 14, 1 },
|
|
{ "ENABLE_DDPDF_0", 13, 1 },
|
|
{ "ENABLE_DDPMF_0", 12, 1 },
|
|
{ "ENABLE_MEMRF_0", 11, 1 },
|
|
{ "ENABLE_PRSDF_0", 10, 1 },
|
|
{ "ENABLE_PCMDF_1", 9, 1 },
|
|
{ "ENABLE_TPTCF_1", 8, 1 },
|
|
{ "ENABLE_DDPCF_1", 7, 1 },
|
|
{ "ENABLE_MPARF_1", 6, 1 },
|
|
{ "ENABLE_MPARC_1", 5, 1 },
|
|
{ "ENABLE_PCMDF_0", 4, 1 },
|
|
{ "ENABLE_TPTCF_0", 3, 1 },
|
|
{ "ENABLE_DDPCF_0", 2, 1 },
|
|
{ "ENABLE_MPARF_0", 1, 1 },
|
|
{ "ENABLE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_INT_CAUSE", 0x19158, 0 },
|
|
{ "CAUSE_CTX_1", 24, 1 },
|
|
{ "CAUSE_CTX_0", 23, 1 },
|
|
{ "CAUSE_FF", 22, 1 },
|
|
{ "CAUSE_APF_1", 21, 1 },
|
|
{ "CAUSE_APF_0", 20, 1 },
|
|
{ "CAUSE_AF_1", 19, 1 },
|
|
{ "CAUSE_AF_0", 18, 1 },
|
|
{ "CAUSE_DDPDF_1", 17, 1 },
|
|
{ "CAUSE_DDPMF_1", 16, 1 },
|
|
{ "CAUSE_MEMRF_1", 15, 1 },
|
|
{ "CAUSE_PRSDF_1", 14, 1 },
|
|
{ "CAUSE_DDPDF_0", 13, 1 },
|
|
{ "CAUSE_DDPMF_0", 12, 1 },
|
|
{ "CAUSE_MEMRF_0", 11, 1 },
|
|
{ "CAUSE_PRSDF_0", 10, 1 },
|
|
{ "CAUSE_PCMDF_1", 9, 1 },
|
|
{ "CAUSE_TPTCF_1", 8, 1 },
|
|
{ "CAUSE_DDPCF_1", 7, 1 },
|
|
{ "CAUSE_MPARF_1", 6, 1 },
|
|
{ "CAUSE_MPARC_1", 5, 1 },
|
|
{ "CAUSE_PCMDF_0", 4, 1 },
|
|
{ "CAUSE_TPTCF_0", 3, 1 },
|
|
{ "CAUSE_DDPCF_0", 2, 1 },
|
|
{ "CAUSE_MPARF_0", 1, 1 },
|
|
{ "CAUSE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
|
|
{ "IscsiLlimit", 6, 26 },
|
|
{ "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
|
|
{ "IscsiUlimit", 6, 26 },
|
|
{ "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
|
|
{ "IscsiTagMask", 6, 26 },
|
|
{ "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
|
|
{ "TddpLlimit", 6, 26 },
|
|
{ "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
|
|
{ "TddpUlimit", 6, 26 },
|
|
{ "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
|
|
{ "TddpTagMask", 6, 26 },
|
|
{ "ULP_RX_TDDP_PSZ", 0x19178, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
|
|
{ "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
|
|
{ "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
|
|
{ "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
|
|
{ "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
|
|
{ "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
|
|
{ "ULP_RX_CTX_BASE", 0x19194, 0 },
|
|
{ "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
|
|
{ "PERR_ENABLE_FF", 22, 1 },
|
|
{ "PERR_ENABLE_APF_1", 21, 1 },
|
|
{ "PERR_ENABLE_APF_0", 20, 1 },
|
|
{ "PERR_ENABLE_AF_1", 19, 1 },
|
|
{ "PERR_ENABLE_AF_0", 18, 1 },
|
|
{ "PERR_ENABLE_DDPDF_1", 17, 1 },
|
|
{ "PERR_ENABLE_DDPMF_1", 16, 1 },
|
|
{ "PERR_ENABLE_MEMRF_1", 15, 1 },
|
|
{ "PERR_ENABLE_PRSDF_1", 14, 1 },
|
|
{ "PERR_ENABLE_DDPDF_0", 13, 1 },
|
|
{ "PERR_ENABLE_DDPMF_0", 12, 1 },
|
|
{ "PERR_ENABLE_MEMRF_0", 11, 1 },
|
|
{ "PERR_ENABLE_PRSDF_0", 10, 1 },
|
|
{ "PERR_ENABLE_PCMDF_1", 9, 1 },
|
|
{ "PERR_ENABLE_TPTCF_1", 8, 1 },
|
|
{ "PERR_ENABLE_DDPCF_1", 7, 1 },
|
|
{ "PERR_ENABLE_MPARF_1", 6, 1 },
|
|
{ "PERR_ENABLE_MPARC_1", 5, 1 },
|
|
{ "PERR_ENABLE_PCMDF_0", 4, 1 },
|
|
{ "PERR_ENABLE_TPTCF_0", 3, 1 },
|
|
{ "PERR_ENABLE_DDPCF_0", 2, 1 },
|
|
{ "PERR_ENABLE_MPARF_0", 1, 1 },
|
|
{ "PERR_ENABLE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_PERR_INJECT", 0x191a0, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 },
|
|
{ "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 },
|
|
{ "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
|
|
{ "REQ", 21, 1 },
|
|
{ "WB", 20, 1 },
|
|
{ "TID", 0, 20 },
|
|
{ "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
|
|
{ "REQ", 21, 1 },
|
|
{ "WB", 20, 1 },
|
|
{ "TID", 0, 20 },
|
|
{ "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
|
|
{ "ERR_CH1", 4, 4 },
|
|
{ "ERR_CH0", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
|
|
{ "CLR_CH0", 4, 4 },
|
|
{ "CLR_CH1", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
|
|
{ "SOP_CNT_OUT0", 28, 4 },
|
|
{ "EOP_CNT_OUT0", 24, 4 },
|
|
{ "SOP_CNT_AL0", 20, 4 },
|
|
{ "EOP_CNT_AL0", 16, 4 },
|
|
{ "SOP_CNT_MR0", 12, 4 },
|
|
{ "EOP_CNT_MR0", 8, 4 },
|
|
{ "SOP_CNT_IN0", 4, 4 },
|
|
{ "EOP_CNT_IN0", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
|
|
{ "SOP_CNT_OUT1", 28, 4 },
|
|
{ "EOP_CNT_OUT1", 24, 4 },
|
|
{ "SOP_CNT_AL1", 20, 4 },
|
|
{ "EOP_CNT_AL1", 16, 4 },
|
|
{ "SOP_CNT_MR1", 12, 4 },
|
|
{ "EOP_CNT_MR1", 8, 4 },
|
|
{ "SOP_CNT_IN1", 4, 4 },
|
|
{ "EOP_CNT_IN1", 0, 4 },
|
|
{ "ULP_RX_DBG_CTL", 0x191e0, 0 },
|
|
{ "EN_DBG_H", 17, 1 },
|
|
{ "EN_DBG_L", 16, 1 },
|
|
{ "SEL_H", 8, 8 },
|
|
{ "SEL_L", 0, 8 },
|
|
{ "ULP_RX_DBG_DATAH", 0x191e4, 0 },
|
|
{ "ULP_RX_DBG_DATAL", 0x191e8, 0 },
|
|
{ "ULP_RX_LA_CHNL", 0x19238, 0 },
|
|
{ "ULP_RX_LA_CTL", 0x1923c, 0 },
|
|
{ "ULP_RX_LA_RDPTR", 0x19240, 0 },
|
|
{ "ULP_RX_LA_RDDATA", 0x19244, 0 },
|
|
{ "ULP_RX_LA_WRPTR", 0x19248, 0 },
|
|
{ "ULP_RX_LA_RESERVED", 0x1924c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_sf_regs[] = {
|
|
{ "SF_DATA", 0x193f8, 0 },
|
|
{ "SF_OP", 0x193fc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Lock", 4, 1 },
|
|
{ "Cont", 3, 1 },
|
|
{ "ByteCnt", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_pl_regs[] = {
|
|
{ "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1e3c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1e7c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1ebc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1efc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1efc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1efc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1f3c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1f7c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1fbc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "SGE", 2, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1ffc8, 0 },
|
|
{ "PL_WHOAMI", 0x19400, 0 },
|
|
{ "PortxMap", 24, 3 },
|
|
{ "SourceBus", 16, 2 },
|
|
{ "SourcePF", 8, 3 },
|
|
{ "IsVF", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_PERR_CAUSE", 0x19404, 0 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "XGMAC_KR1", 12, 1 },
|
|
{ "XGMAC_KR0", 11, 1 },
|
|
{ "XGMAC1", 10, 1 },
|
|
{ "XGMAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_PERR_ENABLE", 0x19408, 0 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "XGMAC_KR1", 12, 1 },
|
|
{ "XGMAC_KR0", 11, 1 },
|
|
{ "XGMAC1", 10, 1 },
|
|
{ "XGMAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_CAUSE", 0x1940c, 0 },
|
|
{ "FLR", 30, 1 },
|
|
{ "SW_CIM", 29, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "XGMAC_KR1", 12, 1 },
|
|
{ "XGMAC_KR0", 11, 1 },
|
|
{ "XGMAC1", 10, 1 },
|
|
{ "XGMAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_ENABLE", 0x19410, 0 },
|
|
{ "FLR", 30, 1 },
|
|
{ "SW_CIM", 29, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "XGMAC_KR1", 12, 1 },
|
|
{ "XGMAC_KR0", 11, 1 },
|
|
{ "XGMAC1", 10, 1 },
|
|
{ "XGMAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_MAP0", 0x19414, 0 },
|
|
{ "MapNCSI", 16, 9 },
|
|
{ "MapDefault", 0, 9 },
|
|
{ "PL_INT_MAP1", 0x19418, 0 },
|
|
{ "MapXGMAC1", 16, 9 },
|
|
{ "MapXGMAC0", 0, 9 },
|
|
{ "PL_INT_MAP2", 0x1941c, 0 },
|
|
{ "MapXGMAC_KR1", 16, 9 },
|
|
{ "MapXGMAC_KR0", 0, 9 },
|
|
{ "PL_INT_MAP3", 0x19420, 0 },
|
|
{ "MapMI", 16, 9 },
|
|
{ "MapSMB", 0, 9 },
|
|
{ "PL_INT_MAP4", 0x19424, 0 },
|
|
{ "MapDBG", 16, 9 },
|
|
{ "MapI2CM", 0, 9 },
|
|
{ "PL_RST", 0x19428, 0 },
|
|
{ "FatalPerrEn", 3, 1 },
|
|
{ "SWIntCIM", 2, 1 },
|
|
{ "PIORst", 1, 1 },
|
|
{ "PIORstMode", 0, 1 },
|
|
{ "PL_PL_PERR_INJECT", 0x1942c, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "PL_PL_INT_CAUSE", 0x19430, 0 },
|
|
{ "PF_EnableErr", 5, 1 },
|
|
{ "FatalPerr", 4, 1 },
|
|
{ "InvalidAccess", 3, 1 },
|
|
{ "Timeout", 2, 1 },
|
|
{ "PLErr", 1, 1 },
|
|
{ "PerrVFID", 0, 1 },
|
|
{ "PL_PL_INT_ENABLE", 0x19434, 0 },
|
|
{ "PF_EnableErr", 5, 1 },
|
|
{ "FatalPerr", 4, 1 },
|
|
{ "InvalidAccess", 3, 1 },
|
|
{ "Timeout", 2, 1 },
|
|
{ "PLErr", 1, 1 },
|
|
{ "PerrVFID", 0, 1 },
|
|
{ "PL_PL_PERR_ENABLE", 0x19438, 0 },
|
|
{ "PL_REV", 0x1943c, 0 },
|
|
{ "PL_SEMAPHORE_CTL", 0x1944c, 0 },
|
|
{ "LockStatus", 16, 8 },
|
|
{ "OwnerOverride", 8, 1 },
|
|
{ "EnablePF", 0, 8 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19450, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19454, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19458, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19460, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19464, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19468, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_PF_ENABLE", 0x19470, 0 },
|
|
{ "PL_PORTX_MAP", 0x19474, 0 },
|
|
{ "MAP7", 28, 3 },
|
|
{ "MAP6", 24, 3 },
|
|
{ "MAP5", 20, 3 },
|
|
{ "MAP4", 16, 3 },
|
|
{ "MAP3", 12, 3 },
|
|
{ "MAP2", 8, 3 },
|
|
{ "MAP1", 4, 3 },
|
|
{ "MAP0", 0, 3 },
|
|
{ "PL_VF_SLICE_L", 0x19490, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x19498, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194a0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194a8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194b0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194b8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194c0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194c8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x19494, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x1949c, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194a4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194ac, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194b4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194bc, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194c4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194cc, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_FLR_VF_STATUS", 0x194d0, 0 },
|
|
{ "PL_FLR_VF_STATUS", 0x194d4, 0 },
|
|
{ "PL_FLR_VF_STATUS", 0x194d8, 0 },
|
|
{ "PL_FLR_VF_STATUS", 0x194dc, 0 },
|
|
{ "PL_FLR_PF_STATUS", 0x194e0, 0 },
|
|
{ "PL_TIMEOUT_CTL", 0x194f0, 0 },
|
|
{ "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
|
|
{ "Addr", 2, 28 },
|
|
{ "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "Write", 22, 1 },
|
|
{ "Bus", 20, 2 },
|
|
{ "Rgn", 19, 1 },
|
|
{ "PF", 16, 3 },
|
|
{ "Function", 0, 16 },
|
|
{ "PL_VFID_MAP", 0x19800, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19804, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19808, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1980c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19810, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19814, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19818, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1981c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19820, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19824, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19828, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1982c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19830, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19834, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19838, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1983c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19840, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19844, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19848, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1984c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19850, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19854, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19858, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1985c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19860, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19864, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19868, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1986c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19870, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19874, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19878, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1987c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19880, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19884, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19888, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1988c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19890, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19894, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19898, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1989c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198a0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198a4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198a8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198ac, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198b0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198b4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198b8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198bc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198c0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198c4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198c8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198cc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198d0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198d4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198d8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198dc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198e0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198e4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198e8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198ec, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198f0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198f4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198f8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x198fc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19900, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19904, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19908, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1990c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19910, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19914, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19918, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1991c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19920, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19924, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19928, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1992c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19930, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19934, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19938, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1993c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19940, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19944, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19948, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1994c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19950, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19954, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19958, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1995c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19960, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19964, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19968, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1996c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19970, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19974, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19978, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1997c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19980, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19984, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19988, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1998c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19990, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19994, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19998, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x1999c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199a0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199a4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199a8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199ac, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199b0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199b4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199b8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199bc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199c0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199c4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199c8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199cc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199d0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199d4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199d8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199dc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199e0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199e4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199e8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199ec, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199f0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199f4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199f8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x199fc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a00, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a04, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a08, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a0c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a10, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a14, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a18, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a1c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a20, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a24, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a28, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a2c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a30, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a34, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a38, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a3c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a40, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a44, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a48, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a4c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a50, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a54, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a58, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a5c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a60, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a64, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a68, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a6c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a70, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a74, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a78, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a7c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a80, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a84, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a88, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a8c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a90, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a94, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a98, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19a9c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19aa0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19aa4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19aa8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19aac, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ab0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ab4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ab8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19abc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ac0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ac4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ac8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19acc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ad0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ad4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ad8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19adc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ae0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ae4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ae8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19aec, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19af0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19af4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19af8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19afc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b00, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b04, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b08, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b0c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b10, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b14, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b18, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b1c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b20, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b24, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b28, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b2c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b30, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b34, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b38, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b3c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b40, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b44, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b48, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b4c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b50, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b54, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b58, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b5c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b60, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b64, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b68, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b6c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b70, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b74, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b78, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b7c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b80, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b84, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b88, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b8c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b90, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b94, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b98, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19b9c, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ba0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ba4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19ba8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bac, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bb0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bb4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bb8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bbc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bc0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bc4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bc8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bcc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bd0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bd4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bd8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bdc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19be0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19be4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19be8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bec, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bf0, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bf4, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bf8, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_VFID_MAP", 0x19bfc, 0 },
|
|
{ "Valid", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_le_regs[] = {
|
|
{ "LE_BUF_CONFIG", 0x19c00, 0 },
|
|
{ "LE_DB_CONFIG", 0x19c04, 0 },
|
|
{ "TCAMCMDOVLAPEN", 21, 1 },
|
|
{ "HASHEN", 20, 1 },
|
|
{ "ASBOTHSRCHEN", 18, 1 },
|
|
{ "ASLIPCOMPEN", 17, 1 },
|
|
{ "BUILD", 16, 1 },
|
|
{ "FilterEn", 11, 1 },
|
|
{ "SYNMode", 7, 2 },
|
|
{ "LEBUSEN", 5, 1 },
|
|
{ "ELOOKDUMEN", 4, 1 },
|
|
{ "IPv4ONLYEN", 3, 1 },
|
|
{ "MOSTCMDOEN", 2, 1 },
|
|
{ "DELACTSYNOEN", 1, 1 },
|
|
{ "CMDOVERLAPDIS", 0, 1 },
|
|
{ "LE_MISC", 0x19c08, 0 },
|
|
{ "LE_DB_ROUTING_TABLE_INDEX", 0x19c10, 0 },
|
|
{ "RTINDX", 7, 6 },
|
|
{ "LE_DB_FILTER_TABLE_INDEX", 0x19c14, 0 },
|
|
{ "FTINDX", 7, 6 },
|
|
{ "LE_DB_SERVER_INDEX", 0x19c18, 0 },
|
|
{ "SRINDX", 7, 6 },
|
|
{ "LE_DB_CLIP_TABLE_INDEX", 0x19c1c, 0 },
|
|
{ "CLIPTINDX", 7, 6 },
|
|
{ "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
|
|
{ "LE_DB_HASH_CONFIG", 0x19c28, 0 },
|
|
{ "HASHTIDSIZE", 16, 6 },
|
|
{ "HASHSIZE", 0, 6 },
|
|
{ "LE_DB_HASH_TABLE_BASE", 0x19c2c, 0 },
|
|
{ "LE_DB_HASH_TID_BASE", 0x19c30, 0 },
|
|
{ "LE_DB_SIZE", 0x19c34, 0 },
|
|
{ "LE_DB_INT_ENABLE", 0x19c38, 0 },
|
|
{ "MsgSel", 27, 5 },
|
|
{ "ReqQParErr", 16, 1 },
|
|
{ "UnknownCmd", 15, 1 },
|
|
{ "DropFilterHit", 13, 1 },
|
|
{ "FilterHit", 12, 1 },
|
|
{ "SYNCookieOff", 11, 1 },
|
|
{ "SYNCookieBad", 10, 1 },
|
|
{ "SYNCookie", 9, 1 },
|
|
{ "NFASrchFail", 8, 1 },
|
|
{ "ActRgnFull", 7, 1 },
|
|
{ "ParityErr", 6, 1 },
|
|
{ "LIPMiss", 5, 1 },
|
|
{ "LIP0", 4, 1 },
|
|
{ "Miss", 3, 1 },
|
|
{ "RoutingHit", 2, 1 },
|
|
{ "ActiveHit", 1, 1 },
|
|
{ "ServerHit", 0, 1 },
|
|
{ "LE_DB_INT_CAUSE", 0x19c3c, 0 },
|
|
{ "ReqQParErr", 16, 1 },
|
|
{ "UnknownCmd", 15, 1 },
|
|
{ "DropFilterHit", 13, 1 },
|
|
{ "FilterHit", 12, 1 },
|
|
{ "SYNCookieOff", 11, 1 },
|
|
{ "SYNCookieBad", 10, 1 },
|
|
{ "SYNCookie", 9, 1 },
|
|
{ "NFASrchFail", 8, 1 },
|
|
{ "ActRgnFull", 7, 1 },
|
|
{ "ParityErr", 6, 1 },
|
|
{ "LIPMiss", 5, 1 },
|
|
{ "LIP0", 4, 1 },
|
|
{ "Miss", 3, 1 },
|
|
{ "RoutingHit", 2, 1 },
|
|
{ "ActiveHit", 1, 1 },
|
|
{ "ServerHit", 0, 1 },
|
|
{ "LE_DB_INT_TID", 0x19c40, 0 },
|
|
{ "LE_DB_INT_PTID", 0x19c44, 0 },
|
|
{ "LE_DB_INT_INDEX", 0x19c48, 0 },
|
|
{ "LE_DB_INT_CMD", 0x19c4c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c50, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c54, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c58, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c5c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c60, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c64, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c68, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c6c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c70, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c74, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c78, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c7c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c80, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c84, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c88, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c8c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c90, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ca0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ca4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ca8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cac, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cb0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cb4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cb8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cbc, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cc0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cc4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cc8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ccc, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cd0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cd4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cd8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cdc, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ce0, 0 },
|
|
{ "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
|
|
{ "RspCnt", 16, 16 },
|
|
{ "ReqCnt", 0, 16 },
|
|
{ "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
|
|
{ "DBGICMDPERR", 31, 1 },
|
|
{ "DBGICMDRANGE", 22, 3 },
|
|
{ "DBGICMDMSKTYPE", 21, 1 },
|
|
{ "DBGICMDSEARCH", 20, 1 },
|
|
{ "DBGICMDREAD", 19, 1 },
|
|
{ "DBGICMDLEARN", 18, 1 },
|
|
{ "DBGICMDERASE", 17, 1 },
|
|
{ "DBGICMDIPv6", 16, 1 },
|
|
{ "DBGICMDTYPE", 13, 3 },
|
|
{ "DBGICMDACKERR", 12, 1 },
|
|
{ "DBGICMDBUSY", 3, 1 },
|
|
{ "DBGICMDSTRT", 2, 1 },
|
|
{ "DBGICMDMODE", 0, 2 },
|
|
{ "LE_DB_DBGI_REQ_TCAM_CMD", 0x19cf4, 0 },
|
|
{ "DBGICMD", 20, 4 },
|
|
{ "DBGITINDEX", 0, 20 },
|
|
{ "LE_PERR_ENABLE", 0x19cf8, 0 },
|
|
{ "ReqQueue", 1, 1 },
|
|
{ "TCAM", 0, 1 },
|
|
{ "LE_SPARE", 0x19cfc, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d2c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d30, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d34, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d38, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d3c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d40, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d7c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d80, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d84, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d88, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d8c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d90, 0 },
|
|
{ "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
|
|
{ "DBGIRspIndex", 12, 20 },
|
|
{ "DBGIRspMsg", 8, 4 },
|
|
{ "DBGIRspMsgVld", 7, 1 },
|
|
{ "DBGIRspMHit", 2, 1 },
|
|
{ "DBGIRspHit", 1, 1 },
|
|
{ "DBGIRspValid", 0, 1 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
|
|
{ "LE_DB_DBGI_RSP_LAST_CMD", 0x19de4, 0 },
|
|
{ "LastCmdB", 16, 11 },
|
|
{ "LastCmdA", 0, 11 },
|
|
{ "LE_DB_DROP_FILTER_ENTRY", 0x19de8, 0 },
|
|
{ "DropFilterEn", 31, 1 },
|
|
{ "DropFilterClear", 17, 1 },
|
|
{ "DropFilterSet", 16, 1 },
|
|
{ "DropFilterFIDX", 0, 13 },
|
|
{ "LE_DB_PTID_SVRBASE", 0x19df0, 0 },
|
|
{ "SVRBASE_ADDR", 2, 18 },
|
|
{ "LE_DB_FTID_FLTRBASE", 0x19df4, 0 },
|
|
{ "FLTRBASE_ADDR", 2, 18 },
|
|
{ "LE_DB_TID_HASHBASE", 0x19df8, 0 },
|
|
{ "HASHBASE_ADDR", 2, 20 },
|
|
{ "LE_PERR_INJECT", 0x19dfc, 0 },
|
|
{ "MemSel", 1, 3 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e14, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e18, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e1c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e20, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e24, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e28, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e2c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e30, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e34, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e38, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e3c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e40, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e70, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e74, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e78, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e7c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e80, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e84, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e88, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e8c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e90, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19eb0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19eb4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19eb8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ebc, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ec0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ee0, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ee4, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ee8, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19eec, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19ef0, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19ef4, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19ef8, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19efc, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f00, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f04, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f08, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f0c, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f10, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f14, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f18, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f1c, 0 },
|
|
{ "LE_DEBUG_LA_CONFIG", 0x19f20, 0 },
|
|
{ "LE_REQ_DEBUG_LA_DATA", 0x19f24, 0 },
|
|
{ "LE_REQ_DEBUG_LA_WRPTR", 0x19f28, 0 },
|
|
{ "LE_RSP_DEBUG_LA_DATA", 0x19f2c, 0 },
|
|
{ "LE_RSP_DEBUG_LA_WRPTR", 0x19f30, 0 },
|
|
{ "LE_DEBUG_LA_SELECTOR", 0x19f34, 0 },
|
|
{ "LE_DEBUG_LA_CAPTURED_DATA", 0x19f38, 0 },
|
|
{ "LE_MA_DEBUG_LA_DATA", 0x19f3c, 0 },
|
|
{ "LE_RSP_DEBUG_LA_HASH_WRPTR", 0x19f40, 0 },
|
|
{ "LE_HASH_DEBUG_LA_DATA", 0x19f44, 0 },
|
|
{ "LE_RSP_DEBUG_LA_TCAM_WRPTR", 0x19f48, 0 },
|
|
{ "LE_TCAM_DEBUG_LA_DATA", 0x19f4c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_ncsi_regs[] = {
|
|
{ "NCSI_PORT_CFGREG", 0x1a000, 0 },
|
|
{ "WireEn", 28, 4 },
|
|
{ "strp_crc", 24, 4 },
|
|
{ "rx_halt", 22, 1 },
|
|
{ "flush_rx_fifo", 21, 1 },
|
|
{ "hw_arb_en", 20, 1 },
|
|
{ "soft_pkg_sel", 19, 1 },
|
|
{ "err_discard_en", 18, 1 },
|
|
{ "max_pkt_size", 4, 14 },
|
|
{ "rx_byte_swap", 3, 1 },
|
|
{ "tx_byte_swap", 2, 1 },
|
|
{ "NCSI_RST_CTRL", 0x1a004, 0 },
|
|
{ "mac_ref_rst", 2, 1 },
|
|
{ "mac_rx_rst", 1, 1 },
|
|
{ "mac_tx_rst", 0, 1 },
|
|
{ "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
|
|
{ "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
|
|
{ "CHO_SADDR_EN", 31, 1 },
|
|
{ "CH0_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
|
|
{ "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
|
|
{ "CH1_SADDR_EN", 31, 1 },
|
|
{ "CH1_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
|
|
{ "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
|
|
{ "CH2_SADDR_EN", 31, 1 },
|
|
{ "CH2_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
|
|
{ "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
|
|
{ "CH3_SADDR_EN", 31, 1 },
|
|
{ "CH3_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
|
|
{ "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
|
|
{ "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
|
|
{ "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
|
|
{ "NCSI_MPS_HDR_LO", 0x1a040, 0 },
|
|
{ "NCSI_MPS_HDR_HI", 0x1a044, 0 },
|
|
{ "NCSI_CTL", 0x1a048, 0 },
|
|
{ "STRIP_OVLAN", 3, 1 },
|
|
{ "bmc_drop_non_bc", 2, 1 },
|
|
{ "bmc_rx_fwd_all", 1, 1 },
|
|
{ "FWD_BMC", 0, 1 },
|
|
{ "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
|
|
{ "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
|
|
{ "NCSI_RX_ERR_CNT", 0x1a054, 0 },
|
|
{ "NCSI_RX_OF_CNT", 0x1a058, 0 },
|
|
{ "NCSI_RX_MS_CNT", 0x1a05c, 0 },
|
|
{ "NCSI_RX_IE_CNT", 0x1a060, 0 },
|
|
{ "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
|
|
{ "MPS2CIM_CNT", 16, 9 },
|
|
{ "MPS2BMC_CNT", 0, 9 },
|
|
{ "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
|
|
{ "CIM2MPS_CNT", 16, 9 },
|
|
{ "CIM2BMC_CNT", 0, 9 },
|
|
{ "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
|
|
{ "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
|
|
{ "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
|
|
{ "NC2MPS_SOP_CNT", 24, 8 },
|
|
{ "NC2MPS_EOP_CNT", 16, 6 },
|
|
{ "MPS2NC_SOP_CNT", 8, 8 },
|
|
{ "MPS2NC_EOP_CNT", 0, 8 },
|
|
{ "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
|
|
{ "NC2CIM_SOP_CNT", 24, 8 },
|
|
{ "NC2CIM_EOP_CNT", 16, 6 },
|
|
{ "CIM2NC_SOP_CNT", 8, 8 },
|
|
{ "CIM2NC_EOP_CNT", 0, 8 },
|
|
{ "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
|
|
{ "SOP_CNT_ERR", 12, 4 },
|
|
{ "BUS_STATE_MPS_OUT", 6, 2 },
|
|
{ "BUS_STATE_MPS_IN", 4, 2 },
|
|
{ "BUS_STATE_CIM_OUT", 2, 2 },
|
|
{ "BUS_STATE_CIM_IN", 0, 2 },
|
|
{ "NCSI_LA_RDPTR", 0x1a0c0, 0 },
|
|
{ "NCSI_LA_RDDATA", 0x1a0c4, 0 },
|
|
{ "NCSI_LA_WRPTR", 0x1a0c8, 0 },
|
|
{ "NCSI_LA_RESERVED", 0x1a0cc, 0 },
|
|
{ "NCSI_LA_CTL", 0x1a0d0, 0 },
|
|
{ "NCSI_INT_ENABLE", 0x1a0d4, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "token", 6, 1 },
|
|
{ "arb_done", 5, 1 },
|
|
{ "arb_started", 4, 1 },
|
|
{ "WOL", 3, 1 },
|
|
{ "MACInt", 2, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_INT_CAUSE", 0x1a0d8, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "token", 6, 1 },
|
|
{ "arb_done", 5, 1 },
|
|
{ "arb_started", 4, 1 },
|
|
{ "WOL", 3, 1 },
|
|
{ "MACInt", 2, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_STATUS", 0x1a0dc, 0 },
|
|
{ "Master", 1, 1 },
|
|
{ "arb_status", 0, 1 },
|
|
{ "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
|
|
{ "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
|
|
{ "NCSI_PAUSE_WM", 0x1a0ec, 0 },
|
|
{ "PauseHWM", 16, 11 },
|
|
{ "PauseLWM", 0, 11 },
|
|
{ "NCSI_DEBUG", 0x1a0f0, 0 },
|
|
{ "NCSI_PERR_INJECT", 0x1a0f4, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
|
|
{ "TxSndZeroPause", 12, 1 },
|
|
{ "TxSndPause", 11, 1 },
|
|
{ "TxStop", 10, 1 },
|
|
{ "TxStart", 9, 1 },
|
|
{ "BackPress", 8, 1 },
|
|
{ "StatWrEn", 7, 1 },
|
|
{ "IncrStat", 6, 1 },
|
|
{ "ClearStat", 5, 1 },
|
|
{ "EnMgmtPort", 4, 1 },
|
|
{ "TxEn", 3, 1 },
|
|
{ "RxEn", 2, 1 },
|
|
{ "LoopLocal", 1, 1 },
|
|
{ "LoopPHY", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
|
|
{ "PClkDiv128", 22, 1 },
|
|
{ "CopyPause", 21, 1 },
|
|
{ "NonStdPreOK", 20, 1 },
|
|
{ "NoFCS", 19, 1 },
|
|
{ "RxEnHalfDup", 18, 1 },
|
|
{ "NoCopyFCS", 17, 1 },
|
|
{ "LenChkEn", 16, 1 },
|
|
{ "RxBufOffset", 14, 2 },
|
|
{ "PauseEn", 13, 1 },
|
|
{ "RetryTest", 12, 1 },
|
|
{ "PClkDiv", 10, 2 },
|
|
{ "ExtClass", 9, 1 },
|
|
{ "En1536Frame", 8, 1 },
|
|
{ "UCastHashEn", 7, 1 },
|
|
{ "MCastHashEn", 6, 1 },
|
|
{ "RxBCastDis", 5, 1 },
|
|
{ "CopyAllFrames", 4, 1 },
|
|
{ "JumboEn", 3, 1 },
|
|
{ "SerEn", 2, 1 },
|
|
{ "FullDuplex", 1, 1 },
|
|
{ "Speed", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
|
|
{ "PHYMgmtStatus", 2, 1 },
|
|
{ "MDIStatus", 1, 1 },
|
|
{ "LinkStatus", 0, 1 },
|
|
{ "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
|
|
{ "UnderrunErr", 6, 1 },
|
|
{ "TxComplete", 5, 1 },
|
|
{ "BufferExhausted", 4, 1 },
|
|
{ "TxProgress", 3, 1 },
|
|
{ "RetryLimit", 2, 1 },
|
|
{ "ColEvent", 1, 1 },
|
|
{ "UsedBitRead", 0, 1 },
|
|
{ "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
|
|
{ "RxBufQPtr", 2, 30 },
|
|
{ "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
|
|
{ "TxBufQPtr", 2, 30 },
|
|
{ "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
|
|
{ "RxOverrunErr", 2, 1 },
|
|
{ "FrameRcvd", 1, 1 },
|
|
{ "NoRxBuf", 0, 1 },
|
|
{ "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_EN", 0x1a128, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_MASK", 0x1a130, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
|
|
{ "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
|
|
{ "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
|
|
{ "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
|
|
{ "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
|
|
{ "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
|
|
{ "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
|
|
{ "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
|
|
{ "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
|
|
{ "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
|
|
{ "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
|
|
{ "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
|
|
{ "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
|
|
{ "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
|
|
{ "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
|
|
{ "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
|
|
{ "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
|
|
{ "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
|
|
{ "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
|
|
{ "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
|
|
{ "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
|
|
{ "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
|
|
{ "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
|
|
{ "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
|
|
{ "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
|
|
{ "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
|
|
{ "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
|
|
{ "UserProgInput", 16, 16 },
|
|
{ "UserProgOutput", 0, 16 },
|
|
{ "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
|
|
{ "MCHashEn", 19, 1 },
|
|
{ "Specific1En", 18, 1 },
|
|
{ "ARPEn", 17, 1 },
|
|
{ "MagicPktEn", 16, 1 },
|
|
{ "ARPIPAddr", 0, 16 },
|
|
{ "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
|
|
{ "PartRef", 16, 16 },
|
|
{ "DesRev", 0, 16 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t4_xgmac_regs[] = {
|
|
{ "XGMAC_PORT_CFG", 0x21000, 0 },
|
|
{ "XGMII_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "xg2g_speed_mode", 25, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "XGM_Tx_pause_size", 23, 1 },
|
|
{ "XGM_Tx_pause_frame", 22, 1 },
|
|
{ "XGM_Tx_Disable_Pre", 21, 1 },
|
|
{ "XGM_Tx_Disable_Crc", 20, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "Pmux_Rx_Loop", 13, 1 },
|
|
{ "Pmux_Tx_Loop", 12, 1 },
|
|
{ "XGM_Rx_Sel", 10, 2 },
|
|
{ "PCS_Tx_Sel", 8, 2 },
|
|
{ "XAUI20_Rem_Pre", 5, 1 },
|
|
{ "XAUI20_XGMII_Sel", 4, 1 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "XGMAC_PORT_RESET_CTRL", 0x21004, 0 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "TXFIFO_Reset", 9, 1 },
|
|
{ "RXFIFO_Reset", 8, 1 },
|
|
{ "BEAN_Reset", 7, 1 },
|
|
{ "XAUI_Reset", 6, 1 },
|
|
{ "AE_Reset", 5, 1 },
|
|
{ "XGM_Reset", 4, 1 },
|
|
{ "XG2G_Reset", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "XFI_PCS_Reset", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "XGMAC_PORT_LED_CFG", 0x21008, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "XGMAC_PORT_LED_COUNTHI", 0x2100c, 0 },
|
|
{ "XGMAC_PORT_LED_COUNTLO", 0x21010, 0 },
|
|
{ "XGMAC_PORT_DEBUG_CFG", 0x21014, 0 },
|
|
{ "XGMAC_PORT_CFG2", 0x21018, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "MACTxEn", 20, 1 },
|
|
{ "MACRxEn", 19, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "TX_IPG", 4, 13 },
|
|
{ "AEC_PMA_TX_READY", 1, 1 },
|
|
{ "AEC_PMA_RX_READY", 0, 1 },
|
|
{ "XGMAC_PORT_PKT_COUNT", 0x2101c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "XGMAC_PORT_PERR_INJECT", 0x21020, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_LO", 0x21024, 0 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_HI", 0x21028, 0 },
|
|
{ "XGMAC_PORT_BUILD_REVISION", 0x2102c, 0 },
|
|
{ "XGMAC_PORT_XGMII_SE_COUNT", 0x21030, 0 },
|
|
{ "TxSop", 24, 8 },
|
|
{ "TxEop", 16, 8 },
|
|
{ "RxSop", 8, 8 },
|
|
{ "RxEop", 0, 8 },
|
|
{ "XGMAC_PORT_LINK_STATUS", 0x21034, 0 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "XGMAC_PORT_CHECKIN", 0x21038, 0 },
|
|
{ "Preamble", 1, 1 },
|
|
{ "CheckIn", 0, 1 },
|
|
{ "XGMAC_PORT_FAULT_TEST", 0x2103c, 0 },
|
|
{ "FltType", 1, 1 },
|
|
{ "FltCtrl", 0, 1 },
|
|
{ "XGMAC_PORT_SPARE", 0x21040, 0 },
|
|
{ "XGMAC_PORT_HSS_SIGDET_STATUS", 0x21044, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_STATUS", 0x21048, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_CTRL", 0x2104c, 0 },
|
|
{ "XGMAC_PORT_FPGA_PAUSE_CTL", 0x21050, 0 },
|
|
{ "CTL", 31, 1 },
|
|
{ "HWM", 13, 13 },
|
|
{ "LWM", 0, 13 },
|
|
{ "XGMAC_PORT_FPGA_ERRPKT_CNT", 0x21054, 0 },
|
|
{ "XGMAC_PORT_LA_TX_0", 0x21058, 0 },
|
|
{ "XGMAC_PORT_LA_RX_0", 0x2105c, 0 },
|
|
{ "XGMAC_PORT_FPGA_LA_CTL", 0x21060, 0 },
|
|
{ "rxrst", 5, 1 },
|
|
{ "txrst", 4, 1 },
|
|
{ "xgmii", 3, 1 },
|
|
{ "pause", 2, 1 },
|
|
{ "stopErr", 1, 1 },
|
|
{ "stop", 0, 1 },
|
|
{ "XGMAC_PORT_EPIO_DATA0", 0x210c0, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA1", 0x210c4, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA2", 0x210c8, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA3", 0x210cc, 0 },
|
|
{ "XGMAC_PORT_EPIO_OP", 0x210d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "XGMAC_PORT_WOL_STATUS", 0x210d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "XGMAC_PORT_INT_EN", 0x210d8, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_INT_CAUSE", 0x210dc, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG0", 0x210e0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKSEL", 20, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRXTS", 16, 1 },
|
|
{ "HSSTXACMODE", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRESYNC", 13, 1 },
|
|
{ "HSSRECCAL", 12, 1 },
|
|
{ "HSSPDWNPLL", 11, 1 },
|
|
{ "HSSDIVSEL", 9, 2 },
|
|
{ "HSSREFDIV", 8, 1 },
|
|
{ "HSSPLLBYP", 7, 1 },
|
|
{ "HSSLOFREQPLL", 6, 1 },
|
|
{ "HSSLOFREQ2PLL", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "HSSRSTCONFIG", 1, 3 },
|
|
{ "HSSPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG1", 0x210e4, 0 },
|
|
{ "RXDPRBSRST", 28, 1 },
|
|
{ "RXDPRBSEN", 27, 1 },
|
|
{ "RXDPRBSFRCERR", 26, 1 },
|
|
{ "TXDPRBSRST", 25, 1 },
|
|
{ "TXDPRBSEN", 24, 1 },
|
|
{ "RXCPRBSRST", 20, 1 },
|
|
{ "RXCPRBSEN", 19, 1 },
|
|
{ "RXCPRBSFRCERR", 18, 1 },
|
|
{ "TXCPRBSRST", 17, 1 },
|
|
{ "TXCPRBSEN", 16, 1 },
|
|
{ "RXBPRBSRST", 12, 1 },
|
|
{ "RXBPRBSEN", 11, 1 },
|
|
{ "RXBPRBSFRCERR", 10, 1 },
|
|
{ "TXBPRBSRST", 9, 1 },
|
|
{ "TXBPRBSEN", 8, 1 },
|
|
{ "RXAPRBSRST", 4, 1 },
|
|
{ "RXAPRBSEN", 3, 1 },
|
|
{ "RXAPRBSFRCERR", 2, 1 },
|
|
{ "TXAPRBSRST", 1, 1 },
|
|
{ "TXAPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG2", 0x210e8, 0 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_STATUS", 0x210ec, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCK", 1, 1 },
|
|
{ "HSSPRTREADY", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CTRL", 0x21200, 0 },
|
|
{ "SendPause", 2, 1 },
|
|
{ "SendZeroPause", 1, 1 },
|
|
{ "TxEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CFG", 0x21204, 0 },
|
|
{ "CRCCal", 8, 2 },
|
|
{ "DisDefIdleCnt", 7, 1 },
|
|
{ "DecAvgTxIPG", 6, 1 },
|
|
{ "UnidirTxEn", 5, 1 },
|
|
{ "CfgClkSpeed", 2, 3 },
|
|
{ "StretchMode", 1, 1 },
|
|
{ "TxPauseEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_QUANTA", 0x21208, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CTRL", 0x2120c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CFG", 0x21210, 0 },
|
|
{ "CRCCal", 16, 2 },
|
|
{ "LocalFault", 15, 1 },
|
|
{ "RemoteFault", 14, 1 },
|
|
{ "LenErrFrameDis", 13, 1 },
|
|
{ "Con802_3Preamble", 12, 1 },
|
|
{ "EnNon802_3Preamble", 11, 1 },
|
|
{ "CopyPreamble", 10, 1 },
|
|
{ "DisPauseFrames", 9, 1 },
|
|
{ "En1536BFrames", 8, 1 },
|
|
{ "EnJumbo", 7, 1 },
|
|
{ "RmFCS", 6, 1 },
|
|
{ "DisNonVlan", 5, 1 },
|
|
{ "EnExtMatch", 4, 1 },
|
|
{ "EnHashUcast", 3, 1 },
|
|
{ "EnHashMcast", 2, 1 },
|
|
{ "DisBCast", 1, 1 },
|
|
{ "CopyAllFrames", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_LOW", 0x21214, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_HIGH", 0x21218, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1", 0x2121c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1", 0x21220, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2", 0x21224, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2", 0x21228, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3", 0x2122c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3", 0x21230, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4", 0x21234, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4", 0x21238, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5", 0x2123c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5", 0x21240, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6", 0x21244, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6", 0x21248, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7", 0x2124c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7", 0x21250, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8", 0x21254, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8", 0x21258, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_1", 0x2125c, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_2", 0x21260, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_3", 0x21264, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_4", 0x21268, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_INT_STATUS", 0x2126c, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_MASK", 0x21270, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_EN", 0x21274, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_DISABLE", 0x21278, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_TIMER", 0x2127c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_CTRL", 0x21280, 0 },
|
|
{ "ReadSnpShot", 4, 1 },
|
|
{ "TakeSnpShot", 3, 1 },
|
|
{ "ClrStats", 2, 1 },
|
|
{ "IncrStats", 1, 1 },
|
|
{ "EnTestModeWr", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_MDIO_CTRL", 0x21284, 0 },
|
|
{ "FrameType", 30, 2 },
|
|
{ "Operation", 28, 2 },
|
|
{ "PortAddr", 23, 5 },
|
|
{ "DevAddr", 18, 5 },
|
|
{ "Resrv", 16, 2 },
|
|
{ "Data", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_MODULE_ID", 0x212fc, 0 },
|
|
{ "ModuleID", 16, 16 },
|
|
{ "ModuleRev", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_LOW", 0x21300, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH", 0x21304, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_LOW", 0x21308, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH", 0x2130c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BCAST", 0x21310, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_MCAST", 0x21314, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_PAUSE", 0x21318, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_64B_FRAMES", 0x2131c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES", 0x21320, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES", 0x21324, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES", 0x21328, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES", 0x2132c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES", 0x21330, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES", 0x21334, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES", 0x21338, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_LOW", 0x2133c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH", 0x21340, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW", 0x21344, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH", 0x21348, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES", 0x2134c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES", 0x21350, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES", 0x21354, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_64B_FRAMES", 0x21358, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES", 0x2135c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES", 0x21360, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES", 0x21364, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES", 0x21368, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES", 0x2136c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES", 0x21370, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES", 0x21374, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES", 0x21378, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES", 0x2137c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES", 0x21380, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES", 0x21384, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES", 0x21388, 0 },
|
|
{ "XGMAC_PORT_XAUI_CTRL", 0x21400, 0 },
|
|
{ "polarity_inv_rx", 8, 4 },
|
|
{ "polarity_inv_tx", 4, 4 },
|
|
{ "test_sel", 2, 2 },
|
|
{ "test_en", 0, 1 },
|
|
{ "XGMAC_PORT_XAUI_STATUS", 0x21404, 0 },
|
|
{ "Decode_Error", 12, 8 },
|
|
{ "Lane3_CTC_Status", 11, 1 },
|
|
{ "Lane2_CTC_Status", 10, 1 },
|
|
{ "Lane1_CTC_Status", 9, 1 },
|
|
{ "Lane0_CTC_Status", 8, 1 },
|
|
{ "Align_Status", 4, 1 },
|
|
{ "Lane3_Sync_Status", 3, 1 },
|
|
{ "Lane2_Sync_Status", 2, 1 },
|
|
{ "Lane1_Sync_Status", 1, 1 },
|
|
{ "Lane0_Sync_Status", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_CTRL", 0x21500, 0 },
|
|
{ "rx_clk_speed", 7, 1 },
|
|
{ "ScrBypass", 6, 1 },
|
|
{ "FECErrIndEn", 5, 1 },
|
|
{ "FECEn", 4, 1 },
|
|
{ "TestSel", 2, 2 },
|
|
{ "ScrLoopEn", 1, 1 },
|
|
{ "XGMIILoopEn", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_CTRL", 0x21510, 0 },
|
|
{ "tx_prbs9_en", 4, 1 },
|
|
{ "tx_prbs31_en", 3, 1 },
|
|
{ "tx_tst_dat_sel", 2, 1 },
|
|
{ "tx_tst_sel", 1, 1 },
|
|
{ "tx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER", 0x21514, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER", 0x21518, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER", 0x2152c, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER", 0x21530, 0 },
|
|
{ "XGMAC_PORT_PCSR_RXTEST_CTRL", 0x2153c, 0 },
|
|
{ "tpter_cnt_rst", 7, 1 },
|
|
{ "test_cnt_125us", 6, 1 },
|
|
{ "test_cnt_pre", 5, 1 },
|
|
{ "ber_cnt_rst", 4, 1 },
|
|
{ "err_blk_cnt_rst", 3, 1 },
|
|
{ "rx_prbs31_en", 2, 1 },
|
|
{ "rx_tst_dat_sel", 1, 1 },
|
|
{ "rx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_STATUS", 0x21550, 0 },
|
|
{ "err_blk_cnt", 16, 8 },
|
|
{ "ber_count", 8, 6 },
|
|
{ "hi_ber", 2, 1 },
|
|
{ "rx_fault", 1, 1 },
|
|
{ "tx_fault", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TEST_STATUS", 0x21554, 0 },
|
|
{ "XGMAC_PORT_AN_CONTROL", 0x21600, 0 },
|
|
{ "soft_reset", 15, 1 },
|
|
{ "an_enable", 12, 1 },
|
|
{ "restart_an", 9, 1 },
|
|
{ "XGMAC_PORT_AN_STATUS", 0x21604, 0 },
|
|
{ "Noncer_Match", 31, 1 },
|
|
{ "Parallel_Det_Fault", 9, 1 },
|
|
{ "Page_Received", 6, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "Remote_Fault", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "link_status", 2, 1 },
|
|
{ "partner_an_ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_ADVERTISEMENT", 0x21608, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "XGMAC_PORT_AN_LINK_PARTNER_ABILITY", 0x2160c, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "Selector_Field", 0, 5 },
|
|
{ "XGMAC_PORT_AN_NP_LOWER_TRANSMIT", 0x21610, 0 },
|
|
{ "NP_Info", 16, 16 },
|
|
{ "NP_Indication", 15, 1 },
|
|
{ "Message_Page", 13, 1 },
|
|
{ "ACK_2", 12, 1 },
|
|
{ "Toggle", 11, 1 },
|
|
{ "XGMAC_PORT_AN_NP_UPPER_TRANSMIT", 0x21614, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_LOWER", 0x21618, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_UPPER", 0x2161c, 0 },
|
|
{ "XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS", 0x21624, 0 },
|
|
{ "TX_Pause_Okay", 6, 1 },
|
|
{ "RX_Pause_Okay", 5, 1 },
|
|
{ "10GBASE_KR_FEC_neg", 4, 1 },
|
|
{ "10GBASE_KR_neg", 3, 1 },
|
|
{ "10GBASE_KX4_neg", 2, 1 },
|
|
{ "1000BASE_KX_neg", 1, 1 },
|
|
{ "BP_AN_Ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_TX_NONCE_CONTROL", 0x21628, 0 },
|
|
{ "Bypass_LFSR", 15, 1 },
|
|
{ "LFSR_Init", 0, 15 },
|
|
{ "XGMAC_PORT_AN_INTERRUPT_STATUS", 0x2162c, 0 },
|
|
{ "NP_From_LP", 3, 1 },
|
|
{ "Parallel_Det_Fault", 2, 1 },
|
|
{ "BP_From_LP", 1, 1 },
|
|
{ "PCS_AN_Complete", 0, 1 },
|
|
{ "XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT", 0x21630, 0 },
|
|
{ "XGMAC_PORT_AN_BREAK_LINK_TIMEOUT", 0x21634, 0 },
|
|
{ "XGMAC_PORT_AN_MODULE_ID", 0x2163c, 0 },
|
|
{ "Module_ID", 16, 16 },
|
|
{ "Module_Revision", 0, 16 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_REQ", 0x21700, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "RXREQ_C0", 4, 2 },
|
|
{ "RXREQ_C1", 2, 2 },
|
|
{ "RXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_STAT", 0x21704, 0 },
|
|
{ "RXSTAT_RDY", 15, 1 },
|
|
{ "RXSTAT_C0", 4, 2 },
|
|
{ "RXSTAT_C1", 2, 2 },
|
|
{ "RXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_REQ", 0x21708, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_C0", 4, 2 },
|
|
{ "TXREQ_C1", 2, 2 },
|
|
{ "TXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_STAT", 0x2170c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "TXSTAT_C0", 4, 2 },
|
|
{ "TXSTAT_C1", 2, 2 },
|
|
{ "TXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_REG_MODE", 0x21710, 0 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "XGMAC_PORT_AE_PRBS_CTL", 0x21714, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_CTL", 0x21718, 0 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_STATE", 0x2171c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "XGMAC_PORT_AE_TX_DIS", 0x21780, 0 },
|
|
{ "XGMAC_PORT_AE_KR_CTRL", 0x21784, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "XGMAC_PORT_AE_RX_SIGDET", 0x21788, 0 },
|
|
{ "XGMAC_PORT_AE_KR_STATUS", 0x2178c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_MODE_CFG", 0x21800, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TEST_CTRL", 0x21804, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_COEFF_CTRL", 0x21808, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_MODE", 0x2180c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL", 0x21810, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER", 0x21814, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER", 0x21818, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_COEFF", 0x21820, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_COEFF", 0x21824, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_COEFF", 0x21828, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR", 0x21830, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_POLARITY", 0x21834, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_CMD", 0x21838, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS", 0x2183c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR", 0x21840, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR", 0x21844, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR", 0x21848, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC_OVR", 0x21850, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC", 0x21854, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP", 0x21860, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP", 0x21864, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP", 0x21868, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_SEG_DIS_APP", 0x21870, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA", 0x21878, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR", 0x2187c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_MODE_CFG", 0x21880, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TEST_CTRL", 0x21884, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_COEFF_CTRL", 0x21888, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_MODE", 0x2188c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL", 0x21890, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER", 0x21894, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER", 0x21898, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_COEFF", 0x218a0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_COEFF", 0x218a4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_COEFF", 0x218a8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR", 0x218b0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_POLARITY", 0x218b4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_CMD", 0x218b8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS", 0x218bc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR", 0x218c0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR", 0x218c4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR", 0x218c8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC_OVR", 0x218d0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC", 0x218d4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP", 0x218e0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP", 0x218e4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP", 0x218e8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_SEG_DIS_APP", 0x218f0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA", 0x218f8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR", 0x218fc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_CFG_MODE", 0x21900, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXA_TEST_CTRL", 0x21904, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL", 0x21908, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL", 0x2190c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1", 0x21910, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2", 0x21914, 0 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET", 0x21918, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_SIGDET_CTRL", 0x2191c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_CTRL", 0x21920, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE", 0x21924, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE", 0x21928, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL1", 0x2192c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL2", 0x21930, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL3", 0x21934, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET", 0x21938, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET", 0x2193c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET", 0x21940, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_OFFSET", 0x21944, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET", 0x21948, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_MIN", 0x2194c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_ADAC_CTRL", 0x21950, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL", 0x21954, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS", 0x21958, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H1", 0x2195c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H2", 0x21960, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H3", 0x21964, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H4", 0x21968, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H5", 0x2196c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DAC_DPC", 0x21970, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DDC", 0x21974, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_INTERNAL_STATUS", 0x21978, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL", 0x2197c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_CFG_MODE", 0x21980, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXB_TEST_CTRL", 0x21984, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL", 0x21988, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL", 0x2198c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1", 0x21990, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2", 0x21994, 0 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET", 0x21998, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_SIGDET_CTRL", 0x2199c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_CTRL", 0x219a0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE", 0x219a4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE", 0x219a8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL1", 0x219ac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL2", 0x219b0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL3", 0x219b4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET", 0x219b8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET", 0x219bc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET", 0x219c0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_OFFSET", 0x219c4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET", 0x219c8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_MIN", 0x219cc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_ADAC_CTRL", 0x219d0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL", 0x219d4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS", 0x219d8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H1", 0x219dc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H2", 0x219e0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H3", 0x219e4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H4", 0x219e8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H5", 0x219ec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DAC_DPC", 0x219f0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DDC", 0x219f4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_INTERNAL_STATUS", 0x219f8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL", 0x219fc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_MODE_CFG", 0x21a00, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TEST_CTRL", 0x21a04, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_COEFF_CTRL", 0x21a08, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_MODE", 0x21a0c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL", 0x21a10, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER", 0x21a14, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER", 0x21a18, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_COEFF", 0x21a20, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_COEFF", 0x21a24, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_COEFF", 0x21a28, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR", 0x21a30, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_POLARITY", 0x21a34, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_CMD", 0x21a38, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS", 0x21a3c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR", 0x21a40, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR", 0x21a44, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR", 0x21a48, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC_OVR", 0x21a50, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC", 0x21a54, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP", 0x21a60, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP", 0x21a64, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP", 0x21a68, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_SEG_DIS_APP", 0x21a70, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA", 0x21a78, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR", 0x21a7c, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_MODE_CFG", 0x21a80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TEST_CTRL", 0x21a84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_COEFF_CTRL", 0x21a88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_MODE", 0x21a8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL", 0x21a90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER", 0x21a94, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER", 0x21a98, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_COEFF", 0x21aa0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_COEFF", 0x21aa4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_COEFF", 0x21aa8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR", 0x21ab0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_POLARITY", 0x21ab4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_CMD", 0x21ab8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS", 0x21abc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR", 0x21ac0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR", 0x21ac4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR", 0x21ac8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC_OVR", 0x21ad0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC", 0x21ad4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP", 0x21ae0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP", 0x21ae4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP", 0x21ae8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_SEG_DIS_APP", 0x21af0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA", 0x21af8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR", 0x21afc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_CFG_MODE", 0x21b00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXC_TEST_CTRL", 0x21b04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL", 0x21b08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL", 0x21b0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1", 0x21b10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2", 0x21b14, 0 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET", 0x21b18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_SIGDET_CTRL", 0x21b1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_CTRL", 0x21b20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE", 0x21b24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE", 0x21b28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL1", 0x21b2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL2", 0x21b30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL3", 0x21b34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET", 0x21b38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET", 0x21b3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET", 0x21b40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_OFFSET", 0x21b44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET", 0x21b48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_MIN", 0x21b4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_ADAC_CTRL", 0x21b50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL", 0x21b54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS", 0x21b58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H1", 0x21b5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H2", 0x21b60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H3", 0x21b64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H4", 0x21b68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H5", 0x21b6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DAC_DPC", 0x21b70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DDC", 0x21b74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_INTERNAL_STATUS", 0x21b78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL", 0x21b7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_CFG_MODE", 0x21b80, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXD_TEST_CTRL", 0x21b84, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL", 0x21b88, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL", 0x21b8c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1", 0x21b90, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2", 0x21b94, 0 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET", 0x21b98, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_SIGDET_CTRL", 0x21b9c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_CTRL", 0x21ba0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE", 0x21ba4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE", 0x21ba8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL1", 0x21bac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL2", 0x21bb0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL3", 0x21bb4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET", 0x21bb8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET", 0x21bbc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET", 0x21bc0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_OFFSET", 0x21bc4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET", 0x21bc8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_MIN", 0x21bcc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_ADAC_CTRL", 0x21bd0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL", 0x21bd4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS", 0x21bd8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H1", 0x21bdc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H2", 0x21be0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H3", 0x21be4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H4", 0x21be8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H5", 0x21bec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DAC_DPC", 0x21bf0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DDC", 0x21bf4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_INTERNAL_STATUS", 0x21bf8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL", 0x21bfc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0", 0x21c00, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1", 0x21c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2", 0x21c08, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3", 0x21c0c, 0 },
|
|
{ "VISEL", 4, 1 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "TCDIS", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4", 0x21c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_ANALOG_TEST_MUX", 0x21c14, 0 },
|
|
{ "XGMAC_PORT_HSS_PORT_EN_0", 0x21c18, 0 },
|
|
{ "RXDEN", 7, 1 },
|
|
{ "RXCEN", 6, 1 },
|
|
{ "TXDEN", 5, 1 },
|
|
{ "TXCEN", 4, 1 },
|
|
{ "RXBEN", 3, 1 },
|
|
{ "RXAEN", 2, 1 },
|
|
{ "TXBEN", 1, 1 },
|
|
{ "TXAEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_PORT_RESET_0", 0x21c20, 0 },
|
|
{ "RXDRST", 7, 1 },
|
|
{ "RXCRST", 6, 1 },
|
|
{ "TXDRST", 5, 1 },
|
|
{ "TXCRST", 4, 1 },
|
|
{ "RXBRST", 3, 1 },
|
|
{ "RXARST", 2, 1 },
|
|
{ "TXBRST", 1, 1 },
|
|
{ "TXARST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CHARGE_PUMP_CTRL", 0x21c28, 0 },
|
|
{ "ENCPIS", 2, 1 },
|
|
{ "CPISEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_BAND_GAP_CTRL", 0x21c2c, 0 },
|
|
{ "XGMAC_PORT_HSS_LOFREQ_OVR", 0x21c30, 0 },
|
|
{ "LFREQ2", 3, 1 },
|
|
{ "LFREQ1", 2, 1 },
|
|
{ "LFREQO", 1, 1 },
|
|
{ "LFSEL", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL", 0x21c38, 0 },
|
|
{ "PFVAL", 2, 1 },
|
|
{ "PFEN", 1, 1 },
|
|
{ "VBADJ", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_MODE_CFG", 0x21c80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXTEST_CTRL", 0x21c84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_COEFF_CTRL", 0x21c88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_MODE", 0x21c8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL", 0x21c90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER", 0x21c94, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER", 0x21c98, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_COEFF", 0x21ca0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_COEFF", 0x21ca4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_COEFF", 0x21ca8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR", 0x21cb0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_POLARITY", 0x21cb4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_CMD", 0x21cb8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_STATUS", 0x21cbc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR", 0x21cc0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR", 0x21cc4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR", 0x21cc8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC_OVR", 0x21cd0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC", 0x21cd4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_APP", 0x21ce0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_APP", 0x21ce4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_APP", 0x21ce8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_SEG_DIS_APP", 0x21cf0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR_DATA", 0x21cf8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR", 0x21cfc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_CFG_MODE", 0x21d00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXTEST_CTRL", 0x21d04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL", 0x21d08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL", 0x21d0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1", 0x21d10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2", 0x21d14, 0 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET", 0x21d18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_SIGDET_CTRL", 0x21d1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_CTRL", 0x21d20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE", 0x21d24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE", 0x21d28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL1", 0x21d2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL2", 0x21d30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL3", 0x21d34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET", 0x21d38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET", 0x21d3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET", 0x21d40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_OFFSET", 0x21d44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET", 0x21d48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_MIN", 0x21d4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_ADAC_CTRL", 0x21d50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL", 0x21d54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS", 0x21d58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H1", 0x21d5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H2", 0x21d60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H3", 0x21d64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H4", 0x21d68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H5", 0x21d6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DAC_DPC", 0x21d70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DDC", 0x21d74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_INTERNAL_STATUS", 0x21d78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL", 0x21d7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXRX_CFG_MODE", 0x21e00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXRXTEST_CTRL", 0x21e04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_CFG", 0x23000, 0 },
|
|
{ "XGMII_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "xg2g_speed_mode", 25, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "XGM_Tx_pause_size", 23, 1 },
|
|
{ "XGM_Tx_pause_frame", 22, 1 },
|
|
{ "XGM_Tx_Disable_Pre", 21, 1 },
|
|
{ "XGM_Tx_Disable_Crc", 20, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "Pmux_Rx_Loop", 13, 1 },
|
|
{ "Pmux_Tx_Loop", 12, 1 },
|
|
{ "XGM_Rx_Sel", 10, 2 },
|
|
{ "PCS_Tx_Sel", 8, 2 },
|
|
{ "XAUI20_Rem_Pre", 5, 1 },
|
|
{ "XAUI20_XGMII_Sel", 4, 1 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "XGMAC_PORT_RESET_CTRL", 0x23004, 0 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "TXFIFO_Reset", 9, 1 },
|
|
{ "RXFIFO_Reset", 8, 1 },
|
|
{ "BEAN_Reset", 7, 1 },
|
|
{ "XAUI_Reset", 6, 1 },
|
|
{ "AE_Reset", 5, 1 },
|
|
{ "XGM_Reset", 4, 1 },
|
|
{ "XG2G_Reset", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "XFI_PCS_Reset", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "XGMAC_PORT_LED_CFG", 0x23008, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "XGMAC_PORT_LED_COUNTHI", 0x2300c, 0 },
|
|
{ "XGMAC_PORT_LED_COUNTLO", 0x23010, 0 },
|
|
{ "XGMAC_PORT_DEBUG_CFG", 0x23014, 0 },
|
|
{ "XGMAC_PORT_CFG2", 0x23018, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "MACTxEn", 20, 1 },
|
|
{ "MACRxEn", 19, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "TX_IPG", 4, 13 },
|
|
{ "AEC_PMA_TX_READY", 1, 1 },
|
|
{ "AEC_PMA_RX_READY", 0, 1 },
|
|
{ "XGMAC_PORT_PKT_COUNT", 0x2301c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "XGMAC_PORT_PERR_INJECT", 0x23020, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_LO", 0x23024, 0 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_HI", 0x23028, 0 },
|
|
{ "XGMAC_PORT_BUILD_REVISION", 0x2302c, 0 },
|
|
{ "XGMAC_PORT_XGMII_SE_COUNT", 0x23030, 0 },
|
|
{ "TxSop", 24, 8 },
|
|
{ "TxEop", 16, 8 },
|
|
{ "RxSop", 8, 8 },
|
|
{ "RxEop", 0, 8 },
|
|
{ "XGMAC_PORT_LINK_STATUS", 0x23034, 0 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "XGMAC_PORT_CHECKIN", 0x23038, 0 },
|
|
{ "Preamble", 1, 1 },
|
|
{ "CheckIn", 0, 1 },
|
|
{ "XGMAC_PORT_FAULT_TEST", 0x2303c, 0 },
|
|
{ "FltType", 1, 1 },
|
|
{ "FltCtrl", 0, 1 },
|
|
{ "XGMAC_PORT_SPARE", 0x23040, 0 },
|
|
{ "XGMAC_PORT_HSS_SIGDET_STATUS", 0x23044, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_STATUS", 0x23048, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_CTRL", 0x2304c, 0 },
|
|
{ "XGMAC_PORT_FPGA_PAUSE_CTL", 0x23050, 0 },
|
|
{ "CTL", 31, 1 },
|
|
{ "HWM", 13, 13 },
|
|
{ "LWM", 0, 13 },
|
|
{ "XGMAC_PORT_FPGA_ERRPKT_CNT", 0x23054, 0 },
|
|
{ "XGMAC_PORT_LA_TX_0", 0x23058, 0 },
|
|
{ "XGMAC_PORT_LA_RX_0", 0x2305c, 0 },
|
|
{ "XGMAC_PORT_FPGA_LA_CTL", 0x23060, 0 },
|
|
{ "rxrst", 5, 1 },
|
|
{ "txrst", 4, 1 },
|
|
{ "xgmii", 3, 1 },
|
|
{ "pause", 2, 1 },
|
|
{ "stopErr", 1, 1 },
|
|
{ "stop", 0, 1 },
|
|
{ "XGMAC_PORT_EPIO_DATA0", 0x230c0, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA1", 0x230c4, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA2", 0x230c8, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA3", 0x230cc, 0 },
|
|
{ "XGMAC_PORT_EPIO_OP", 0x230d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "XGMAC_PORT_WOL_STATUS", 0x230d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "XGMAC_PORT_INT_EN", 0x230d8, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_INT_CAUSE", 0x230dc, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG0", 0x230e0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKSEL", 20, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRXTS", 16, 1 },
|
|
{ "HSSTXACMODE", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRESYNC", 13, 1 },
|
|
{ "HSSRECCAL", 12, 1 },
|
|
{ "HSSPDWNPLL", 11, 1 },
|
|
{ "HSSDIVSEL", 9, 2 },
|
|
{ "HSSREFDIV", 8, 1 },
|
|
{ "HSSPLLBYP", 7, 1 },
|
|
{ "HSSLOFREQPLL", 6, 1 },
|
|
{ "HSSLOFREQ2PLL", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "HSSRSTCONFIG", 1, 3 },
|
|
{ "HSSPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG1", 0x230e4, 0 },
|
|
{ "RXDPRBSRST", 28, 1 },
|
|
{ "RXDPRBSEN", 27, 1 },
|
|
{ "RXDPRBSFRCERR", 26, 1 },
|
|
{ "TXDPRBSRST", 25, 1 },
|
|
{ "TXDPRBSEN", 24, 1 },
|
|
{ "RXCPRBSRST", 20, 1 },
|
|
{ "RXCPRBSEN", 19, 1 },
|
|
{ "RXCPRBSFRCERR", 18, 1 },
|
|
{ "TXCPRBSRST", 17, 1 },
|
|
{ "TXCPRBSEN", 16, 1 },
|
|
{ "RXBPRBSRST", 12, 1 },
|
|
{ "RXBPRBSEN", 11, 1 },
|
|
{ "RXBPRBSFRCERR", 10, 1 },
|
|
{ "TXBPRBSRST", 9, 1 },
|
|
{ "TXBPRBSEN", 8, 1 },
|
|
{ "RXAPRBSRST", 4, 1 },
|
|
{ "RXAPRBSEN", 3, 1 },
|
|
{ "RXAPRBSFRCERR", 2, 1 },
|
|
{ "TXAPRBSRST", 1, 1 },
|
|
{ "TXAPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG2", 0x230e8, 0 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_STATUS", 0x230ec, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCK", 1, 1 },
|
|
{ "HSSPRTREADY", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CTRL", 0x23200, 0 },
|
|
{ "SendPause", 2, 1 },
|
|
{ "SendZeroPause", 1, 1 },
|
|
{ "TxEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CFG", 0x23204, 0 },
|
|
{ "CRCCal", 8, 2 },
|
|
{ "DisDefIdleCnt", 7, 1 },
|
|
{ "DecAvgTxIPG", 6, 1 },
|
|
{ "UnidirTxEn", 5, 1 },
|
|
{ "CfgClkSpeed", 2, 3 },
|
|
{ "StretchMode", 1, 1 },
|
|
{ "TxPauseEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_QUANTA", 0x23208, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CTRL", 0x2320c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CFG", 0x23210, 0 },
|
|
{ "CRCCal", 16, 2 },
|
|
{ "LocalFault", 15, 1 },
|
|
{ "RemoteFault", 14, 1 },
|
|
{ "LenErrFrameDis", 13, 1 },
|
|
{ "Con802_3Preamble", 12, 1 },
|
|
{ "EnNon802_3Preamble", 11, 1 },
|
|
{ "CopyPreamble", 10, 1 },
|
|
{ "DisPauseFrames", 9, 1 },
|
|
{ "En1536BFrames", 8, 1 },
|
|
{ "EnJumbo", 7, 1 },
|
|
{ "RmFCS", 6, 1 },
|
|
{ "DisNonVlan", 5, 1 },
|
|
{ "EnExtMatch", 4, 1 },
|
|
{ "EnHashUcast", 3, 1 },
|
|
{ "EnHashMcast", 2, 1 },
|
|
{ "DisBCast", 1, 1 },
|
|
{ "CopyAllFrames", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_LOW", 0x23214, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_HIGH", 0x23218, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1", 0x2321c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1", 0x23220, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2", 0x23224, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2", 0x23228, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3", 0x2322c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3", 0x23230, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4", 0x23234, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4", 0x23238, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5", 0x2323c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5", 0x23240, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6", 0x23244, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6", 0x23248, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7", 0x2324c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7", 0x23250, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8", 0x23254, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8", 0x23258, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_1", 0x2325c, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_2", 0x23260, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_3", 0x23264, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_4", 0x23268, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_INT_STATUS", 0x2326c, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_MASK", 0x23270, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_EN", 0x23274, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_DISABLE", 0x23278, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_TIMER", 0x2327c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_CTRL", 0x23280, 0 },
|
|
{ "ReadSnpShot", 4, 1 },
|
|
{ "TakeSnpShot", 3, 1 },
|
|
{ "ClrStats", 2, 1 },
|
|
{ "IncrStats", 1, 1 },
|
|
{ "EnTestModeWr", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_MDIO_CTRL", 0x23284, 0 },
|
|
{ "FrameType", 30, 2 },
|
|
{ "Operation", 28, 2 },
|
|
{ "PortAddr", 23, 5 },
|
|
{ "DevAddr", 18, 5 },
|
|
{ "Resrv", 16, 2 },
|
|
{ "Data", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_MODULE_ID", 0x232fc, 0 },
|
|
{ "ModuleID", 16, 16 },
|
|
{ "ModuleRev", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_LOW", 0x23300, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH", 0x23304, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_LOW", 0x23308, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH", 0x2330c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BCAST", 0x23310, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_MCAST", 0x23314, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_PAUSE", 0x23318, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_64B_FRAMES", 0x2331c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES", 0x23320, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES", 0x23324, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES", 0x23328, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES", 0x2332c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES", 0x23330, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES", 0x23334, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES", 0x23338, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_LOW", 0x2333c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH", 0x23340, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW", 0x23344, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH", 0x23348, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES", 0x2334c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES", 0x23350, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES", 0x23354, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_64B_FRAMES", 0x23358, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES", 0x2335c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES", 0x23360, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES", 0x23364, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES", 0x23368, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES", 0x2336c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES", 0x23370, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES", 0x23374, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES", 0x23378, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES", 0x2337c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES", 0x23380, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES", 0x23384, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES", 0x23388, 0 },
|
|
{ "XGMAC_PORT_XAUI_CTRL", 0x23400, 0 },
|
|
{ "polarity_inv_rx", 8, 4 },
|
|
{ "polarity_inv_tx", 4, 4 },
|
|
{ "test_sel", 2, 2 },
|
|
{ "test_en", 0, 1 },
|
|
{ "XGMAC_PORT_XAUI_STATUS", 0x23404, 0 },
|
|
{ "Decode_Error", 12, 8 },
|
|
{ "Lane3_CTC_Status", 11, 1 },
|
|
{ "Lane2_CTC_Status", 10, 1 },
|
|
{ "Lane1_CTC_Status", 9, 1 },
|
|
{ "Lane0_CTC_Status", 8, 1 },
|
|
{ "Align_Status", 4, 1 },
|
|
{ "Lane3_Sync_Status", 3, 1 },
|
|
{ "Lane2_Sync_Status", 2, 1 },
|
|
{ "Lane1_Sync_Status", 1, 1 },
|
|
{ "Lane0_Sync_Status", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_CTRL", 0x23500, 0 },
|
|
{ "rx_clk_speed", 7, 1 },
|
|
{ "ScrBypass", 6, 1 },
|
|
{ "FECErrIndEn", 5, 1 },
|
|
{ "FECEn", 4, 1 },
|
|
{ "TestSel", 2, 2 },
|
|
{ "ScrLoopEn", 1, 1 },
|
|
{ "XGMIILoopEn", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_CTRL", 0x23510, 0 },
|
|
{ "tx_prbs9_en", 4, 1 },
|
|
{ "tx_prbs31_en", 3, 1 },
|
|
{ "tx_tst_dat_sel", 2, 1 },
|
|
{ "tx_tst_sel", 1, 1 },
|
|
{ "tx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER", 0x23514, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER", 0x23518, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER", 0x2352c, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER", 0x23530, 0 },
|
|
{ "XGMAC_PORT_PCSR_RXTEST_CTRL", 0x2353c, 0 },
|
|
{ "tpter_cnt_rst", 7, 1 },
|
|
{ "test_cnt_125us", 6, 1 },
|
|
{ "test_cnt_pre", 5, 1 },
|
|
{ "ber_cnt_rst", 4, 1 },
|
|
{ "err_blk_cnt_rst", 3, 1 },
|
|
{ "rx_prbs31_en", 2, 1 },
|
|
{ "rx_tst_dat_sel", 1, 1 },
|
|
{ "rx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_STATUS", 0x23550, 0 },
|
|
{ "err_blk_cnt", 16, 8 },
|
|
{ "ber_count", 8, 6 },
|
|
{ "hi_ber", 2, 1 },
|
|
{ "rx_fault", 1, 1 },
|
|
{ "tx_fault", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TEST_STATUS", 0x23554, 0 },
|
|
{ "XGMAC_PORT_AN_CONTROL", 0x23600, 0 },
|
|
{ "soft_reset", 15, 1 },
|
|
{ "an_enable", 12, 1 },
|
|
{ "restart_an", 9, 1 },
|
|
{ "XGMAC_PORT_AN_STATUS", 0x23604, 0 },
|
|
{ "Noncer_Match", 31, 1 },
|
|
{ "Parallel_Det_Fault", 9, 1 },
|
|
{ "Page_Received", 6, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "Remote_Fault", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "link_status", 2, 1 },
|
|
{ "partner_an_ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_ADVERTISEMENT", 0x23608, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "XGMAC_PORT_AN_LINK_PARTNER_ABILITY", 0x2360c, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "Selector_Field", 0, 5 },
|
|
{ "XGMAC_PORT_AN_NP_LOWER_TRANSMIT", 0x23610, 0 },
|
|
{ "NP_Info", 16, 16 },
|
|
{ "NP_Indication", 15, 1 },
|
|
{ "Message_Page", 13, 1 },
|
|
{ "ACK_2", 12, 1 },
|
|
{ "Toggle", 11, 1 },
|
|
{ "XGMAC_PORT_AN_NP_UPPER_TRANSMIT", 0x23614, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_LOWER", 0x23618, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_UPPER", 0x2361c, 0 },
|
|
{ "XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS", 0x23624, 0 },
|
|
{ "TX_Pause_Okay", 6, 1 },
|
|
{ "RX_Pause_Okay", 5, 1 },
|
|
{ "10GBASE_KR_FEC_neg", 4, 1 },
|
|
{ "10GBASE_KR_neg", 3, 1 },
|
|
{ "10GBASE_KX4_neg", 2, 1 },
|
|
{ "1000BASE_KX_neg", 1, 1 },
|
|
{ "BP_AN_Ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_TX_NONCE_CONTROL", 0x23628, 0 },
|
|
{ "Bypass_LFSR", 15, 1 },
|
|
{ "LFSR_Init", 0, 15 },
|
|
{ "XGMAC_PORT_AN_INTERRUPT_STATUS", 0x2362c, 0 },
|
|
{ "NP_From_LP", 3, 1 },
|
|
{ "Parallel_Det_Fault", 2, 1 },
|
|
{ "BP_From_LP", 1, 1 },
|
|
{ "PCS_AN_Complete", 0, 1 },
|
|
{ "XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT", 0x23630, 0 },
|
|
{ "XGMAC_PORT_AN_BREAK_LINK_TIMEOUT", 0x23634, 0 },
|
|
{ "XGMAC_PORT_AN_MODULE_ID", 0x2363c, 0 },
|
|
{ "Module_ID", 16, 16 },
|
|
{ "Module_Revision", 0, 16 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_REQ", 0x23700, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "RXREQ_C0", 4, 2 },
|
|
{ "RXREQ_C1", 2, 2 },
|
|
{ "RXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_STAT", 0x23704, 0 },
|
|
{ "RXSTAT_RDY", 15, 1 },
|
|
{ "RXSTAT_C0", 4, 2 },
|
|
{ "RXSTAT_C1", 2, 2 },
|
|
{ "RXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_REQ", 0x23708, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_C0", 4, 2 },
|
|
{ "TXREQ_C1", 2, 2 },
|
|
{ "TXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_STAT", 0x2370c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "TXSTAT_C0", 4, 2 },
|
|
{ "TXSTAT_C1", 2, 2 },
|
|
{ "TXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_REG_MODE", 0x23710, 0 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "XGMAC_PORT_AE_PRBS_CTL", 0x23714, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_CTL", 0x23718, 0 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_STATE", 0x2371c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "XGMAC_PORT_AE_TX_DIS", 0x23780, 0 },
|
|
{ "XGMAC_PORT_AE_KR_CTRL", 0x23784, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "XGMAC_PORT_AE_RX_SIGDET", 0x23788, 0 },
|
|
{ "XGMAC_PORT_AE_KR_STATUS", 0x2378c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_MODE_CFG", 0x23800, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TEST_CTRL", 0x23804, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_COEFF_CTRL", 0x23808, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_MODE", 0x2380c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL", 0x23810, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER", 0x23814, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER", 0x23818, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_COEFF", 0x23820, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_COEFF", 0x23824, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_COEFF", 0x23828, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR", 0x23830, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_POLARITY", 0x23834, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_CMD", 0x23838, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS", 0x2383c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR", 0x23840, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR", 0x23844, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR", 0x23848, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC_OVR", 0x23850, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC", 0x23854, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP", 0x23860, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP", 0x23864, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP", 0x23868, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_SEG_DIS_APP", 0x23870, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA", 0x23878, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR", 0x2387c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_MODE_CFG", 0x23880, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TEST_CTRL", 0x23884, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_COEFF_CTRL", 0x23888, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_MODE", 0x2388c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL", 0x23890, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER", 0x23894, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER", 0x23898, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_COEFF", 0x238a0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_COEFF", 0x238a4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_COEFF", 0x238a8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR", 0x238b0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_POLARITY", 0x238b4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_CMD", 0x238b8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS", 0x238bc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR", 0x238c0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR", 0x238c4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR", 0x238c8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC_OVR", 0x238d0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC", 0x238d4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP", 0x238e0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP", 0x238e4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP", 0x238e8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_SEG_DIS_APP", 0x238f0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA", 0x238f8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR", 0x238fc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_CFG_MODE", 0x23900, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXA_TEST_CTRL", 0x23904, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL", 0x23908, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL", 0x2390c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1", 0x23910, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2", 0x23914, 0 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET", 0x23918, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_SIGDET_CTRL", 0x2391c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_CTRL", 0x23920, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE", 0x23924, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE", 0x23928, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL1", 0x2392c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL2", 0x23930, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL3", 0x23934, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET", 0x23938, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET", 0x2393c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET", 0x23940, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_OFFSET", 0x23944, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET", 0x23948, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_MIN", 0x2394c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_ADAC_CTRL", 0x23950, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL", 0x23954, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS", 0x23958, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H1", 0x2395c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H2", 0x23960, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H3", 0x23964, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H4", 0x23968, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H5", 0x2396c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DAC_DPC", 0x23970, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DDC", 0x23974, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_INTERNAL_STATUS", 0x23978, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL", 0x2397c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_CFG_MODE", 0x23980, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXB_TEST_CTRL", 0x23984, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL", 0x23988, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL", 0x2398c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1", 0x23990, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2", 0x23994, 0 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET", 0x23998, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_SIGDET_CTRL", 0x2399c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_CTRL", 0x239a0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE", 0x239a4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE", 0x239a8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL1", 0x239ac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL2", 0x239b0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL3", 0x239b4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET", 0x239b8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET", 0x239bc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET", 0x239c0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_OFFSET", 0x239c4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET", 0x239c8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_MIN", 0x239cc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_ADAC_CTRL", 0x239d0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL", 0x239d4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS", 0x239d8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H1", 0x239dc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H2", 0x239e0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H3", 0x239e4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H4", 0x239e8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H5", 0x239ec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DAC_DPC", 0x239f0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DDC", 0x239f4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_INTERNAL_STATUS", 0x239f8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL", 0x239fc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_MODE_CFG", 0x23a00, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TEST_CTRL", 0x23a04, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_COEFF_CTRL", 0x23a08, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_MODE", 0x23a0c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL", 0x23a10, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER", 0x23a14, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER", 0x23a18, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_COEFF", 0x23a20, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_COEFF", 0x23a24, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_COEFF", 0x23a28, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR", 0x23a30, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_POLARITY", 0x23a34, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_CMD", 0x23a38, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS", 0x23a3c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR", 0x23a40, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR", 0x23a44, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR", 0x23a48, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC_OVR", 0x23a50, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC", 0x23a54, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP", 0x23a60, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP", 0x23a64, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP", 0x23a68, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_SEG_DIS_APP", 0x23a70, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA", 0x23a78, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR", 0x23a7c, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_MODE_CFG", 0x23a80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TEST_CTRL", 0x23a84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_COEFF_CTRL", 0x23a88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_MODE", 0x23a8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL", 0x23a90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER", 0x23a94, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER", 0x23a98, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_COEFF", 0x23aa0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_COEFF", 0x23aa4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_COEFF", 0x23aa8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR", 0x23ab0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_POLARITY", 0x23ab4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_CMD", 0x23ab8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS", 0x23abc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR", 0x23ac0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR", 0x23ac4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR", 0x23ac8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC_OVR", 0x23ad0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC", 0x23ad4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP", 0x23ae0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP", 0x23ae4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP", 0x23ae8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_SEG_DIS_APP", 0x23af0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA", 0x23af8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR", 0x23afc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_CFG_MODE", 0x23b00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXC_TEST_CTRL", 0x23b04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL", 0x23b08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL", 0x23b0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1", 0x23b10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2", 0x23b14, 0 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET", 0x23b18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_SIGDET_CTRL", 0x23b1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_CTRL", 0x23b20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE", 0x23b24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE", 0x23b28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL1", 0x23b2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL2", 0x23b30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL3", 0x23b34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET", 0x23b38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET", 0x23b3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET", 0x23b40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_OFFSET", 0x23b44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET", 0x23b48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_MIN", 0x23b4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_ADAC_CTRL", 0x23b50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL", 0x23b54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS", 0x23b58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H1", 0x23b5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H2", 0x23b60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H3", 0x23b64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H4", 0x23b68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H5", 0x23b6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DAC_DPC", 0x23b70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DDC", 0x23b74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_INTERNAL_STATUS", 0x23b78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL", 0x23b7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_CFG_MODE", 0x23b80, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXD_TEST_CTRL", 0x23b84, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL", 0x23b88, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL", 0x23b8c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1", 0x23b90, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2", 0x23b94, 0 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET", 0x23b98, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_SIGDET_CTRL", 0x23b9c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_CTRL", 0x23ba0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE", 0x23ba4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE", 0x23ba8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL1", 0x23bac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL2", 0x23bb0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL3", 0x23bb4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET", 0x23bb8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET", 0x23bbc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET", 0x23bc0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_OFFSET", 0x23bc4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET", 0x23bc8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_MIN", 0x23bcc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_ADAC_CTRL", 0x23bd0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL", 0x23bd4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS", 0x23bd8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H1", 0x23bdc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H2", 0x23be0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H3", 0x23be4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H4", 0x23be8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H5", 0x23bec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DAC_DPC", 0x23bf0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DDC", 0x23bf4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_INTERNAL_STATUS", 0x23bf8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL", 0x23bfc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0", 0x23c00, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1", 0x23c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2", 0x23c08, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3", 0x23c0c, 0 },
|
|
{ "VISEL", 4, 1 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "TCDIS", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4", 0x23c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_ANALOG_TEST_MUX", 0x23c14, 0 },
|
|
{ "XGMAC_PORT_HSS_PORT_EN_0", 0x23c18, 0 },
|
|
{ "RXDEN", 7, 1 },
|
|
{ "RXCEN", 6, 1 },
|
|
{ "TXDEN", 5, 1 },
|
|
{ "TXCEN", 4, 1 },
|
|
{ "RXBEN", 3, 1 },
|
|
{ "RXAEN", 2, 1 },
|
|
{ "TXBEN", 1, 1 },
|
|
{ "TXAEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_PORT_RESET_0", 0x23c20, 0 },
|
|
{ "RXDRST", 7, 1 },
|
|
{ "RXCRST", 6, 1 },
|
|
{ "TXDRST", 5, 1 },
|
|
{ "TXCRST", 4, 1 },
|
|
{ "RXBRST", 3, 1 },
|
|
{ "RXARST", 2, 1 },
|
|
{ "TXBRST", 1, 1 },
|
|
{ "TXARST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CHARGE_PUMP_CTRL", 0x23c28, 0 },
|
|
{ "ENCPIS", 2, 1 },
|
|
{ "CPISEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_BAND_GAP_CTRL", 0x23c2c, 0 },
|
|
{ "XGMAC_PORT_HSS_LOFREQ_OVR", 0x23c30, 0 },
|
|
{ "LFREQ2", 3, 1 },
|
|
{ "LFREQ1", 2, 1 },
|
|
{ "LFREQO", 1, 1 },
|
|
{ "LFSEL", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL", 0x23c38, 0 },
|
|
{ "PFVAL", 2, 1 },
|
|
{ "PFEN", 1, 1 },
|
|
{ "VBADJ", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_MODE_CFG", 0x23c80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXTEST_CTRL", 0x23c84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_COEFF_CTRL", 0x23c88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_MODE", 0x23c8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL", 0x23c90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER", 0x23c94, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER", 0x23c98, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_COEFF", 0x23ca0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_COEFF", 0x23ca4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_COEFF", 0x23ca8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR", 0x23cb0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_POLARITY", 0x23cb4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_CMD", 0x23cb8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_STATUS", 0x23cbc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR", 0x23cc0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR", 0x23cc4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR", 0x23cc8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC_OVR", 0x23cd0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC", 0x23cd4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_APP", 0x23ce0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_APP", 0x23ce4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_APP", 0x23ce8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_SEG_DIS_APP", 0x23cf0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR_DATA", 0x23cf8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR", 0x23cfc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_CFG_MODE", 0x23d00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXTEST_CTRL", 0x23d04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL", 0x23d08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL", 0x23d0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1", 0x23d10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2", 0x23d14, 0 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET", 0x23d18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_SIGDET_CTRL", 0x23d1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_CTRL", 0x23d20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE", 0x23d24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE", 0x23d28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL1", 0x23d2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL2", 0x23d30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL3", 0x23d34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET", 0x23d38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET", 0x23d3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET", 0x23d40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_OFFSET", 0x23d44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET", 0x23d48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_MIN", 0x23d4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_ADAC_CTRL", 0x23d50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL", 0x23d54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS", 0x23d58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H1", 0x23d5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H2", 0x23d60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H3", 0x23d64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H4", 0x23d68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H5", 0x23d6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DAC_DPC", 0x23d70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DDC", 0x23d74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_INTERNAL_STATUS", 0x23d78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL", 0x23d7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXRX_CFG_MODE", 0x23e00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXRXTEST_CTRL", 0x23e04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_CFG", 0x25000, 0 },
|
|
{ "XGMII_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "xg2g_speed_mode", 25, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "XGM_Tx_pause_size", 23, 1 },
|
|
{ "XGM_Tx_pause_frame", 22, 1 },
|
|
{ "XGM_Tx_Disable_Pre", 21, 1 },
|
|
{ "XGM_Tx_Disable_Crc", 20, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "Pmux_Rx_Loop", 13, 1 },
|
|
{ "Pmux_Tx_Loop", 12, 1 },
|
|
{ "XGM_Rx_Sel", 10, 2 },
|
|
{ "PCS_Tx_Sel", 8, 2 },
|
|
{ "XAUI20_Rem_Pre", 5, 1 },
|
|
{ "XAUI20_XGMII_Sel", 4, 1 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "XGMAC_PORT_RESET_CTRL", 0x25004, 0 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "TXFIFO_Reset", 9, 1 },
|
|
{ "RXFIFO_Reset", 8, 1 },
|
|
{ "BEAN_Reset", 7, 1 },
|
|
{ "XAUI_Reset", 6, 1 },
|
|
{ "AE_Reset", 5, 1 },
|
|
{ "XGM_Reset", 4, 1 },
|
|
{ "XG2G_Reset", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "XFI_PCS_Reset", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "XGMAC_PORT_LED_CFG", 0x25008, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "XGMAC_PORT_LED_COUNTHI", 0x2500c, 0 },
|
|
{ "XGMAC_PORT_LED_COUNTLO", 0x25010, 0 },
|
|
{ "XGMAC_PORT_DEBUG_CFG", 0x25014, 0 },
|
|
{ "XGMAC_PORT_CFG2", 0x25018, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "MACTxEn", 20, 1 },
|
|
{ "MACRxEn", 19, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "TX_IPG", 4, 13 },
|
|
{ "AEC_PMA_TX_READY", 1, 1 },
|
|
{ "AEC_PMA_RX_READY", 0, 1 },
|
|
{ "XGMAC_PORT_PKT_COUNT", 0x2501c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "XGMAC_PORT_PERR_INJECT", 0x25020, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_LO", 0x25024, 0 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_HI", 0x25028, 0 },
|
|
{ "XGMAC_PORT_BUILD_REVISION", 0x2502c, 0 },
|
|
{ "XGMAC_PORT_XGMII_SE_COUNT", 0x25030, 0 },
|
|
{ "TxSop", 24, 8 },
|
|
{ "TxEop", 16, 8 },
|
|
{ "RxSop", 8, 8 },
|
|
{ "RxEop", 0, 8 },
|
|
{ "XGMAC_PORT_LINK_STATUS", 0x25034, 0 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "XGMAC_PORT_CHECKIN", 0x25038, 0 },
|
|
{ "Preamble", 1, 1 },
|
|
{ "CheckIn", 0, 1 },
|
|
{ "XGMAC_PORT_FAULT_TEST", 0x2503c, 0 },
|
|
{ "FltType", 1, 1 },
|
|
{ "FltCtrl", 0, 1 },
|
|
{ "XGMAC_PORT_SPARE", 0x25040, 0 },
|
|
{ "XGMAC_PORT_HSS_SIGDET_STATUS", 0x25044, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_STATUS", 0x25048, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_CTRL", 0x2504c, 0 },
|
|
{ "XGMAC_PORT_FPGA_PAUSE_CTL", 0x25050, 0 },
|
|
{ "CTL", 31, 1 },
|
|
{ "HWM", 13, 13 },
|
|
{ "LWM", 0, 13 },
|
|
{ "XGMAC_PORT_FPGA_ERRPKT_CNT", 0x25054, 0 },
|
|
{ "XGMAC_PORT_LA_TX_0", 0x25058, 0 },
|
|
{ "XGMAC_PORT_LA_RX_0", 0x2505c, 0 },
|
|
{ "XGMAC_PORT_FPGA_LA_CTL", 0x25060, 0 },
|
|
{ "rxrst", 5, 1 },
|
|
{ "txrst", 4, 1 },
|
|
{ "xgmii", 3, 1 },
|
|
{ "pause", 2, 1 },
|
|
{ "stopErr", 1, 1 },
|
|
{ "stop", 0, 1 },
|
|
{ "XGMAC_PORT_EPIO_DATA0", 0x250c0, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA1", 0x250c4, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA2", 0x250c8, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA3", 0x250cc, 0 },
|
|
{ "XGMAC_PORT_EPIO_OP", 0x250d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "XGMAC_PORT_WOL_STATUS", 0x250d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "XGMAC_PORT_INT_EN", 0x250d8, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_INT_CAUSE", 0x250dc, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG0", 0x250e0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKSEL", 20, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRXTS", 16, 1 },
|
|
{ "HSSTXACMODE", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRESYNC", 13, 1 },
|
|
{ "HSSRECCAL", 12, 1 },
|
|
{ "HSSPDWNPLL", 11, 1 },
|
|
{ "HSSDIVSEL", 9, 2 },
|
|
{ "HSSREFDIV", 8, 1 },
|
|
{ "HSSPLLBYP", 7, 1 },
|
|
{ "HSSLOFREQPLL", 6, 1 },
|
|
{ "HSSLOFREQ2PLL", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "HSSRSTCONFIG", 1, 3 },
|
|
{ "HSSPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG1", 0x250e4, 0 },
|
|
{ "RXDPRBSRST", 28, 1 },
|
|
{ "RXDPRBSEN", 27, 1 },
|
|
{ "RXDPRBSFRCERR", 26, 1 },
|
|
{ "TXDPRBSRST", 25, 1 },
|
|
{ "TXDPRBSEN", 24, 1 },
|
|
{ "RXCPRBSRST", 20, 1 },
|
|
{ "RXCPRBSEN", 19, 1 },
|
|
{ "RXCPRBSFRCERR", 18, 1 },
|
|
{ "TXCPRBSRST", 17, 1 },
|
|
{ "TXCPRBSEN", 16, 1 },
|
|
{ "RXBPRBSRST", 12, 1 },
|
|
{ "RXBPRBSEN", 11, 1 },
|
|
{ "RXBPRBSFRCERR", 10, 1 },
|
|
{ "TXBPRBSRST", 9, 1 },
|
|
{ "TXBPRBSEN", 8, 1 },
|
|
{ "RXAPRBSRST", 4, 1 },
|
|
{ "RXAPRBSEN", 3, 1 },
|
|
{ "RXAPRBSFRCERR", 2, 1 },
|
|
{ "TXAPRBSRST", 1, 1 },
|
|
{ "TXAPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG2", 0x250e8, 0 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_STATUS", 0x250ec, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCK", 1, 1 },
|
|
{ "HSSPRTREADY", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CTRL", 0x25200, 0 },
|
|
{ "SendPause", 2, 1 },
|
|
{ "SendZeroPause", 1, 1 },
|
|
{ "TxEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CFG", 0x25204, 0 },
|
|
{ "CRCCal", 8, 2 },
|
|
{ "DisDefIdleCnt", 7, 1 },
|
|
{ "DecAvgTxIPG", 6, 1 },
|
|
{ "UnidirTxEn", 5, 1 },
|
|
{ "CfgClkSpeed", 2, 3 },
|
|
{ "StretchMode", 1, 1 },
|
|
{ "TxPauseEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_QUANTA", 0x25208, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CTRL", 0x2520c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CFG", 0x25210, 0 },
|
|
{ "CRCCal", 16, 2 },
|
|
{ "LocalFault", 15, 1 },
|
|
{ "RemoteFault", 14, 1 },
|
|
{ "LenErrFrameDis", 13, 1 },
|
|
{ "Con802_3Preamble", 12, 1 },
|
|
{ "EnNon802_3Preamble", 11, 1 },
|
|
{ "CopyPreamble", 10, 1 },
|
|
{ "DisPauseFrames", 9, 1 },
|
|
{ "En1536BFrames", 8, 1 },
|
|
{ "EnJumbo", 7, 1 },
|
|
{ "RmFCS", 6, 1 },
|
|
{ "DisNonVlan", 5, 1 },
|
|
{ "EnExtMatch", 4, 1 },
|
|
{ "EnHashUcast", 3, 1 },
|
|
{ "EnHashMcast", 2, 1 },
|
|
{ "DisBCast", 1, 1 },
|
|
{ "CopyAllFrames", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_LOW", 0x25214, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_HIGH", 0x25218, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1", 0x2521c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1", 0x25220, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2", 0x25224, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2", 0x25228, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3", 0x2522c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3", 0x25230, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4", 0x25234, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4", 0x25238, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5", 0x2523c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5", 0x25240, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6", 0x25244, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6", 0x25248, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7", 0x2524c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7", 0x25250, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8", 0x25254, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8", 0x25258, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_1", 0x2525c, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_2", 0x25260, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_3", 0x25264, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_4", 0x25268, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_INT_STATUS", 0x2526c, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_MASK", 0x25270, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_EN", 0x25274, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_DISABLE", 0x25278, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_TIMER", 0x2527c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_CTRL", 0x25280, 0 },
|
|
{ "ReadSnpShot", 4, 1 },
|
|
{ "TakeSnpShot", 3, 1 },
|
|
{ "ClrStats", 2, 1 },
|
|
{ "IncrStats", 1, 1 },
|
|
{ "EnTestModeWr", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_MDIO_CTRL", 0x25284, 0 },
|
|
{ "FrameType", 30, 2 },
|
|
{ "Operation", 28, 2 },
|
|
{ "PortAddr", 23, 5 },
|
|
{ "DevAddr", 18, 5 },
|
|
{ "Resrv", 16, 2 },
|
|
{ "Data", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_MODULE_ID", 0x252fc, 0 },
|
|
{ "ModuleID", 16, 16 },
|
|
{ "ModuleRev", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_LOW", 0x25300, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH", 0x25304, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_LOW", 0x25308, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH", 0x2530c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BCAST", 0x25310, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_MCAST", 0x25314, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_PAUSE", 0x25318, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_64B_FRAMES", 0x2531c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES", 0x25320, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES", 0x25324, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES", 0x25328, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES", 0x2532c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES", 0x25330, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES", 0x25334, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES", 0x25338, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_LOW", 0x2533c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH", 0x25340, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW", 0x25344, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH", 0x25348, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES", 0x2534c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES", 0x25350, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES", 0x25354, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_64B_FRAMES", 0x25358, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES", 0x2535c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES", 0x25360, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES", 0x25364, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES", 0x25368, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES", 0x2536c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES", 0x25370, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES", 0x25374, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES", 0x25378, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES", 0x2537c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES", 0x25380, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES", 0x25384, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES", 0x25388, 0 },
|
|
{ "XGMAC_PORT_XAUI_CTRL", 0x25400, 0 },
|
|
{ "polarity_inv_rx", 8, 4 },
|
|
{ "polarity_inv_tx", 4, 4 },
|
|
{ "test_sel", 2, 2 },
|
|
{ "test_en", 0, 1 },
|
|
{ "XGMAC_PORT_XAUI_STATUS", 0x25404, 0 },
|
|
{ "Decode_Error", 12, 8 },
|
|
{ "Lane3_CTC_Status", 11, 1 },
|
|
{ "Lane2_CTC_Status", 10, 1 },
|
|
{ "Lane1_CTC_Status", 9, 1 },
|
|
{ "Lane0_CTC_Status", 8, 1 },
|
|
{ "Align_Status", 4, 1 },
|
|
{ "Lane3_Sync_Status", 3, 1 },
|
|
{ "Lane2_Sync_Status", 2, 1 },
|
|
{ "Lane1_Sync_Status", 1, 1 },
|
|
{ "Lane0_Sync_Status", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_CTRL", 0x25500, 0 },
|
|
{ "rx_clk_speed", 7, 1 },
|
|
{ "ScrBypass", 6, 1 },
|
|
{ "FECErrIndEn", 5, 1 },
|
|
{ "FECEn", 4, 1 },
|
|
{ "TestSel", 2, 2 },
|
|
{ "ScrLoopEn", 1, 1 },
|
|
{ "XGMIILoopEn", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_CTRL", 0x25510, 0 },
|
|
{ "tx_prbs9_en", 4, 1 },
|
|
{ "tx_prbs31_en", 3, 1 },
|
|
{ "tx_tst_dat_sel", 2, 1 },
|
|
{ "tx_tst_sel", 1, 1 },
|
|
{ "tx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER", 0x25514, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER", 0x25518, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER", 0x2552c, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER", 0x25530, 0 },
|
|
{ "XGMAC_PORT_PCSR_RXTEST_CTRL", 0x2553c, 0 },
|
|
{ "tpter_cnt_rst", 7, 1 },
|
|
{ "test_cnt_125us", 6, 1 },
|
|
{ "test_cnt_pre", 5, 1 },
|
|
{ "ber_cnt_rst", 4, 1 },
|
|
{ "err_blk_cnt_rst", 3, 1 },
|
|
{ "rx_prbs31_en", 2, 1 },
|
|
{ "rx_tst_dat_sel", 1, 1 },
|
|
{ "rx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_STATUS", 0x25550, 0 },
|
|
{ "err_blk_cnt", 16, 8 },
|
|
{ "ber_count", 8, 6 },
|
|
{ "hi_ber", 2, 1 },
|
|
{ "rx_fault", 1, 1 },
|
|
{ "tx_fault", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TEST_STATUS", 0x25554, 0 },
|
|
{ "XGMAC_PORT_AN_CONTROL", 0x25600, 0 },
|
|
{ "soft_reset", 15, 1 },
|
|
{ "an_enable", 12, 1 },
|
|
{ "restart_an", 9, 1 },
|
|
{ "XGMAC_PORT_AN_STATUS", 0x25604, 0 },
|
|
{ "Noncer_Match", 31, 1 },
|
|
{ "Parallel_Det_Fault", 9, 1 },
|
|
{ "Page_Received", 6, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "Remote_Fault", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "link_status", 2, 1 },
|
|
{ "partner_an_ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_ADVERTISEMENT", 0x25608, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "XGMAC_PORT_AN_LINK_PARTNER_ABILITY", 0x2560c, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "Selector_Field", 0, 5 },
|
|
{ "XGMAC_PORT_AN_NP_LOWER_TRANSMIT", 0x25610, 0 },
|
|
{ "NP_Info", 16, 16 },
|
|
{ "NP_Indication", 15, 1 },
|
|
{ "Message_Page", 13, 1 },
|
|
{ "ACK_2", 12, 1 },
|
|
{ "Toggle", 11, 1 },
|
|
{ "XGMAC_PORT_AN_NP_UPPER_TRANSMIT", 0x25614, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_LOWER", 0x25618, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_UPPER", 0x2561c, 0 },
|
|
{ "XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS", 0x25624, 0 },
|
|
{ "TX_Pause_Okay", 6, 1 },
|
|
{ "RX_Pause_Okay", 5, 1 },
|
|
{ "10GBASE_KR_FEC_neg", 4, 1 },
|
|
{ "10GBASE_KR_neg", 3, 1 },
|
|
{ "10GBASE_KX4_neg", 2, 1 },
|
|
{ "1000BASE_KX_neg", 1, 1 },
|
|
{ "BP_AN_Ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_TX_NONCE_CONTROL", 0x25628, 0 },
|
|
{ "Bypass_LFSR", 15, 1 },
|
|
{ "LFSR_Init", 0, 15 },
|
|
{ "XGMAC_PORT_AN_INTERRUPT_STATUS", 0x2562c, 0 },
|
|
{ "NP_From_LP", 3, 1 },
|
|
{ "Parallel_Det_Fault", 2, 1 },
|
|
{ "BP_From_LP", 1, 1 },
|
|
{ "PCS_AN_Complete", 0, 1 },
|
|
{ "XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT", 0x25630, 0 },
|
|
{ "XGMAC_PORT_AN_BREAK_LINK_TIMEOUT", 0x25634, 0 },
|
|
{ "XGMAC_PORT_AN_MODULE_ID", 0x2563c, 0 },
|
|
{ "Module_ID", 16, 16 },
|
|
{ "Module_Revision", 0, 16 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_REQ", 0x25700, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "RXREQ_C0", 4, 2 },
|
|
{ "RXREQ_C1", 2, 2 },
|
|
{ "RXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_STAT", 0x25704, 0 },
|
|
{ "RXSTAT_RDY", 15, 1 },
|
|
{ "RXSTAT_C0", 4, 2 },
|
|
{ "RXSTAT_C1", 2, 2 },
|
|
{ "RXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_REQ", 0x25708, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_C0", 4, 2 },
|
|
{ "TXREQ_C1", 2, 2 },
|
|
{ "TXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_STAT", 0x2570c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "TXSTAT_C0", 4, 2 },
|
|
{ "TXSTAT_C1", 2, 2 },
|
|
{ "TXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_REG_MODE", 0x25710, 0 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "XGMAC_PORT_AE_PRBS_CTL", 0x25714, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_CTL", 0x25718, 0 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_STATE", 0x2571c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "XGMAC_PORT_AE_TX_DIS", 0x25780, 0 },
|
|
{ "XGMAC_PORT_AE_KR_CTRL", 0x25784, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "XGMAC_PORT_AE_RX_SIGDET", 0x25788, 0 },
|
|
{ "XGMAC_PORT_AE_KR_STATUS", 0x2578c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_MODE_CFG", 0x25800, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TEST_CTRL", 0x25804, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_COEFF_CTRL", 0x25808, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_MODE", 0x2580c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL", 0x25810, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER", 0x25814, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER", 0x25818, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_COEFF", 0x25820, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_COEFF", 0x25824, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_COEFF", 0x25828, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR", 0x25830, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_POLARITY", 0x25834, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_CMD", 0x25838, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS", 0x2583c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR", 0x25840, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR", 0x25844, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR", 0x25848, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC_OVR", 0x25850, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC", 0x25854, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP", 0x25860, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP", 0x25864, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP", 0x25868, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_SEG_DIS_APP", 0x25870, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA", 0x25878, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR", 0x2587c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_MODE_CFG", 0x25880, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TEST_CTRL", 0x25884, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_COEFF_CTRL", 0x25888, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_MODE", 0x2588c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL", 0x25890, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER", 0x25894, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER", 0x25898, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_COEFF", 0x258a0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_COEFF", 0x258a4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_COEFF", 0x258a8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR", 0x258b0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_POLARITY", 0x258b4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_CMD", 0x258b8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS", 0x258bc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR", 0x258c0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR", 0x258c4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR", 0x258c8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC_OVR", 0x258d0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC", 0x258d4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP", 0x258e0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP", 0x258e4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP", 0x258e8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_SEG_DIS_APP", 0x258f0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA", 0x258f8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR", 0x258fc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_CFG_MODE", 0x25900, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXA_TEST_CTRL", 0x25904, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL", 0x25908, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL", 0x2590c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1", 0x25910, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2", 0x25914, 0 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET", 0x25918, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_SIGDET_CTRL", 0x2591c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_CTRL", 0x25920, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE", 0x25924, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE", 0x25928, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL1", 0x2592c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL2", 0x25930, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL3", 0x25934, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET", 0x25938, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET", 0x2593c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET", 0x25940, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_OFFSET", 0x25944, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET", 0x25948, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_MIN", 0x2594c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_ADAC_CTRL", 0x25950, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL", 0x25954, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS", 0x25958, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H1", 0x2595c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H2", 0x25960, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H3", 0x25964, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H4", 0x25968, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H5", 0x2596c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DAC_DPC", 0x25970, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DDC", 0x25974, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_INTERNAL_STATUS", 0x25978, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL", 0x2597c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_CFG_MODE", 0x25980, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXB_TEST_CTRL", 0x25984, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL", 0x25988, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL", 0x2598c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1", 0x25990, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2", 0x25994, 0 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET", 0x25998, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_SIGDET_CTRL", 0x2599c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_CTRL", 0x259a0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE", 0x259a4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE", 0x259a8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL1", 0x259ac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL2", 0x259b0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL3", 0x259b4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET", 0x259b8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET", 0x259bc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET", 0x259c0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_OFFSET", 0x259c4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET", 0x259c8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_MIN", 0x259cc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_ADAC_CTRL", 0x259d0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL", 0x259d4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS", 0x259d8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H1", 0x259dc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H2", 0x259e0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H3", 0x259e4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H4", 0x259e8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H5", 0x259ec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DAC_DPC", 0x259f0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DDC", 0x259f4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_INTERNAL_STATUS", 0x259f8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL", 0x259fc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_MODE_CFG", 0x25a00, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TEST_CTRL", 0x25a04, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_COEFF_CTRL", 0x25a08, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_MODE", 0x25a0c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL", 0x25a10, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER", 0x25a14, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER", 0x25a18, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_COEFF", 0x25a20, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_COEFF", 0x25a24, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_COEFF", 0x25a28, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR", 0x25a30, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_POLARITY", 0x25a34, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_CMD", 0x25a38, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS", 0x25a3c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR", 0x25a40, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR", 0x25a44, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR", 0x25a48, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC_OVR", 0x25a50, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC", 0x25a54, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP", 0x25a60, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP", 0x25a64, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP", 0x25a68, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_SEG_DIS_APP", 0x25a70, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA", 0x25a78, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR", 0x25a7c, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_MODE_CFG", 0x25a80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TEST_CTRL", 0x25a84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_COEFF_CTRL", 0x25a88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_MODE", 0x25a8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL", 0x25a90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER", 0x25a94, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER", 0x25a98, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_COEFF", 0x25aa0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_COEFF", 0x25aa4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_COEFF", 0x25aa8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR", 0x25ab0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_POLARITY", 0x25ab4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_CMD", 0x25ab8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS", 0x25abc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR", 0x25ac0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR", 0x25ac4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR", 0x25ac8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC_OVR", 0x25ad0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC", 0x25ad4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP", 0x25ae0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP", 0x25ae4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP", 0x25ae8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_SEG_DIS_APP", 0x25af0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA", 0x25af8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR", 0x25afc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_CFG_MODE", 0x25b00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXC_TEST_CTRL", 0x25b04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL", 0x25b08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL", 0x25b0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1", 0x25b10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2", 0x25b14, 0 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET", 0x25b18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_SIGDET_CTRL", 0x25b1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_CTRL", 0x25b20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE", 0x25b24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE", 0x25b28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL1", 0x25b2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL2", 0x25b30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL3", 0x25b34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET", 0x25b38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET", 0x25b3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET", 0x25b40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_OFFSET", 0x25b44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET", 0x25b48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_MIN", 0x25b4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_ADAC_CTRL", 0x25b50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL", 0x25b54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS", 0x25b58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H1", 0x25b5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H2", 0x25b60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H3", 0x25b64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H4", 0x25b68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H5", 0x25b6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DAC_DPC", 0x25b70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DDC", 0x25b74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_INTERNAL_STATUS", 0x25b78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL", 0x25b7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_CFG_MODE", 0x25b80, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXD_TEST_CTRL", 0x25b84, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL", 0x25b88, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL", 0x25b8c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1", 0x25b90, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2", 0x25b94, 0 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET", 0x25b98, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_SIGDET_CTRL", 0x25b9c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_CTRL", 0x25ba0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE", 0x25ba4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE", 0x25ba8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL1", 0x25bac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL2", 0x25bb0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL3", 0x25bb4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET", 0x25bb8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET", 0x25bbc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET", 0x25bc0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_OFFSET", 0x25bc4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET", 0x25bc8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_MIN", 0x25bcc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_ADAC_CTRL", 0x25bd0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL", 0x25bd4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS", 0x25bd8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H1", 0x25bdc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H2", 0x25be0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H3", 0x25be4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H4", 0x25be8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H5", 0x25bec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DAC_DPC", 0x25bf0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DDC", 0x25bf4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_INTERNAL_STATUS", 0x25bf8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL", 0x25bfc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0", 0x25c00, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1", 0x25c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2", 0x25c08, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3", 0x25c0c, 0 },
|
|
{ "VISEL", 4, 1 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "TCDIS", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4", 0x25c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_ANALOG_TEST_MUX", 0x25c14, 0 },
|
|
{ "XGMAC_PORT_HSS_PORT_EN_0", 0x25c18, 0 },
|
|
{ "RXDEN", 7, 1 },
|
|
{ "RXCEN", 6, 1 },
|
|
{ "TXDEN", 5, 1 },
|
|
{ "TXCEN", 4, 1 },
|
|
{ "RXBEN", 3, 1 },
|
|
{ "RXAEN", 2, 1 },
|
|
{ "TXBEN", 1, 1 },
|
|
{ "TXAEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_PORT_RESET_0", 0x25c20, 0 },
|
|
{ "RXDRST", 7, 1 },
|
|
{ "RXCRST", 6, 1 },
|
|
{ "TXDRST", 5, 1 },
|
|
{ "TXCRST", 4, 1 },
|
|
{ "RXBRST", 3, 1 },
|
|
{ "RXARST", 2, 1 },
|
|
{ "TXBRST", 1, 1 },
|
|
{ "TXARST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CHARGE_PUMP_CTRL", 0x25c28, 0 },
|
|
{ "ENCPIS", 2, 1 },
|
|
{ "CPISEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_BAND_GAP_CTRL", 0x25c2c, 0 },
|
|
{ "XGMAC_PORT_HSS_LOFREQ_OVR", 0x25c30, 0 },
|
|
{ "LFREQ2", 3, 1 },
|
|
{ "LFREQ1", 2, 1 },
|
|
{ "LFREQO", 1, 1 },
|
|
{ "LFSEL", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL", 0x25c38, 0 },
|
|
{ "PFVAL", 2, 1 },
|
|
{ "PFEN", 1, 1 },
|
|
{ "VBADJ", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_MODE_CFG", 0x25c80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXTEST_CTRL", 0x25c84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_COEFF_CTRL", 0x25c88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_MODE", 0x25c8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL", 0x25c90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER", 0x25c94, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER", 0x25c98, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_COEFF", 0x25ca0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_COEFF", 0x25ca4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_COEFF", 0x25ca8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR", 0x25cb0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_POLARITY", 0x25cb4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_CMD", 0x25cb8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_STATUS", 0x25cbc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR", 0x25cc0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR", 0x25cc4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR", 0x25cc8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC_OVR", 0x25cd0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC", 0x25cd4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_APP", 0x25ce0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_APP", 0x25ce4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_APP", 0x25ce8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_SEG_DIS_APP", 0x25cf0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR_DATA", 0x25cf8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR", 0x25cfc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_CFG_MODE", 0x25d00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXTEST_CTRL", 0x25d04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL", 0x25d08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL", 0x25d0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1", 0x25d10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2", 0x25d14, 0 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET", 0x25d18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_SIGDET_CTRL", 0x25d1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_CTRL", 0x25d20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE", 0x25d24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE", 0x25d28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL1", 0x25d2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL2", 0x25d30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL3", 0x25d34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET", 0x25d38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET", 0x25d3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET", 0x25d40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_OFFSET", 0x25d44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET", 0x25d48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_MIN", 0x25d4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_ADAC_CTRL", 0x25d50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL", 0x25d54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS", 0x25d58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H1", 0x25d5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H2", 0x25d60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H3", 0x25d64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H4", 0x25d68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H5", 0x25d6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DAC_DPC", 0x25d70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DDC", 0x25d74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_INTERNAL_STATUS", 0x25d78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL", 0x25d7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXRX_CFG_MODE", 0x25e00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXRXTEST_CTRL", 0x25e04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_CFG", 0x27000, 0 },
|
|
{ "XGMII_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "xg2g_speed_mode", 25, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "XGM_Tx_pause_size", 23, 1 },
|
|
{ "XGM_Tx_pause_frame", 22, 1 },
|
|
{ "XGM_Tx_Disable_Pre", 21, 1 },
|
|
{ "XGM_Tx_Disable_Crc", 20, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "Pmux_Rx_Loop", 13, 1 },
|
|
{ "Pmux_Tx_Loop", 12, 1 },
|
|
{ "XGM_Rx_Sel", 10, 2 },
|
|
{ "PCS_Tx_Sel", 8, 2 },
|
|
{ "XAUI20_Rem_Pre", 5, 1 },
|
|
{ "XAUI20_XGMII_Sel", 4, 1 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "XGMAC_PORT_RESET_CTRL", 0x27004, 0 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "TXFIFO_Reset", 9, 1 },
|
|
{ "RXFIFO_Reset", 8, 1 },
|
|
{ "BEAN_Reset", 7, 1 },
|
|
{ "XAUI_Reset", 6, 1 },
|
|
{ "AE_Reset", 5, 1 },
|
|
{ "XGM_Reset", 4, 1 },
|
|
{ "XG2G_Reset", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "XFI_PCS_Reset", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "XGMAC_PORT_LED_CFG", 0x27008, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "XGMAC_PORT_LED_COUNTHI", 0x2700c, 0 },
|
|
{ "XGMAC_PORT_LED_COUNTLO", 0x27010, 0 },
|
|
{ "XGMAC_PORT_DEBUG_CFG", 0x27014, 0 },
|
|
{ "XGMAC_PORT_CFG2", 0x27018, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "MACTxEn", 20, 1 },
|
|
{ "MACRxEn", 19, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "TX_IPG", 4, 13 },
|
|
{ "AEC_PMA_TX_READY", 1, 1 },
|
|
{ "AEC_PMA_RX_READY", 0, 1 },
|
|
{ "XGMAC_PORT_PKT_COUNT", 0x2701c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "XGMAC_PORT_PERR_INJECT", 0x27020, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_LO", 0x27024, 0 },
|
|
{ "XGMAC_PORT_MAGIC_MACID_HI", 0x27028, 0 },
|
|
{ "XGMAC_PORT_BUILD_REVISION", 0x2702c, 0 },
|
|
{ "XGMAC_PORT_XGMII_SE_COUNT", 0x27030, 0 },
|
|
{ "TxSop", 24, 8 },
|
|
{ "TxEop", 16, 8 },
|
|
{ "RxSop", 8, 8 },
|
|
{ "RxEop", 0, 8 },
|
|
{ "XGMAC_PORT_LINK_STATUS", 0x27034, 0 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "XGMAC_PORT_CHECKIN", 0x27038, 0 },
|
|
{ "Preamble", 1, 1 },
|
|
{ "CheckIn", 0, 1 },
|
|
{ "XGMAC_PORT_FAULT_TEST", 0x2703c, 0 },
|
|
{ "FltType", 1, 1 },
|
|
{ "FltCtrl", 0, 1 },
|
|
{ "XGMAC_PORT_SPARE", 0x27040, 0 },
|
|
{ "XGMAC_PORT_HSS_SIGDET_STATUS", 0x27044, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_STATUS", 0x27048, 0 },
|
|
{ "XGMAC_PORT_EXT_LOS_CTRL", 0x2704c, 0 },
|
|
{ "XGMAC_PORT_FPGA_PAUSE_CTL", 0x27050, 0 },
|
|
{ "CTL", 31, 1 },
|
|
{ "HWM", 13, 13 },
|
|
{ "LWM", 0, 13 },
|
|
{ "XGMAC_PORT_FPGA_ERRPKT_CNT", 0x27054, 0 },
|
|
{ "XGMAC_PORT_LA_TX_0", 0x27058, 0 },
|
|
{ "XGMAC_PORT_LA_RX_0", 0x2705c, 0 },
|
|
{ "XGMAC_PORT_FPGA_LA_CTL", 0x27060, 0 },
|
|
{ "rxrst", 5, 1 },
|
|
{ "txrst", 4, 1 },
|
|
{ "xgmii", 3, 1 },
|
|
{ "pause", 2, 1 },
|
|
{ "stopErr", 1, 1 },
|
|
{ "stop", 0, 1 },
|
|
{ "XGMAC_PORT_EPIO_DATA0", 0x270c0, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA1", 0x270c4, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA2", 0x270c8, 0 },
|
|
{ "XGMAC_PORT_EPIO_DATA3", 0x270cc, 0 },
|
|
{ "XGMAC_PORT_EPIO_OP", 0x270d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "XGMAC_PORT_WOL_STATUS", 0x270d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "XGMAC_PORT_INT_EN", 0x270d8, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_INT_CAUSE", 0x270dc, 0 },
|
|
{ "ext_los", 28, 1 },
|
|
{ "incmptbl_link", 27, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "PCSR_fec_corr", 23, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCSR_Hi_BER", 18, 1 },
|
|
{ "PCSR_FEC_Error", 17, 1 },
|
|
{ "PCSR_Link_Fail", 16, 1 },
|
|
{ "XAUI_Dec_Error", 15, 1 },
|
|
{ "XAUI_Link_Fail", 14, 1 },
|
|
{ "PCS_CTC_Error", 13, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "BEAN_Int", 3, 1 },
|
|
{ "XGM_Int", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG0", 0x270e0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKSEL", 20, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRXTS", 16, 1 },
|
|
{ "HSSTXACMODE", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRESYNC", 13, 1 },
|
|
{ "HSSRECCAL", 12, 1 },
|
|
{ "HSSPDWNPLL", 11, 1 },
|
|
{ "HSSDIVSEL", 9, 2 },
|
|
{ "HSSREFDIV", 8, 1 },
|
|
{ "HSSPLLBYP", 7, 1 },
|
|
{ "HSSLOFREQPLL", 6, 1 },
|
|
{ "HSSLOFREQ2PLL", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "HSSRSTCONFIG", 1, 3 },
|
|
{ "HSSPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG1", 0x270e4, 0 },
|
|
{ "RXDPRBSRST", 28, 1 },
|
|
{ "RXDPRBSEN", 27, 1 },
|
|
{ "RXDPRBSFRCERR", 26, 1 },
|
|
{ "TXDPRBSRST", 25, 1 },
|
|
{ "TXDPRBSEN", 24, 1 },
|
|
{ "RXCPRBSRST", 20, 1 },
|
|
{ "RXCPRBSEN", 19, 1 },
|
|
{ "RXCPRBSFRCERR", 18, 1 },
|
|
{ "TXCPRBSRST", 17, 1 },
|
|
{ "TXCPRBSEN", 16, 1 },
|
|
{ "RXBPRBSRST", 12, 1 },
|
|
{ "RXBPRBSEN", 11, 1 },
|
|
{ "RXBPRBSFRCERR", 10, 1 },
|
|
{ "TXBPRBSRST", 9, 1 },
|
|
{ "TXBPRBSEN", 8, 1 },
|
|
{ "RXAPRBSRST", 4, 1 },
|
|
{ "RXAPRBSEN", 3, 1 },
|
|
{ "RXAPRBSFRCERR", 2, 1 },
|
|
{ "TXAPRBSRST", 1, 1 },
|
|
{ "TXAPRBSEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CFG2", 0x270e8, 0 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_STATUS", 0x270ec, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCK", 1, 1 },
|
|
{ "HSSPRTREADY", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CTRL", 0x27200, 0 },
|
|
{ "SendPause", 2, 1 },
|
|
{ "SendZeroPause", 1, 1 },
|
|
{ "TxEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_CFG", 0x27204, 0 },
|
|
{ "CRCCal", 8, 2 },
|
|
{ "DisDefIdleCnt", 7, 1 },
|
|
{ "DecAvgTxIPG", 6, 1 },
|
|
{ "UnidirTxEn", 5, 1 },
|
|
{ "CfgClkSpeed", 2, 3 },
|
|
{ "StretchMode", 1, 1 },
|
|
{ "TxPauseEn", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_QUANTA", 0x27208, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CTRL", 0x2720c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_CFG", 0x27210, 0 },
|
|
{ "CRCCal", 16, 2 },
|
|
{ "LocalFault", 15, 1 },
|
|
{ "RemoteFault", 14, 1 },
|
|
{ "LenErrFrameDis", 13, 1 },
|
|
{ "Con802_3Preamble", 12, 1 },
|
|
{ "EnNon802_3Preamble", 11, 1 },
|
|
{ "CopyPreamble", 10, 1 },
|
|
{ "DisPauseFrames", 9, 1 },
|
|
{ "En1536BFrames", 8, 1 },
|
|
{ "EnJumbo", 7, 1 },
|
|
{ "RmFCS", 6, 1 },
|
|
{ "DisNonVlan", 5, 1 },
|
|
{ "EnExtMatch", 4, 1 },
|
|
{ "EnHashUcast", 3, 1 },
|
|
{ "EnHashMcast", 2, 1 },
|
|
{ "DisBCast", 1, 1 },
|
|
{ "CopyAllFrames", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_LOW", 0x27214, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_HASH_HIGH", 0x27218, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1", 0x2721c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1", 0x27220, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2", 0x27224, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2", 0x27228, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3", 0x2722c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3", 0x27230, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4", 0x27234, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4", 0x27238, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5", 0x2723c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5", 0x27240, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6", 0x27244, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6", 0x27248, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7", 0x2724c, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7", 0x27250, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8", 0x27254, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8", 0x27258, 0 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_1", 0x2725c, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_2", 0x27260, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_3", 0x27264, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_RX_TYPE_MATCH_4", 0x27268, 0 },
|
|
{ "EnTypeMatch", 31, 1 },
|
|
{ "type", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_INT_STATUS", 0x2726c, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_MASK", 0x27270, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_EN", 0x27274, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_INT_DISABLE", 0x27278, 0 },
|
|
{ "XGMIIExtInt", 10, 1 },
|
|
{ "LinkFaultChange", 9, 1 },
|
|
{ "PhyFrameComplete", 8, 1 },
|
|
{ "PauseFrameTxmt", 7, 1 },
|
|
{ "PauseCntrTimeOut", 6, 1 },
|
|
{ "Non0PauseRcvd", 5, 1 },
|
|
{ "StatOFlow", 4, 1 },
|
|
{ "TxErrFIFO", 3, 1 },
|
|
{ "TxUFlow", 2, 1 },
|
|
{ "FrameTxmt", 1, 1 },
|
|
{ "FrameRcvd", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_TX_PAUSE_TIMER", 0x2727c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_CTRL", 0x27280, 0 },
|
|
{ "ReadSnpShot", 4, 1 },
|
|
{ "TakeSnpShot", 3, 1 },
|
|
{ "ClrStats", 2, 1 },
|
|
{ "IncrStats", 1, 1 },
|
|
{ "EnTestModeWr", 0, 1 },
|
|
{ "XGMAC_PORT_XGM_MDIO_CTRL", 0x27284, 0 },
|
|
{ "FrameType", 30, 2 },
|
|
{ "Operation", 28, 2 },
|
|
{ "PortAddr", 23, 5 },
|
|
{ "DevAddr", 18, 5 },
|
|
{ "Resrv", 16, 2 },
|
|
{ "Data", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_MODULE_ID", 0x272fc, 0 },
|
|
{ "ModuleID", 16, 16 },
|
|
{ "ModuleRev", 0, 16 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_LOW", 0x27300, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH", 0x27304, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_LOW", 0x27308, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH", 0x2730c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_BCAST", 0x27310, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_MCAST", 0x27314, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_PAUSE", 0x27318, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_64B_FRAMES", 0x2731c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES", 0x27320, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES", 0x27324, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES", 0x27328, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES", 0x2732c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES", 0x27330, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES", 0x27334, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES", 0x27338, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_LOW", 0x2733c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH", 0x27340, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW", 0x27344, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH", 0x27348, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES", 0x2734c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES", 0x27350, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES", 0x27354, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_64B_FRAMES", 0x27358, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES", 0x2735c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES", 0x27360, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES", 0x27364, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES", 0x27368, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES", 0x2736c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES", 0x27370, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES", 0x27374, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES", 0x27378, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES", 0x2737c, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES", 0x27380, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES", 0x27384, 0 },
|
|
{ "XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES", 0x27388, 0 },
|
|
{ "XGMAC_PORT_XAUI_CTRL", 0x27400, 0 },
|
|
{ "polarity_inv_rx", 8, 4 },
|
|
{ "polarity_inv_tx", 4, 4 },
|
|
{ "test_sel", 2, 2 },
|
|
{ "test_en", 0, 1 },
|
|
{ "XGMAC_PORT_XAUI_STATUS", 0x27404, 0 },
|
|
{ "Decode_Error", 12, 8 },
|
|
{ "Lane3_CTC_Status", 11, 1 },
|
|
{ "Lane2_CTC_Status", 10, 1 },
|
|
{ "Lane1_CTC_Status", 9, 1 },
|
|
{ "Lane0_CTC_Status", 8, 1 },
|
|
{ "Align_Status", 4, 1 },
|
|
{ "Lane3_Sync_Status", 3, 1 },
|
|
{ "Lane2_Sync_Status", 2, 1 },
|
|
{ "Lane1_Sync_Status", 1, 1 },
|
|
{ "Lane0_Sync_Status", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_CTRL", 0x27500, 0 },
|
|
{ "rx_clk_speed", 7, 1 },
|
|
{ "ScrBypass", 6, 1 },
|
|
{ "FECErrIndEn", 5, 1 },
|
|
{ "FECEn", 4, 1 },
|
|
{ "TestSel", 2, 2 },
|
|
{ "ScrLoopEn", 1, 1 },
|
|
{ "XGMIILoopEn", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_CTRL", 0x27510, 0 },
|
|
{ "tx_prbs9_en", 4, 1 },
|
|
{ "tx_prbs31_en", 3, 1 },
|
|
{ "tx_tst_dat_sel", 2, 1 },
|
|
{ "tx_tst_sel", 1, 1 },
|
|
{ "tx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER", 0x27514, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER", 0x27518, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER", 0x2752c, 0 },
|
|
{ "XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER", 0x27530, 0 },
|
|
{ "XGMAC_PORT_PCSR_RXTEST_CTRL", 0x2753c, 0 },
|
|
{ "tpter_cnt_rst", 7, 1 },
|
|
{ "test_cnt_125us", 6, 1 },
|
|
{ "test_cnt_pre", 5, 1 },
|
|
{ "ber_cnt_rst", 4, 1 },
|
|
{ "err_blk_cnt_rst", 3, 1 },
|
|
{ "rx_prbs31_en", 2, 1 },
|
|
{ "rx_tst_dat_sel", 1, 1 },
|
|
{ "rx_tst_en", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_STATUS", 0x27550, 0 },
|
|
{ "err_blk_cnt", 16, 8 },
|
|
{ "ber_count", 8, 6 },
|
|
{ "hi_ber", 2, 1 },
|
|
{ "rx_fault", 1, 1 },
|
|
{ "tx_fault", 0, 1 },
|
|
{ "XGMAC_PORT_PCSR_TEST_STATUS", 0x27554, 0 },
|
|
{ "XGMAC_PORT_AN_CONTROL", 0x27600, 0 },
|
|
{ "soft_reset", 15, 1 },
|
|
{ "an_enable", 12, 1 },
|
|
{ "restart_an", 9, 1 },
|
|
{ "XGMAC_PORT_AN_STATUS", 0x27604, 0 },
|
|
{ "Noncer_Match", 31, 1 },
|
|
{ "Parallel_Det_Fault", 9, 1 },
|
|
{ "Page_Received", 6, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "Remote_Fault", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "link_status", 2, 1 },
|
|
{ "partner_an_ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_ADVERTISEMENT", 0x27608, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "XGMAC_PORT_AN_LINK_PARTNER_ABILITY", 0x2760c, 0 },
|
|
{ "FEC_Enable", 31, 1 },
|
|
{ "FEC_Ability", 30, 1 },
|
|
{ "10GBASE_KR_Capable", 23, 1 },
|
|
{ "10GBASE_KX4_Capable", 22, 1 },
|
|
{ "1000BASE_KX_Capable", 21, 1 },
|
|
{ "Transmitted_Nonce", 16, 5 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "Remote_Fault", 13, 1 },
|
|
{ "ASM_DIR", 11, 1 },
|
|
{ "Pause", 10, 1 },
|
|
{ "Echoed_Nonce", 5, 5 },
|
|
{ "Selector_Field", 0, 5 },
|
|
{ "XGMAC_PORT_AN_NP_LOWER_TRANSMIT", 0x27610, 0 },
|
|
{ "NP_Info", 16, 16 },
|
|
{ "NP_Indication", 15, 1 },
|
|
{ "Message_Page", 13, 1 },
|
|
{ "ACK_2", 12, 1 },
|
|
{ "Toggle", 11, 1 },
|
|
{ "XGMAC_PORT_AN_NP_UPPER_TRANSMIT", 0x27614, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_LOWER", 0x27618, 0 },
|
|
{ "XGMAC_PORT_AN_LP_NP_UPPER", 0x2761c, 0 },
|
|
{ "XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS", 0x27624, 0 },
|
|
{ "TX_Pause_Okay", 6, 1 },
|
|
{ "RX_Pause_Okay", 5, 1 },
|
|
{ "10GBASE_KR_FEC_neg", 4, 1 },
|
|
{ "10GBASE_KR_neg", 3, 1 },
|
|
{ "10GBASE_KX4_neg", 2, 1 },
|
|
{ "1000BASE_KX_neg", 1, 1 },
|
|
{ "BP_AN_Ability", 0, 1 },
|
|
{ "XGMAC_PORT_AN_TX_NONCE_CONTROL", 0x27628, 0 },
|
|
{ "Bypass_LFSR", 15, 1 },
|
|
{ "LFSR_Init", 0, 15 },
|
|
{ "XGMAC_PORT_AN_INTERRUPT_STATUS", 0x2762c, 0 },
|
|
{ "NP_From_LP", 3, 1 },
|
|
{ "Parallel_Det_Fault", 2, 1 },
|
|
{ "BP_From_LP", 1, 1 },
|
|
{ "PCS_AN_Complete", 0, 1 },
|
|
{ "XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT", 0x27630, 0 },
|
|
{ "XGMAC_PORT_AN_BREAK_LINK_TIMEOUT", 0x27634, 0 },
|
|
{ "XGMAC_PORT_AN_MODULE_ID", 0x2763c, 0 },
|
|
{ "Module_ID", 16, 16 },
|
|
{ "Module_Revision", 0, 16 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_REQ", 0x27700, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "RXREQ_C0", 4, 2 },
|
|
{ "RXREQ_C1", 2, 2 },
|
|
{ "RXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_RX_COEF_STAT", 0x27704, 0 },
|
|
{ "RXSTAT_RDY", 15, 1 },
|
|
{ "RXSTAT_C0", 4, 2 },
|
|
{ "RXSTAT_C1", 2, 2 },
|
|
{ "RXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_REQ", 0x27708, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "TXREQ_C0", 4, 2 },
|
|
{ "TXREQ_C1", 2, 2 },
|
|
{ "TXREQ_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_TX_COEF_STAT", 0x2770c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "TXSTAT_C0", 4, 2 },
|
|
{ "TXSTAT_C1", 2, 2 },
|
|
{ "TXSTAT_C2", 0, 2 },
|
|
{ "XGMAC_PORT_AE_REG_MODE", 0x27710, 0 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "XGMAC_PORT_AE_PRBS_CTL", 0x27714, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_CTL", 0x27718, 0 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "XGMAC_PORT_AE_FSM_STATE", 0x2771c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "XGMAC_PORT_AE_TX_DIS", 0x27780, 0 },
|
|
{ "XGMAC_PORT_AE_KR_CTRL", 0x27784, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "XGMAC_PORT_AE_RX_SIGDET", 0x27788, 0 },
|
|
{ "XGMAC_PORT_AE_KR_STATUS", 0x2778c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_MODE_CFG", 0x27800, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TEST_CTRL", 0x27804, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_COEFF_CTRL", 0x27808, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_MODE", 0x2780c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL", 0x27810, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER", 0x27814, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER", 0x27818, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_COEFF", 0x27820, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_COEFF", 0x27824, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_COEFF", 0x27828, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR", 0x27830, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_POLARITY", 0x27834, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_CMD", 0x27838, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS", 0x2783c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR", 0x27840, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR", 0x27844, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR", 0x27848, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC_OVR", 0x27850, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXA_PWR_DAC", 0x27854, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP", 0x27860, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP", 0x27864, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP", 0x27868, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_SEG_DIS_APP", 0x27870, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA", 0x27878, 0 },
|
|
{ "XGMAC_PORT_HSS_TXA_EXT_ADDR", 0x2787c, 0 },
|
|
{ "XADDR", 1, 5 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_MODE_CFG", 0x27880, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TEST_CTRL", 0x27884, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_COEFF_CTRL", 0x27888, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_MODE", 0x2788c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL", 0x27890, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER", 0x27894, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER", 0x27898, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_COEFF", 0x278a0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_COEFF", 0x278a4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_COEFF", 0x278a8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR", 0x278b0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_POLARITY", 0x278b4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_CMD", 0x278b8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS", 0x278bc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR", 0x278c0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR", 0x278c4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR", 0x278c8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC_OVR", 0x278d0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXB_PWR_DAC", 0x278d4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP", 0x278e0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP", 0x278e4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP", 0x278e8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_SEG_DIS_APP", 0x278f0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA", 0x278f8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXB_EXT_ADDR", 0x278fc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_CFG_MODE", 0x27900, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXA_TEST_CTRL", 0x27904, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL", 0x27908, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL", 0x2790c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1", 0x27910, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2", 0x27914, 0 },
|
|
{ "XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET", 0x27918, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_SIGDET_CTRL", 0x2791c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_CTRL", 0x27920, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE", 0x27924, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE", 0x27928, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL1", 0x2792c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL2", 0x27930, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_VGA_CTRL3", 0x27934, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET", 0x27938, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET", 0x2793c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET", 0x27940, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_OFFSET", 0x27944, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET", 0x27948, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_DACA_MIN", 0x2794c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXA_ADAC_CTRL", 0x27950, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL", 0x27954, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS", 0x27958, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H1", 0x2795c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H2", 0x27960, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H3", 0x27964, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H4", 0x27968, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_H5", 0x2796c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DAC_DPC", 0x27970, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXA_DDC", 0x27974, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXA_INTERNAL_STATUS", 0x27978, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL", 0x2797c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_CFG_MODE", 0x27980, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXB_TEST_CTRL", 0x27984, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL", 0x27988, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL", 0x2798c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1", 0x27990, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2", 0x27994, 0 },
|
|
{ "XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET", 0x27998, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_SIGDET_CTRL", 0x2799c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_CTRL", 0x279a0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE", 0x279a4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE", 0x279a8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL1", 0x279ac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL2", 0x279b0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_VGA_CTRL3", 0x279b4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET", 0x279b8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET", 0x279bc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET", 0x279c0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_OFFSET", 0x279c4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET", 0x279c8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_DACA_MIN", 0x279cc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXB_ADAC_CTRL", 0x279d0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL", 0x279d4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS", 0x279d8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H1", 0x279dc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H2", 0x279e0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H3", 0x279e4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H4", 0x279e8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_H5", 0x279ec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DAC_DPC", 0x279f0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXB_DDC", 0x279f4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXB_INTERNAL_STATUS", 0x279f8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL", 0x279fc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_MODE_CFG", 0x27a00, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TEST_CTRL", 0x27a04, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_COEFF_CTRL", 0x27a08, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_MODE", 0x27a0c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL", 0x27a10, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER", 0x27a14, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER", 0x27a18, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_COEFF", 0x27a20, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_COEFF", 0x27a24, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_COEFF", 0x27a28, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR", 0x27a30, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_POLARITY", 0x27a34, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_CMD", 0x27a38, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS", 0x27a3c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR", 0x27a40, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR", 0x27a44, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR", 0x27a48, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC_OVR", 0x27a50, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXC_PWR_DAC", 0x27a54, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP", 0x27a60, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP", 0x27a64, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP", 0x27a68, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_SEG_DIS_APP", 0x27a70, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA", 0x27a78, 0 },
|
|
{ "XGMAC_PORT_HSS_TXC_EXT_ADDR", 0x27a7c, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_MODE_CFG", 0x27a80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TEST_CTRL", 0x27a84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_COEFF_CTRL", 0x27a88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_MODE", 0x27a8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL", 0x27a90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER", 0x27a94, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER", 0x27a98, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_COEFF", 0x27aa0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_COEFF", 0x27aa4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_COEFF", 0x27aa8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR", 0x27ab0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_POLARITY", 0x27ab4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_CMD", 0x27ab8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS", 0x27abc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR", 0x27ac0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR", 0x27ac4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR", 0x27ac8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC_OVR", 0x27ad0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TXD_PWR_DAC", 0x27ad4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP", 0x27ae0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP", 0x27ae4, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP", 0x27ae8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_SEG_DIS_APP", 0x27af0, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA", 0x27af8, 0 },
|
|
{ "XGMAC_PORT_HSS_TXD_EXT_ADDR", 0x27afc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_CFG_MODE", 0x27b00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXC_TEST_CTRL", 0x27b04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL", 0x27b08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL", 0x27b0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1", 0x27b10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2", 0x27b14, 0 },
|
|
{ "XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET", 0x27b18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_SIGDET_CTRL", 0x27b1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_CTRL", 0x27b20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE", 0x27b24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE", 0x27b28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL1", 0x27b2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL2", 0x27b30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_VGA_CTRL3", 0x27b34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET", 0x27b38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET", 0x27b3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET", 0x27b40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_OFFSET", 0x27b44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET", 0x27b48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_DACA_MIN", 0x27b4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXC_ADAC_CTRL", 0x27b50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL", 0x27b54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS", 0x27b58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H1", 0x27b5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H2", 0x27b60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H3", 0x27b64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H4", 0x27b68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_H5", 0x27b6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DAC_DPC", 0x27b70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXC_DDC", 0x27b74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXC_INTERNAL_STATUS", 0x27b78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL", 0x27b7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_CFG_MODE", 0x27b80, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXD_TEST_CTRL", 0x27b84, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL", 0x27b88, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL", 0x27b8c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1", 0x27b90, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2", 0x27b94, 0 },
|
|
{ "XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET", 0x27b98, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_SIGDET_CTRL", 0x27b9c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_CTRL", 0x27ba0, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE", 0x27ba4, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE", 0x27ba8, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL1", 0x27bac, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL2", 0x27bb0, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_VGA_CTRL3", 0x27bb4, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET", 0x27bb8, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET", 0x27bbc, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET", 0x27bc0, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_OFFSET", 0x27bc4, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET", 0x27bc8, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_DACA_MIN", 0x27bcc, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RXD_ADAC_CTRL", 0x27bd0, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL", 0x27bd4, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS", 0x27bd8, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H1", 0x27bdc, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H2", 0x27be0, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H3", 0x27be4, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H4", 0x27be8, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_H5", 0x27bec, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DAC_DPC", 0x27bf0, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RXD_DDC", 0x27bf4, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RXD_INTERNAL_STATUS", 0x27bf8, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL", 0x27bfc, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0", 0x27c00, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1", 0x27c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2", 0x27c08, 0 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3", 0x27c0c, 0 },
|
|
{ "VISEL", 4, 1 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "TCDIS", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4", 0x27c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_ANALOG_TEST_MUX", 0x27c14, 0 },
|
|
{ "XGMAC_PORT_HSS_PORT_EN_0", 0x27c18, 0 },
|
|
{ "RXDEN", 7, 1 },
|
|
{ "RXCEN", 6, 1 },
|
|
{ "TXDEN", 5, 1 },
|
|
{ "TXCEN", 4, 1 },
|
|
{ "RXBEN", 3, 1 },
|
|
{ "RXAEN", 2, 1 },
|
|
{ "TXBEN", 1, 1 },
|
|
{ "TXAEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_PORT_RESET_0", 0x27c20, 0 },
|
|
{ "RXDRST", 7, 1 },
|
|
{ "RXCRST", 6, 1 },
|
|
{ "TXDRST", 5, 1 },
|
|
{ "TXCRST", 4, 1 },
|
|
{ "RXBRST", 3, 1 },
|
|
{ "RXARST", 2, 1 },
|
|
{ "TXBRST", 1, 1 },
|
|
{ "TXARST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_CHARGE_PUMP_CTRL", 0x27c28, 0 },
|
|
{ "ENCPIS", 2, 1 },
|
|
{ "CPISEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_BAND_GAP_CTRL", 0x27c2c, 0 },
|
|
{ "XGMAC_PORT_HSS_LOFREQ_OVR", 0x27c30, 0 },
|
|
{ "LFREQ2", 3, 1 },
|
|
{ "LFREQ1", 2, 1 },
|
|
{ "LFREQO", 1, 1 },
|
|
{ "LFSEL", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL", 0x27c38, 0 },
|
|
{ "PFVAL", 2, 1 },
|
|
{ "PFEN", 1, 1 },
|
|
{ "VBADJ", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_MODE_CFG", 0x27c80, 0 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXTEST_CTRL", 0x27c84, 0 },
|
|
{ "TWDP", 5, 1 },
|
|
{ "TPGRST", 4, 1 },
|
|
{ "TPGEN", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_COEFF_CTRL", 0x27c88, 0 },
|
|
{ "AEINVPOL", 6, 1 },
|
|
{ "AESOURCE", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "SPEN", 1, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_MODE", 0x27c8c, 0 },
|
|
{ "DRVOFFT", 5, 1 },
|
|
{ "SLEW", 2, 3 },
|
|
{ "FFE", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL", 0x27c90, 0 },
|
|
{ "VLINC", 7, 1 },
|
|
{ "VLDEC", 6, 1 },
|
|
{ "LOPWR", 5, 1 },
|
|
{ "TDMEN", 4, 1 },
|
|
{ "DCCEN", 3, 1 },
|
|
{ "VHSEL", 2, 1 },
|
|
{ "IDAC", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER", 0x27c94, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER", 0x27c98, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_COEFF", 0x27ca0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_COEFF", 0x27ca4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_COEFF", 0x27ca8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR", 0x27cb0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_POLARITY", 0x27cb4, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NTXPOL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_CMD", 0x27cb8, 0 },
|
|
{ "CXPRESET", 13, 1 },
|
|
{ "CXINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_8023AP_AE_STATUS", 0x27cbc, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR", 0x27cc0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR", 0x27cc4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR", 0x27cc8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC_OVR", 0x27cd0, 0 },
|
|
{ "OPEN", 7, 1 },
|
|
{ "OPVAL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_TX_PWR_DAC", 0x27cd4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP0_IDAC_APP", 0x27ce0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP1_IDAC_APP", 0x27ce4, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_TAP2_IDAC_APP", 0x27ce8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_SEG_DIS_APP", 0x27cf0, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR_DATA", 0x27cf8, 0 },
|
|
{ "XGMAC_PORT_HSS_TX_EXT_ADDR", 0x27cfc, 0 },
|
|
{ "XADDR", 2, 4 },
|
|
{ "XWR", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_CFG_MODE", 0x27d00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_RXTEST_CTRL", 0x27d04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL", 0x27d08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTONSTUCK", 3, 1 },
|
|
{ "FREEZEFW", 2, 1 },
|
|
{ "RESETFW", 1, 1 },
|
|
{ "SSCENABLE", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL", 0x27d0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1", 0x27d10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "RTSEL", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2", 0x27d14, 0 },
|
|
{ "XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET", 0x27d18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_SIGDET_CTRL", 0x27d1c, 0 },
|
|
{ "SIGNSD", 13, 2 },
|
|
{ "DACSD", 8, 5 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_CTRL", 0x27d20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE", 0x27d24, 0 },
|
|
{ "ESAMP", 8, 8 },
|
|
{ "DSAMP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE", 0x27d28, 0 },
|
|
{ "SMODE", 8, 4 },
|
|
{ "ADCORR", 7, 1 },
|
|
{ "TRAINEN", 6, 1 },
|
|
{ "ASAMPQ", 3, 3 },
|
|
{ "ASAMP", 0, 3 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL1", 0x27d2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL2", 0x27d30, 0 },
|
|
{ "SHORTV", 10, 1 },
|
|
{ "VGAIN", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_VGA_CTRL3", 0x27d34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET", 0x27d38, 0 },
|
|
{ "D01SN", 13, 2 },
|
|
{ "D01AMP", 8, 5 },
|
|
{ "D00SN", 5, 2 },
|
|
{ "D00AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET", 0x27d3c, 0 },
|
|
{ "D11SN", 13, 2 },
|
|
{ "D11AMP", 8, 5 },
|
|
{ "D10SN", 5, 2 },
|
|
{ "D10AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET", 0x27d40, 0 },
|
|
{ "E1SN", 13, 2 },
|
|
{ "E1AMP", 8, 5 },
|
|
{ "E0SN", 5, 2 },
|
|
{ "E0AMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_OFFSET", 0x27d44, 0 },
|
|
{ "AOFFO", 8, 6 },
|
|
{ "AOFFE", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET", 0x27d48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_DACA_MIN", 0x27d4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "XGMAC_PORT_HSS_RX_ADAC_CTRL", 0x27d50, 0 },
|
|
{ "ADSN", 7, 2 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL", 0x27d54, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWIDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS", 0x27d58, 0 },
|
|
{ "EMBRDY", 10, 1 },
|
|
{ "EMBUMP", 7, 1 },
|
|
{ "EMMD", 5, 2 },
|
|
{ "EMPAT", 1, 1 },
|
|
{ "EMEN", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H1", 0x27d5c, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H2", 0x27d60, 0 },
|
|
{ "H2OSN", 13, 2 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN", 5, 2 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H3", 0x27d64, 0 },
|
|
{ "H3OSN", 12, 2 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN", 4, 2 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H4", 0x27d68, 0 },
|
|
{ "H4OSN", 12, 2 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4ESN", 4, 2 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_H5", 0x27d6c, 0 },
|
|
{ "H5OSN", 12, 2 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5ESN", 4, 2 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DAC_DPC", 0x27d70, 0 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "XGMAC_PORT_HSS_RX_DDC", 0x27d74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "XGMAC_PORT_HSS_RX_INTERNAL_STATUS", 0x27d78, 0 },
|
|
{ "BER6", 15, 1 },
|
|
{ "BER6VAL", 14, 1 },
|
|
{ "BER3VAL", 13, 1 },
|
|
{ "DPCCMP", 9, 1 },
|
|
{ "DACCMP", 8, 1 },
|
|
{ "DDCCMP", 7, 1 },
|
|
{ "AERRFLG", 6, 1 },
|
|
{ "WERRFLG", 5, 1 },
|
|
{ "TRCMP", 4, 1 },
|
|
{ "VLCKF", 3, 1 },
|
|
{ "ROCADJ", 2, 1 },
|
|
{ "ROCCMP", 1, 1 },
|
|
{ "OCCMP", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL", 0x27d7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "XGMAC_PORT_HSS_TXRX_CFG_MODE", 0x27e00, 0 },
|
|
{ "BW810", 8, 1 },
|
|
{ "AUXCLK", 7, 1 },
|
|
{ "DMSEL", 4, 3 },
|
|
{ "BWSEL", 2, 2 },
|
|
{ "RTSEL", 0, 2 },
|
|
{ "XGMAC_PORT_HSS_TXRXTEST_CTRL", 0x27e04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "LBFRCERROR", 10, 1 },
|
|
{ "LBERROR", 9, 1 },
|
|
{ "LBSYNC", 8, 1 },
|
|
{ "FDWRAPCLK", 7, 1 },
|
|
{ "FDWRAP", 6, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PRBSSEL", 0, 3 },
|
|
{ NULL }
|
|
};
|