c3c50c4e3a
Further experimentation showed that some Dell 2450 machines with the prevention kludge installed still got T_RESERVED traps. CPU interrupt vector 0x7A was observed to be triggered. This might have been the bitwise OR of two different vectors sent from each of the IOAPICs at the same time. IOAPIC #0: 0x68 --> irq 8: RTC timer interrupt IOAPIC #1: 0x32 --> irq 18: scsi host adapter or network interface ---- 0x7a --> T_RESERVED Both IOAPICs had ID 0. Appendix B.3 in the MP spec indicates that the operating system is responsible for assigning unique IDs to the IOAPICs. The enclosed patch programs the IOAPIC IDs according to the IOAPIC entries in the MP table. Submitted by: tegge
749 lines
17 KiB
C
749 lines
17 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_smp.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <machine/smptests.h> /** TEST_TEST1 */
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#include <machine/smp.h>
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#include <machine/mpapic.h>
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#include <machine/segments.h>
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#include <i386/isa/intr_machdep.h> /* Xspuriousint() */
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/* EISA Edge/Level trigger control registers */
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#define ELCR0 0x4d0 /* eisa irq 0-7 */
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#define ELCR1 0x4d1 /* eisa irq 8-15 */
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/*
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* pointers to pmapped apic hardware.
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*/
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#if defined(APIC_IO)
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volatile ioapic_t *ioapic[NAPIC];
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#endif /* APIC_IO */
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/*
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* Enable APIC, configure interrupts.
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*/
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void
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apic_initialize(void)
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{
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u_int temp;
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/* setup LVT1 as ExtINT */
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temp = lapic.lvt_lint0;
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temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
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if (cpuid == 0)
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temp |= 0x00000700; /* process ExtInts */
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else
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temp |= 0x00010700; /* mask ExtInts */
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lapic.lvt_lint0 = temp;
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/* setup LVT2 as NMI, masked till later... */
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temp = lapic.lvt_lint1;
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temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
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temp |= 0x00010400; /* masked, edge trigger, active hi */
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lapic.lvt_lint1 = temp;
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/* set the Task Priority Register as needed */
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temp = lapic.tpr;
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temp &= ~APIC_TPR_PRIO; /* clear priority field */
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temp |= LOPRIO_LEVEL; /* allow INT arbitration */
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lapic.tpr = temp;
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/* enable the local APIC */
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temp = lapic.svr;
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temp |= APIC_SVR_SWEN; /* software enable APIC */
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temp &= ~APIC_SVR_FOCUS; /* enable 'focus processor' */
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/* set the 'spurious INT' vector */
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if ((XSPURIOUSINT_OFFSET & APIC_SVR_VEC_FIX) != APIC_SVR_VEC_FIX)
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panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
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temp &= ~APIC_SVR_VEC_PROG; /* clear (programmable) vector field */
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temp |= (XSPURIOUSINT_OFFSET & APIC_SVR_VEC_PROG);
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#if defined(TEST_TEST1)
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if (cpuid == GUARD_CPU) {
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temp &= ~APIC_SVR_SWEN; /* software DISABLE APIC */
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}
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#endif /** TEST_TEST1 */
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lapic.svr = temp;
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if (bootverbose)
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apic_dump("apic_initialize()");
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}
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/*
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* dump contents of local APIC registers
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*/
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void
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apic_dump(char* str)
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{
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printf("SMP: CPU%d %s:\n", cpuid, str);
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printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
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lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
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}
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#if defined(APIC_IO)
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/*
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* IO APIC code,
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*/
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#define IOAPIC_ISA_INTS 16
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#define REDIRCNT_IOAPIC(A) \
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((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
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static int trigger __P((int apic, int pin, u_int32_t * flags));
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static void polarity __P((int apic, int pin, u_int32_t * flags, int level));
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#define DEFAULT_FLAGS \
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((u_int32_t) \
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(IOART_INTMSET | \
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IOART_DESTPHY | \
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IOART_DELLOPRI))
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#define DEFAULT_ISA_FLAGS \
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((u_int32_t) \
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(IOART_INTMSET | \
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IOART_TRGREDG | \
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IOART_INTAHI | \
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IOART_DESTPHY | \
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IOART_DELLOPRI))
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void
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io_apic_set_id(int apic, int id)
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{
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u_int32_t ux;
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ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
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if (((ux & APIC_ID_MASK) >> 24) != id) {
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ux &= ~APIC_ID_MASK; /* clear the ID field */
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ux |= (id << 24);
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io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
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ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
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if (((ux & APIC_ID_MASK) >> 24) != id)
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panic("can't control IO APIC #%d ID, reg: 0x%08x",
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apic, ux);
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}
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}
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/*
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* Setup the IO APIC.
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*/
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extern int apic_pin_trigger; /* 'opaque' */
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int
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io_apic_setup(int apic)
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{
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int maxpin;
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u_char select; /* the select register is 8 bits */
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u_int32_t flags; /* the window register is 32 bits */
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u_int32_t target; /* the window register is 32 bits */
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u_int32_t vector; /* the window register is 32 bits */
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int pin, level;
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target = IOART_DEST;
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if (apic == 0)
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apic_pin_trigger = 0; /* default to edge-triggered */
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maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
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printf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
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for (pin = 0; pin < maxpin; ++pin) {
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int bus, bustype, irq;
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select = pin * 2 + IOAPIC_REDTBL0; /* register */
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/*
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* Always disable interrupts, and by default map
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* pin X to IRQX because the disable doesn't stick
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* and the uninitialize vector will get translated
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* into a panic.
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*
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* This is correct for IRQs 1 and 3-15. In the other cases,
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* any robust driver will handle the spurious interrupt, and
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* the effective NOP beats a panic.
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*
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* A dedicated "bogus interrupt" entry in the IDT would
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* be a nicer hack, although some one should find out
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* why some systems are generating interrupts when they
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* shouldn't and stop the carnage.
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*/
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vector = NRSVIDT + pin; /* IDT vec */
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io_apic_write(apic, select,
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(io_apic_read(apic, select) & ~IOART_INTMASK
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& ~0xff)|IOART_INTMSET|vector);
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/* we only deal with vectored INTs here */
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if (apic_int_type(apic, pin) != 0)
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continue;
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irq = apic_irq(apic, pin);
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if (irq < 0)
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continue;
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/* determine the bus type for this pin */
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bus = apic_src_bus_id(apic, pin);
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if (bus == -1)
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continue;
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bustype = apic_bus_type(bus);
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if ((bustype == ISA) &&
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(pin < IOAPIC_ISA_INTS) &&
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(irq == pin) &&
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(apic_polarity(apic, pin) == 0x1) &&
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(apic_trigger(apic, pin) == 0x3)) {
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/*
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* A broken BIOS might describe some ISA
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* interrupts as active-high level-triggered.
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* Use default ISA flags for those interrupts.
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*/
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flags = DEFAULT_ISA_FLAGS;
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} else {
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/*
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* Program polarity and trigger mode according to
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* interrupt entry.
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*/
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flags = DEFAULT_FLAGS;
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level = trigger(apic, pin, &flags);
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if (level == 1)
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apic_pin_trigger |= (1 << irq);
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polarity(apic, pin, &flags, level);
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}
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/* program the appropriate registers */
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if (apic != 0 || pin != irq)
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printf("IOAPIC #%d intpin %d -> irq %d\n",
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apic, pin, irq);
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vector = NRSVIDT + irq; /* IDT vec */
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io_apic_write(apic, select, flags | vector);
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io_apic_write(apic, select + 1, target);
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}
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/* return GOOD status */
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return 0;
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}
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#undef DEFAULT_ISA_FLAGS
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#undef DEFAULT_FLAGS
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#define DEFAULT_EXTINT_FLAGS \
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((u_int32_t) \
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(IOART_INTMSET | \
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IOART_TRGREDG | \
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IOART_INTAHI | \
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IOART_DESTPHY | \
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IOART_DELLOPRI))
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/*
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* Setup the source of External INTerrupts.
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*/
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int
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ext_int_setup(int apic, int intr)
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{
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u_char select; /* the select register is 8 bits */
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u_int32_t flags; /* the window register is 32 bits */
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u_int32_t target; /* the window register is 32 bits */
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u_int32_t vector; /* the window register is 32 bits */
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if (apic_int_type(apic, intr) != 3)
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return -1;
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target = IOART_DEST;
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select = IOAPIC_REDTBL0 + (2 * intr);
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vector = NRSVIDT + intr;
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flags = DEFAULT_EXTINT_FLAGS;
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io_apic_write(apic, select, flags | vector);
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io_apic_write(apic, select + 1, target);
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return 0;
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}
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#undef DEFAULT_EXTINT_FLAGS
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/*
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* Set the trigger level for an IO APIC pin.
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*/
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static int
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trigger(int apic, int pin, u_int32_t * flags)
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{
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int id;
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int eirq;
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int level;
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static int intcontrol = -1;
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switch (apic_trigger(apic, pin)) {
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case 0x00:
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break;
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case 0x01:
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*flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
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return 0;
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case 0x03:
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*flags |= IOART_TRGRLVL;
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return 1;
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case -1:
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default:
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goto bad;
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}
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if ((id = apic_src_bus_id(apic, pin)) == -1)
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goto bad;
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switch (apic_bus_type(id)) {
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case ISA:
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*flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
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return 0;
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case EISA:
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eirq = apic_src_bus_irq(apic, pin);
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if (eirq < 0 || eirq > 15) {
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printf("EISA IRQ %d?!?!\n", eirq);
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goto bad;
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}
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if (intcontrol == -1) {
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intcontrol = inb(ELCR1) << 8;
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intcontrol |= inb(ELCR0);
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printf("EISA INTCONTROL = %08x\n", intcontrol);
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}
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/* Use ELCR settings to determine level or edge mode */
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level = (intcontrol >> eirq) & 1;
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/*
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* Note that on older Neptune chipset based systems, any
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* pci interrupts often show up here and in the ELCR as well
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* as level sensitive interrupts attributed to the EISA bus.
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*/
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if (level)
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*flags |= IOART_TRGRLVL;
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else
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*flags &= ~IOART_TRGRLVL;
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return level;
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case PCI:
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*flags |= IOART_TRGRLVL;
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return 1;
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case -1:
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default:
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goto bad;
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}
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bad:
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panic("bad APIC IO INT flags");
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}
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|
|
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/*
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* Set the polarity value for an IO APIC pin.
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*/
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static void
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polarity(int apic, int pin, u_int32_t * flags, int level)
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{
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int id;
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switch (apic_polarity(apic, pin)) {
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case 0x00:
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break;
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case 0x01:
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*flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
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return;
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case 0x03:
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*flags |= IOART_INTALO;
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return;
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case -1:
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default:
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goto bad;
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}
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if ((id = apic_src_bus_id(apic, pin)) == -1)
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goto bad;
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switch (apic_bus_type(id)) {
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case ISA:
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*flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
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return;
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case EISA:
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/* polarity converter always gives active high */
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*flags &= ~IOART_INTALO;
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return;
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|
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case PCI:
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*flags |= IOART_INTALO;
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return;
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|
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case -1:
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default:
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goto bad;
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}
|
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bad:
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panic("bad APIC IO INT flags");
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}
|
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|
|
|
|
/*
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* Print contents of apic_imen.
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*/
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extern u_int apic_imen; /* keep apic_imen 'opaque' */
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void
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imen_dump(void)
|
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{
|
|
int x;
|
|
|
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printf("SMP: enabled INTs: ");
|
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for (x = 0; x < 24; ++x)
|
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if ((apic_imen & (1 << x)) == 0)
|
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printf("%d, ", x);
|
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printf("apic_imen: 0x%08x\n", apic_imen);
|
|
}
|
|
|
|
|
|
/*
|
|
* Inter Processor Interrupt functions.
|
|
*/
|
|
|
|
|
|
/*
|
|
* Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
|
|
*
|
|
* destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
|
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* vector is any valid SYSTEM INT vector
|
|
* delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
|
|
*/
|
|
#define DETECT_DEADLOCK
|
|
int
|
|
apic_ipi(int dest_type, int vector, int delivery_mode)
|
|
{
|
|
u_long icr_lo;
|
|
|
|
#if defined(DETECT_DEADLOCK)
|
|
#define MAX_SPIN1 10000000
|
|
#define MAX_SPIN2 1000
|
|
int x;
|
|
|
|
/* "lazy delivery", ie we only barf if they stack up on us... */
|
|
for (x = MAX_SPIN1; x; --x) {
|
|
if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
|
|
break;
|
|
}
|
|
if (x == 0)
|
|
panic("apic_ipi was stuck");
|
|
#endif /* DETECT_DEADLOCK */
|
|
|
|
/* build IRC_LOW */
|
|
icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
|
|
| dest_type | delivery_mode | vector;
|
|
|
|
/* write APIC ICR */
|
|
lapic.icr_lo = icr_lo;
|
|
|
|
/* wait for pending status end */
|
|
#if defined(DETECT_DEADLOCK)
|
|
for (x = MAX_SPIN2; x; --x) {
|
|
if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
|
|
break;
|
|
}
|
|
#ifdef needsattention
|
|
/*
|
|
* XXX FIXME:
|
|
* The above loop waits for the message to actually be delivered.
|
|
* It breaks out after an arbitrary timout on the theory that it eventually
|
|
* will be delivered and we will catch a real failure on the next entry to
|
|
* this function, which would panic().
|
|
* We could skip this wait entirely, EXCEPT it probably protects us from
|
|
* other "less robust" routines that assume the message was delivered and
|
|
* acted upon when this function returns. TLB shootdowns are one such
|
|
* "less robust" function.
|
|
*/
|
|
if (x == 0)
|
|
printf("apic_ipi might be stuck\n");
|
|
#endif
|
|
#undef MAX_SPIN2
|
|
#undef MAX_SPIN1
|
|
#else
|
|
while (lapic.icr_lo & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
#endif /* DETECT_DEADLOCK */
|
|
|
|
/** XXX FIXME: return result */
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
apic_ipi_singledest(int cpu, int vector, int delivery_mode)
|
|
{
|
|
u_long icr_lo;
|
|
u_long icr_hi;
|
|
u_long eflags;
|
|
|
|
#if defined(DETECT_DEADLOCK)
|
|
#define MAX_SPIN1 10000000
|
|
#define MAX_SPIN2 1000
|
|
int x;
|
|
|
|
/* "lazy delivery", ie we only barf if they stack up on us... */
|
|
for (x = MAX_SPIN1; x; --x) {
|
|
if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
|
|
break;
|
|
}
|
|
if (x == 0)
|
|
panic("apic_ipi was stuck");
|
|
#endif /* DETECT_DEADLOCK */
|
|
|
|
eflags = read_eflags();
|
|
__asm __volatile("cli" : : : "memory");
|
|
icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
|
|
icr_hi |= (CPU_TO_ID(cpu) << 24);
|
|
lapic.icr_hi = icr_hi;
|
|
|
|
/* build IRC_LOW */
|
|
icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
|
|
| APIC_DEST_DESTFLD | delivery_mode | vector;
|
|
|
|
/* write APIC ICR */
|
|
lapic.icr_lo = icr_lo;
|
|
write_eflags(eflags);
|
|
|
|
/* wait for pending status end */
|
|
#if defined(DETECT_DEADLOCK)
|
|
for (x = MAX_SPIN2; x; --x) {
|
|
if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0)
|
|
break;
|
|
}
|
|
#ifdef needsattention
|
|
/*
|
|
* XXX FIXME:
|
|
* The above loop waits for the message to actually be delivered.
|
|
* It breaks out after an arbitrary timout on the theory that it eventually
|
|
* will be delivered and we will catch a real failure on the next entry to
|
|
* this function, which would panic().
|
|
* We could skip this wait entirely, EXCEPT it probably protects us from
|
|
* other "less robust" routines that assume the message was delivered and
|
|
* acted upon when this function returns. TLB shootdowns are one such
|
|
* "less robust" function.
|
|
*/
|
|
if (x == 0)
|
|
printf("apic_ipi might be stuck\n");
|
|
#endif
|
|
#undef MAX_SPIN2
|
|
#undef MAX_SPIN1
|
|
#else
|
|
while (lapic.icr_lo & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
#endif /* DETECT_DEADLOCK */
|
|
|
|
/** XXX FIXME: return result */
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
|
|
*
|
|
* target contains a bitfield with a bit set for selected APICs.
|
|
* vector is any valid SYSTEM INT vector
|
|
* delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
|
|
*/
|
|
int
|
|
selected_apic_ipi(u_int target, int vector, int delivery_mode)
|
|
{
|
|
int x;
|
|
int status;
|
|
|
|
if (target & ~0x7fff)
|
|
return -1; /* only 15 targets allowed */
|
|
|
|
for (status = 0, x = 0; x <= 14; ++x)
|
|
if (target & (1 << x)) {
|
|
|
|
/* send the IPI */
|
|
if (apic_ipi_singledest(x, vector,
|
|
delivery_mode) == -1)
|
|
status |= (1 << x);
|
|
}
|
|
return status;
|
|
}
|
|
|
|
|
|
#if defined(READY)
|
|
/*
|
|
* Send an IPI INTerrupt containing 'vector' to CPU 'target'
|
|
* NOTE: target is a LOGICAL APIC ID
|
|
*/
|
|
int
|
|
selected_proc_ipi(int target, int vector)
|
|
{
|
|
u_long icr_lo;
|
|
u_long icr_hi;
|
|
|
|
/* write the destination field for the target AP */
|
|
icr_hi = (lapic.icr_hi & ~APIC_ID_MASK) |
|
|
(cpu_num_to_apic_id[target] << 24);
|
|
lapic.icr_hi = icr_hi;
|
|
|
|
/* write command */
|
|
icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) |
|
|
APIC_DEST_DESTFLD | APIC_DELMODE_FIXED | vector;
|
|
lapic.icr_lo = icr_lo;
|
|
|
|
/* wait for pending status end */
|
|
while (lapic.icr_lo & APIC_DELSTAT_MASK)
|
|
/* spin */ ;
|
|
|
|
return 0; /** XXX FIXME: return result */
|
|
}
|
|
#endif /* READY */
|
|
|
|
#endif /* APIC_IO */
|
|
|
|
|
|
/*
|
|
* Timer code, in development...
|
|
* - suggested by rgrimes@gndrsh.aac.dev.com
|
|
*/
|
|
|
|
/** XXX FIXME: temp hack till we can determin bus clock */
|
|
#ifndef BUS_CLOCK
|
|
#define BUS_CLOCK 66000000
|
|
#define bus_clock() 66000000
|
|
#endif
|
|
|
|
#if defined(READY)
|
|
int acquire_apic_timer __P((void));
|
|
int release_apic_timer __P((void));
|
|
|
|
/*
|
|
* Acquire the APIC timer for exclusive use.
|
|
*/
|
|
int
|
|
acquire_apic_timer(void)
|
|
{
|
|
#if 1
|
|
return 0;
|
|
#else
|
|
/** XXX FIXME: make this really do something */
|
|
panic("APIC timer in use when attempting to aquire");
|
|
#endif
|
|
}
|
|
|
|
|
|
/*
|
|
* Return the APIC timer.
|
|
*/
|
|
int
|
|
release_apic_timer(void)
|
|
{
|
|
#if 1
|
|
return 0;
|
|
#else
|
|
/** XXX FIXME: make this really do something */
|
|
panic("APIC timer was already released");
|
|
#endif
|
|
}
|
|
#endif /* READY */
|
|
|
|
|
|
/*
|
|
* Load a 'downcount time' in uSeconds.
|
|
*/
|
|
void
|
|
set_apic_timer(int value)
|
|
{
|
|
u_long lvtt;
|
|
long ticks_per_microsec;
|
|
|
|
/*
|
|
* Calculate divisor and count from value:
|
|
*
|
|
* timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
|
|
* value == time in uS
|
|
*/
|
|
lapic.dcr_timer = APIC_TDCR_1;
|
|
ticks_per_microsec = bus_clock() / 1000000;
|
|
|
|
/* configure timer as one-shot */
|
|
lvtt = lapic.lvt_timer;
|
|
lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS | APIC_LVTT_M | APIC_LVTT_TM);
|
|
lvtt |= APIC_LVTT_M; /* no INT, one-shot */
|
|
lapic.lvt_timer = lvtt;
|
|
|
|
/* */
|
|
lapic.icr_timer = value * ticks_per_microsec;
|
|
}
|
|
|
|
|
|
/*
|
|
* Read remaining time in timer.
|
|
*/
|
|
int
|
|
read_apic_timer(void)
|
|
{
|
|
#if 0
|
|
/** XXX FIXME: we need to return the actual remaining time,
|
|
* for now we just return the remaining count.
|
|
*/
|
|
#else
|
|
return lapic.ccr_timer;
|
|
#endif
|
|
}
|
|
|
|
|
|
/*
|
|
* Spin-style delay, set delay time in uS, spin till it drains.
|
|
*/
|
|
void
|
|
u_sleep(int count)
|
|
{
|
|
set_apic_timer(count);
|
|
while (read_apic_timer())
|
|
/* spin */ ;
|
|
}
|