56efeb9567
Differential Revision: https://reviews.freebsd.org/D3159 Submitted by: erj MFC after: 2 weeks
93 lines
3.6 KiB
C
93 lines
3.6 KiB
C
/******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_82541_H_
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#define _E1000_82541_H_
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#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
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#define IGP01E1000_PHY_CHANNEL_NUM 4
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#define IGP01E1000_PHY_AGC_A 0x1172
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#define IGP01E1000_PHY_AGC_B 0x1272
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#define IGP01E1000_PHY_AGC_C 0x1472
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#define IGP01E1000_PHY_AGC_D 0x1872
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#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
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#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
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#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
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#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
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#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
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#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
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#define IGP01E1000_PHY_DSP_RESET 0x1F33
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#define IGP01E1000_PHY_DSP_FFE 0x1F35
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#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
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#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
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#define IGP01E1000_IEEE_FORCE_GIG 0x0140
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#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
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#define IGP01E1000_AGC_LENGTH_SHIFT 7
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#define IGP01E1000_AGC_RANGE 10
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#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
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#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
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#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
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#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
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#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
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#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
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#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
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#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
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#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
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#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
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#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
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#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
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#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
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#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
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#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
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#define IGP01E1000_MSE_CHANNEL_D 0x000F
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#define IGP01E1000_MSE_CHANNEL_C 0x00F0
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#define IGP01E1000_MSE_CHANNEL_B 0x0F00
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#define IGP01E1000_MSE_CHANNEL_A 0xF000
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void e1000_init_script_state_82541(struct e1000_hw *hw, bool state);
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#endif
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