301 lines
7.0 KiB
C
301 lines
7.0 KiB
C
/*-
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* Copyright (c) 2004 John Birrell
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* AMD Elan SC520 Memory Mapped Configuration Region (MMCR).
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*
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* The layout of this structure is documented by AMD in the Elan SC520
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* Microcontroller Register Set Manual. The field names match those
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* described in that document. The overall structure size must be 4096
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* bytes. Ignore fields with the 'pad' prefix - they are only present for
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* alignment purposes.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ELAN_MMCR_H_
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#define _MACHINE_ELAN_MMCR_H_ 1
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struct elan_mmcr {
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/* CPU */
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u_int16_t REVID;
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u_int8_t CPUCTL;
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u_int8_t pad_0x003[0xd];
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/* SDRAM Controller */
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u_int16_t DRCCTL;
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u_int16_t DRCTMCTL;
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u_int16_t DRCCFG;
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u_int16_t DRCBENDADR;
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u_int8_t pad_0x01a[0x6];
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u_int8_t ECCCTL;
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u_int8_t ECCSTA;
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u_int8_t ECCCKBPOS;
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u_int8_t ECCCKTEST;
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u_int32_t ECCSBADD;
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u_int32_t ECCMBADD;
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u_int8_t pad_0x02c[0x14];
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/* SDRAM Buffer */
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u_int8_t DBCTL;
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u_int8_t pad_0x041[0xf];
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/* ROM/Flash Controller */
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u_int16_t BOOTCSCTL;
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u_int8_t pad_0x052[0x2];
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u_int16_t ROMCS1CTL;
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u_int16_t ROMCS2CTL;
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u_int8_t pad_0x058[0x8];
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/* PCI Bus Host Bridge */
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u_int16_t HBCTL;
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u_int16_t HBTGTIRQCTL;
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u_int16_t HBTGTIRQSTA;
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u_int16_t HBMSTIRQCTL;
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u_int16_t HBMSTIRQSTA;
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u_int8_t pad_0x06a[0x2];
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u_int32_t MSTINTADD;
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/* System Arbitration */
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u_int8_t SYSARBCTL;
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u_int8_t PCIARBSTA;
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u_int16_t SYSARBMENB;
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u_int32_t ARBPRICTL;
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u_int8_t pad_0x078[0x8];
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/* System Address Mapping */
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u_int32_t ADDDECCTL;
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u_int32_t WPVSTA;
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u_int32_t PAR0;
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u_int32_t PAR1;
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u_int32_t PAR2;
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u_int32_t PAR3;
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u_int32_t PAR4;
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u_int32_t PAR5;
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u_int32_t PAR6;
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u_int32_t PAR7;
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u_int32_t PAR8;
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u_int32_t PAR9;
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u_int32_t PAR10;
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u_int32_t PAR11;
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u_int32_t PAR12;
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u_int32_t PAR13;
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u_int32_t PAR14;
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u_int32_t PAR15;
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u_int8_t pad_0x0c8[0xb38];
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/* GP Bus Controller */
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u_int8_t GPECHO;
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u_int8_t GPCSDW;
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u_int16_t GPCSQUAL;
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u_int8_t pad_0xc04[0x4];
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u_int8_t GPCSRT;
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u_int8_t GPCSPW;
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u_int8_t GPCSOFF;
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u_int8_t GPRDW;
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u_int8_t GPRDOFF;
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u_int8_t GPWRW;
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u_int8_t GPWROFF;
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u_int8_t GPALEW;
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u_int8_t GPALEOFF;
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u_int8_t pad_0xc11[0xf];
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/* Programmable Input/Output */
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u_int16_t PIOPFS15_0;
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u_int16_t PIOPFS31_16;
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u_int8_t CSPFS;
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u_int8_t pad_0xc25;
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u_int8_t CLKSEL;
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u_int8_t pad_0xc27;
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u_int16_t DSCTL;
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u_int16_t PIODIR15_0;
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u_int16_t PIODIR31_16;
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u_int8_t pad_0xc2e[0x2];
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u_int16_t PIODATA15_0;
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u_int16_t PIODATA31_16;
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u_int16_t PIOSET15_0;
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u_int16_t PIOSET31_16;
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u_int16_t PIOCLR15_0;
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u_int16_t PIOCLR31_16;
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u_int8_t pad_0xc3c[0x24];
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/* Software Timer */
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u_int16_t SWTMRMILLI;
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u_int16_t SWTMRMICRO;
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u_int8_t SWTMRCFG;
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u_int8_t pad_0xc65[0xb];
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/* General-Purpose Timers */
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u_int8_t GPTMRSTA;
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u_int8_t pad_0xc71;
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u_int16_t GPTMR0CTL;
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u_int16_t GPTMR0CNT;
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u_int16_t GPTMR0MAXCMPA;
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u_int16_t GPTMR0MAXCMPB;
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u_int16_t GPTMR1CTL;
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u_int16_t GPTMR1CNT;
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u_int16_t GPTMR1MAXCMPA;
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u_int16_t GPTMR1MAXCMPB;
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u_int16_t GPTMR2CTL;
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u_int16_t GPTMR2CNT;
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u_int8_t pad_0xc86[0x8];
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u_int16_t GPTMR2MAXCMPA;
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u_int8_t pad_0xc90[0x20];
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/* Watchdog Timer */
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u_int16_t WDTMRCTL;
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u_int16_t WDTMRCNTL;
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u_int16_t WDTMRCNTH;
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u_int8_t pad_0xcb6[0xa];
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/* UART Serial Ports */
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u_int8_t UART1CTL;
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u_int8_t UART1STA;
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u_int8_t UART1FCRSHAD;
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u_int8_t pad_0xcc3;
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u_int8_t UART2CTL;
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u_int8_t UART2STA;
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u_int8_t UART2FCRSHAD;
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u_int8_t pad_0xcc7[0x9];
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/* Synchronous Serial Interface */
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u_int8_t SSICTL;
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u_int8_t SSIXMIT;
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u_int8_t SSICMD;
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u_int8_t SSISTA;
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u_int8_t SSIRCV;
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u_int8_t pad_0xcd5[0x2b];
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/* Programmable Interrupt Controller */
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u_int8_t PICICR;
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u_int8_t pad_0xd01;
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u_int8_t MPICMODE;
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u_int8_t SL1PICMODE;
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u_int8_t SL2PICMODE;
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u_int8_t pad_0xd05[0x3];
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u_int16_t SWINT16_1;
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u_int8_t SWINT22_17;
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u_int8_t pad_0xd0b[0x5];
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u_int16_t INTPINPOL;
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u_int8_t pad_0xd12[0x2];
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u_int16_t PCIHOSTMAP;
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u_int8_t pad_0xd16[0x2];
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u_int16_t ECCMAP;
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u_int8_t GPTMR0MAP;
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u_int8_t GPTMR1MAP;
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u_int8_t GPTMR2MAP;
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u_int8_t pad_0xd1d[0x3];
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u_int8_t PIT0MAP;
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u_int8_t PIT1MAP;
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u_int8_t PIT2MAP;
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u_int8_t pad_0xd23[0x5];
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u_int8_t UART1MAP;
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u_int8_t UART2MAP;
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u_int8_t pad_0xd2a[0x6];
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u_int8_t PCIINTAMAP;
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u_int8_t PCIINTBMAP;
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u_int8_t PCIINTCMAP;
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u_int8_t PCIINTDMAP;
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u_int8_t pad_0xd34[0xc];
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u_int8_t DMABCINTMAP;
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u_int8_t SSIMAP;
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u_int8_t WDTMAP;
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u_int8_t RTCMAP;
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u_int8_t WPVMAP;
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u_int8_t ICEMAP;
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u_int8_t FERRMAP;
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u_int8_t pad_0xd47[0x9];
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u_int8_t GP0IMAP;
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u_int8_t GP1IMAP;
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u_int8_t GP2IMAP;
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u_int8_t GP3IMAP;
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u_int8_t GP4IMAP;
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u_int8_t GP5IMAP;
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u_int8_t GP6IMAP;
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u_int8_t GP7IMAP;
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u_int8_t GP8IMAP;
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u_int8_t GP9IMAP;
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u_int8_t GP10IMAP;
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u_int8_t pad_0xd5b[0x15];
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/* Reset Generation */
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u_int8_t SYSINFO;
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u_int8_t pad_0xd71;
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u_int8_t RESCFG;
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u_int8_t pad_0xd73;
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u_int8_t RESSTA;
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u_int8_t pad_0xd75[0xb];
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/* GP DMA Controller */
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u_int8_t GPDMACTL;
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u_int8_t GPDMAMMIO;
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u_int16_t GPDMAEXTCHMAPA;
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u_int16_t GPDMAEXTCHMAPB;
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u_int8_t GPDMAEXTPG0;
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u_int8_t GPDMAEXTPG1;
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u_int8_t GPDMAEXTPG2;
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u_int8_t GPDMAEXTPG3;
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u_int8_t GPDMAEXTPG5;
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u_int8_t GPDMAEXTPG6;
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u_int8_t GPDMAEXTPG7;
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u_int8_t pad_0xd8d[0x3];
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u_int8_t GPDMAEXTTC3;
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u_int8_t GPDMAEXTTC5;
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u_int8_t GPDMAEXTTC6;
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u_int8_t GPDMAEXTTC7;
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u_int8_t pad_0xd94[0x4];
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u_int8_t GPDMABCCTL;
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u_int8_t GPDMABCSTA;
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u_int8_t GPDMABSINTENB;
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u_int8_t GPDMABCVAL;
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u_int8_t pad_0xd9c[0x4];
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u_int16_t GPDMANXTADDL3;
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u_int16_t GPDMANXTADDH3;
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u_int16_t GPDMANXTADDL5;
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u_int16_t GPDMANXTADDH5;
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u_int16_t GPDMANXTADDL6;
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u_int16_t GPDMANXTADDH6;
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u_int16_t GPDMANXTADDL7;
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u_int16_t GPDMANXTADDH7;
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u_int16_t GPDMANXTTCL3;
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u_int8_t GPDMANXTTCH3;
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u_int8_t pad_0xdb3;
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u_int16_t GPDMANXTTCL5;
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u_int8_t GPDMANXTTCH5;
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u_int8_t pad_0xdb7;
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u_int16_t GPDMANXTTCL6;
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u_int8_t GPDMANXTTCH6;
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u_int8_t pad_0xdbb;
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u_int16_t GPDMANXTTCL7;
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u_int8_t GPDMANXTTCH7;
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u_int8_t pad_0xdc0[0x240];
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};
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CTASSERT(sizeof(struct elan_mmcr) == 4096);
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extern volatile struct elan_mmcr * elan_mmcr;
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#endif /* _MACHINE_ELAN_MMCR_H_ */
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