298341aaac
(which should be a PCIE Gen 3 slot for this adapter) by looking back thru the PCI parent devices to the slot device. The fix above also corrects the bandwidth display to GT/s rather than the incorrect Gb/s Next, allow the use of ALTQ if you select the compile option IXGBE_LEGACY_TX. Allow the use of 'unsupported' optic modules by a compile option as well. Add a phy reset capability into the stop code, this is so a static configured driver will still behave properly when taken down (not being able to unload it). This revision synchronizes the shared code with Intel internal current code, and note that it now includes DCB supporting code, this was necessitated by some internal changes with the code, but it also will provide the opportunity to develop this feature in the core driver down the road. I have edited the README to get rid of some of the worse anachronisms in it as well, its by no means as robust as I might wish at this point however. Oh, I also have included some conditional stuff in the code so it will be compatible in both the 9.X and 10 environments. Performance has been a focus in recent changes and I believe this revision driver will perform very well in most workloads. MFC after: 2 weeks
360 lines
10 KiB
C
360 lines
10 KiB
C
/******************************************************************************
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Copyright (c) 2001-2013, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82598.h"
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/**
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* ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
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* @hw: pointer to hardware structure
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* @stats: pointer to statistics structure
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* @tc_count: Number of elements in bwg_array.
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*
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* This function returns the status data for each of the Traffic Classes in use.
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*/
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s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
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struct ixgbe_hw_stats *stats,
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u8 tc_count)
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{
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int tc;
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DEBUGFUNC("dcb_get_tc_stats");
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if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
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return IXGBE_ERR_PARAM;
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/* Statistics pertaining to each traffic class */
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for (tc = 0; tc < tc_count; tc++) {
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/* Transmitted Packets */
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stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
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/* Transmitted Bytes */
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stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
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/* Received Packets */
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stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
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/* Received Bytes */
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stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
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#if 0
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/* Can we get rid of these?? Consequently, getting rid
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* of the tc_stats structure.
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*/
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tc_stats_array[up]->in_overflow_discards = 0;
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tc_stats_array[up]->out_overflow_discards = 0;
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#endif
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}
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
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* @hw: pointer to hardware structure
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* @stats: pointer to statistics structure
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* @tc_count: Number of elements in bwg_array.
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*
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* This function returns the CBFC status data for each of the Traffic Classes.
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*/
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s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
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struct ixgbe_hw_stats *stats,
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u8 tc_count)
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{
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int tc;
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DEBUGFUNC("dcb_get_pfc_stats");
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if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
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return IXGBE_ERR_PARAM;
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for (tc = 0; tc < tc_count; tc++) {
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/* Priority XOFF Transmitted */
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stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
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/* Priority XOFF Received */
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stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
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}
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Rx Data Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
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u16 *max, u8 *tsa)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
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IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
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/* Enable Arbiter */
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reg &= ~IXGBE_RMCS_ARBDIS;
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/* Enable Receive Recycle within the BWG */
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reg |= IXGBE_RMCS_RRM;
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/* Enable Deficit Fixed Priority arbitration*/
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reg |= IXGBE_RMCS_DFP;
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
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if (tsa[i] == ixgbe_dcb_tsa_strict)
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reg |= IXGBE_RT2CR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
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}
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reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
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reg |= IXGBE_RDRXCTL_RDMTS_1_2;
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reg |= IXGBE_RDRXCTL_MPBEN;
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reg |= IXGBE_RDRXCTL_MCEN;
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IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
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/* Make sure there is enough descriptors before arbitration */
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reg &= ~IXGBE_RXCTRL_DMBYPS;
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IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill, u16 *max, u8 *bwg_id,
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u8 *tsa)
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{
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u32 reg, max_credits;
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u8 i;
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reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
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/* Enable arbiter */
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reg &= ~IXGBE_DPMCS_ARBDIS;
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reg |= IXGBE_DPMCS_TSOEF;
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/* Configure Max TSO packet size 34KB including payload and headers */
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reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
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IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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max_credits = max[i];
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reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
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reg |= refill[i];
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reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
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if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
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reg |= IXGBE_TDTQ2TCCR_GSP;
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if (tsa[i] == ixgbe_dcb_tsa_strict)
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reg |= IXGBE_TDTQ2TCCR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
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}
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Tx Data Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
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u16 *refill, u16 *max, u8 *bwg_id,
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u8 *tsa)
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{
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u32 reg;
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u8 i;
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reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
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/* Enable Data Plane Arbiter */
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reg &= ~IXGBE_PDPMCS_ARBDIS;
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/* Enable DFP and Transmit Recycle Mode */
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reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
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IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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reg = refill[i];
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reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
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reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
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if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
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reg |= IXGBE_TDPT2TCCR_GSP;
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if (tsa[i] == ixgbe_dcb_tsa_strict)
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reg |= IXGBE_TDPT2TCCR_LSP;
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IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
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}
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/* Enable Tx packet buffer division */
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reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
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reg |= IXGBE_DTXCTL_ENDBUBD;
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IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_pfc_82598 - Config priority flow control
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Priority Flow Control for each traffic class.
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*/
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s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
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{
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u32 fcrtl, reg;
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u8 i;
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/* Enable Transmit Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
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reg &= ~IXGBE_RMCS_TFCE_802_3X;
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reg |= IXGBE_RMCS_TFCE_PRIORITY;
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
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/* Enable Receive Priority Flow Control */
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reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
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reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
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if (pfc_en)
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reg |= IXGBE_FCTRL_RPFCE;
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IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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if (!(pfc_en & (1 << i))) {
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
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continue;
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}
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
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}
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/* Configure pause time */
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reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
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for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
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* @hw: pointer to hardware structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
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{
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u32 reg = 0;
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u8 i = 0;
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u8 j = 0;
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/* Receive Queues stats setting - 8 queues per statistics reg */
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for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
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reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
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reg |= ((0x1010101) * j);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
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reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
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reg |= ((0x1010101) * j);
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IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
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}
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/* Transmit Queues stats setting - 4 queues per statistics reg*/
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for (i = 0; i < 8; i++) {
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reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
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reg |= ((0x1010101) * i);
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IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
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}
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return IXGBE_SUCCESS;
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}
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/**
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* ixgbe_dcb_hw_config_82598 - Config and enable DCB
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure dcb settings and enable dcb mode.
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*/
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s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
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u16 *refill, u16 *max, u8 *bwg_id,
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u8 *tsa)
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{
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ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
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ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
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tsa);
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ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
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tsa);
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ixgbe_dcb_config_tc_stats_82598(hw);
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return IXGBE_SUCCESS;
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}
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