440565dad1
"blksz is only used in one of the two blocks, so assign it inside that block rather than outside. MFC after: 2 weeks
1534 lines
37 KiB
C
1534 lines
37 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
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* Copyright (c) 2013 Alexander Fedorov
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcbrvar.h>
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#include <arm/allwinner/aw_mmc.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#include "opt_mmccam.h"
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#ifdef MMCCAM
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/cam_debug.h>
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#include <cam/cam_sim.h>
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#include <cam/cam_xpt_sim.h>
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#endif
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#define AW_MMC_MEMRES 0
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#define AW_MMC_IRQRES 1
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#define AW_MMC_RESSZ 2
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#define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc))
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#define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS)
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#define AW_MMC_DMA_FTRGLEVEL 0x20070008
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#define AW_MMC_RESET_RETRY 1000
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#define CARD_ID_FREQUENCY 400000
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struct aw_mmc_conf {
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uint32_t dma_xferlen;
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bool mask_data0;
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bool can_calibrate;
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bool new_timing;
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};
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static const struct aw_mmc_conf a10_mmc_conf = {
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.dma_xferlen = 0x2000,
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};
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static const struct aw_mmc_conf a13_mmc_conf = {
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.dma_xferlen = 0x10000,
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};
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static const struct aw_mmc_conf a64_mmc_conf = {
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.dma_xferlen = 0x10000,
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.mask_data0 = true,
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.can_calibrate = true,
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.new_timing = true,
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};
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static const struct aw_mmc_conf a64_emmc_conf = {
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.dma_xferlen = 0x2000,
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.can_calibrate = true,
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};
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static struct ofw_compat_data compat_data[] = {
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{"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf},
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{"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf},
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{"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf},
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{"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf},
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{"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf},
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{NULL, 0}
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};
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struct aw_mmc_softc {
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device_t aw_dev;
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clk_t aw_clk_ahb;
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clk_t aw_clk_mmc;
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hwreset_t aw_rst_ahb;
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int aw_bus_busy;
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int aw_resid;
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int aw_timeout;
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struct callout aw_timeoutc;
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struct mmc_host aw_host;
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#ifdef MMCCAM
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union ccb * ccb;
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struct cam_devq * devq;
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struct cam_sim * sim;
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struct mtx sim_mtx;
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#else
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struct mmc_request * aw_req;
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#endif
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struct mtx aw_mtx;
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struct resource * aw_res[AW_MMC_RESSZ];
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struct aw_mmc_conf * aw_mmc_conf;
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uint32_t aw_intr;
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uint32_t aw_intr_wait;
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void * aw_intrhand;
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regulator_t aw_reg_vmmc;
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regulator_t aw_reg_vqmmc;
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unsigned int aw_clock;
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/* Fields required for DMA access. */
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bus_addr_t aw_dma_desc_phys;
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bus_dmamap_t aw_dma_map;
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bus_dma_tag_t aw_dma_tag;
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void * aw_dma_desc;
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bus_dmamap_t aw_dma_buf_map;
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bus_dma_tag_t aw_dma_buf_tag;
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int aw_dma_map_err;
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};
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static struct resource_spec aw_mmc_res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
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{ -1, 0, 0 }
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};
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static int aw_mmc_probe(device_t);
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static int aw_mmc_attach(device_t);
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static int aw_mmc_detach(device_t);
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static int aw_mmc_setup_dma(struct aw_mmc_softc *);
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static int aw_mmc_reset(struct aw_mmc_softc *);
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static int aw_mmc_init(struct aw_mmc_softc *);
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static void aw_mmc_intr(void *);
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static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
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static void aw_mmc_print_error(uint32_t);
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static int aw_mmc_update_ios(device_t, device_t);
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static int aw_mmc_request(device_t, device_t, struct mmc_request *);
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static int aw_mmc_get_ro(device_t, device_t);
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static int aw_mmc_acquire_host(device_t, device_t);
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static int aw_mmc_release_host(device_t, device_t);
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#ifdef MMCCAM
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static void aw_mmc_cam_action(struct cam_sim *, union ccb *);
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static void aw_mmc_cam_poll(struct cam_sim *);
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static int aw_mmc_cam_settran_settings(struct aw_mmc_softc *, union ccb *);
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static int aw_mmc_cam_request(struct aw_mmc_softc *, union ccb *);
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static void aw_mmc_cam_handle_mmcio(struct cam_sim *, union ccb *);
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#endif
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#define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx)
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#define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx)
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#define AW_MMC_READ_4(_sc, _reg) \
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bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)
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#define AW_MMC_WRITE_4(_sc, _reg, _value) \
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bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)
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#ifdef MMCCAM
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static void
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aw_mmc_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb)
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{
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struct aw_mmc_softc *sc;
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sc = cam_sim_softc(sim);
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aw_mmc_cam_request(sc, ccb);
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}
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static void
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aw_mmc_cam_action(struct cam_sim *sim, union ccb *ccb)
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{
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struct aw_mmc_softc *sc;
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sc = cam_sim_softc(sim);
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if (sc == NULL) {
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ccb->ccb_h.status = CAM_SEL_TIMEOUT;
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xpt_done(ccb);
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return;
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}
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mtx_assert(&sc->sim_mtx, MA_OWNED);
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switch (ccb->ccb_h.func_code) {
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case XPT_PATH_INQ:
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{
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struct ccb_pathinq *cpi;
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cpi = &ccb->cpi;
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cpi->version_num = 1;
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cpi->hba_inquiry = 0;
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cpi->target_sprt = 0;
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cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN;
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cpi->hba_eng_cnt = 0;
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cpi->max_target = 0;
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cpi->max_lun = 0;
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cpi->initiator_id = 1;
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cpi->maxio = (sc->aw_mmc_conf->dma_xferlen *
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AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
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strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
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strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN);
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strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
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cpi->unit_number = cam_sim_unit(sim);
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cpi->bus_id = cam_sim_bus(sim);
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cpi->protocol = PROTO_MMCSD;
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cpi->protocol_version = SCSI_REV_0;
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cpi->transport = XPORT_MMCSD;
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cpi->transport_version = 1;
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cpi->ccb_h.status = CAM_REQ_CMP;
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break;
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}
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case XPT_GET_TRAN_SETTINGS:
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{
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struct ccb_trans_settings *cts = &ccb->cts;
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if (bootverbose)
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device_printf(sc->aw_dev, "Got XPT_GET_TRAN_SETTINGS\n");
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cts->protocol = PROTO_MMCSD;
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cts->protocol_version = 1;
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cts->transport = XPORT_MMCSD;
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cts->transport_version = 1;
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cts->xport_specific.valid = 0;
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cts->proto_specific.mmc.host_ocr = sc->aw_host.host_ocr;
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cts->proto_specific.mmc.host_f_min = sc->aw_host.f_min;
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cts->proto_specific.mmc.host_f_max = sc->aw_host.f_max;
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cts->proto_specific.mmc.host_caps = sc->aw_host.caps;
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cts->proto_specific.mmc.host_max_data = (sc->aw_mmc_conf->dma_xferlen *
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AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
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memcpy(&cts->proto_specific.mmc.ios, &sc->aw_host.ios, sizeof(struct mmc_ios));
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ccb->ccb_h.status = CAM_REQ_CMP;
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break;
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}
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case XPT_SET_TRAN_SETTINGS:
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{
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if (bootverbose)
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device_printf(sc->aw_dev, "Got XPT_SET_TRAN_SETTINGS\n");
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aw_mmc_cam_settran_settings(sc, ccb);
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ccb->ccb_h.status = CAM_REQ_CMP;
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break;
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}
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case XPT_RESET_BUS:
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if (bootverbose)
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device_printf(sc->aw_dev, "Got XPT_RESET_BUS, ACK it...\n");
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ccb->ccb_h.status = CAM_REQ_CMP;
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break;
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case XPT_MMC_IO:
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/*
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* Here is the HW-dependent part of
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* sending the command to the underlying h/w
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* At some point in the future an interrupt comes.
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* Then the request will be marked as completed.
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*/
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ccb->ccb_h.status = CAM_REQ_INPROG;
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aw_mmc_cam_handle_mmcio(sim, ccb);
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return;
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/* NOTREACHED */
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break;
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default:
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ccb->ccb_h.status = CAM_REQ_INVALID;
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break;
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}
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xpt_done(ccb);
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return;
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}
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static void
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aw_mmc_cam_poll(struct cam_sim *sim)
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{
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return;
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}
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static int
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aw_mmc_cam_settran_settings(struct aw_mmc_softc *sc, union ccb *ccb)
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{
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struct mmc_ios *ios;
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struct mmc_ios *new_ios;
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struct ccb_trans_settings_mmc *cts;
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ios = &sc->aw_host.ios;
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cts = &ccb->cts.proto_specific.mmc;
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new_ios = &cts->ios;
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/* Update only requested fields */
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if (cts->ios_valid & MMC_CLK) {
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ios->clock = new_ios->clock;
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device_printf(sc->aw_dev, "Clock => %d\n", ios->clock);
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}
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if (cts->ios_valid & MMC_VDD) {
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ios->vdd = new_ios->vdd;
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device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd);
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}
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if (cts->ios_valid & MMC_CS) {
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ios->chip_select = new_ios->chip_select;
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device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select);
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}
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if (cts->ios_valid & MMC_BW) {
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ios->bus_width = new_ios->bus_width;
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device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width);
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}
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if (cts->ios_valid & MMC_PM) {
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ios->power_mode = new_ios->power_mode;
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device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode);
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}
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if (cts->ios_valid & MMC_BT) {
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ios->timing = new_ios->timing;
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device_printf(sc->aw_dev, "Timing => %d\n", ios->timing);
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}
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if (cts->ios_valid & MMC_BM) {
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ios->bus_mode = new_ios->bus_mode;
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device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode);
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}
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return (aw_mmc_update_ios(sc->aw_dev, NULL));
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}
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static int
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aw_mmc_cam_request(struct aw_mmc_softc *sc, union ccb *ccb)
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{
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struct ccb_mmcio *mmcio;
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mmcio = &ccb->mmcio;
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AW_MMC_LOCK(sc);
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|
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#ifdef DEBUG
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if (__predict_false(bootverbose)) {
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device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
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mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
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mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
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mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
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}
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#endif
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if (mmcio->cmd.data != NULL) {
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if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
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panic("data->len = %d, data->flags = %d -- something is b0rked",
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(int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
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}
|
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if (sc->ccb != NULL) {
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device_printf(sc->aw_dev, "Controller still has an active command\n");
|
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return (EBUSY);
|
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}
|
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sc->ccb = ccb;
|
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/* aw_mmc_request locks again */
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AW_MMC_UNLOCK(sc);
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aw_mmc_request(sc->aw_dev, NULL, NULL);
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|
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return (0);
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}
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#endif /* MMCCAM */
|
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|
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static int
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aw_mmc_probe(device_t dev)
|
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{
|
|
|
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if (!ofw_bus_status_okay(dev))
|
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return (ENXIO);
|
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
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return (ENXIO);
|
|
|
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device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
|
|
|
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return (BUS_PROBE_DEFAULT);
|
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}
|
|
|
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static int
|
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aw_mmc_attach(device_t dev)
|
|
{
|
|
device_t child;
|
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struct aw_mmc_softc *sc;
|
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struct sysctl_ctx_list *ctx;
|
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struct sysctl_oid_list *tree;
|
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uint32_t bus_width, max_freq;
|
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phandle_t node;
|
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int error;
|
|
|
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node = ofw_bus_get_node(dev);
|
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sc = device_get_softc(dev);
|
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sc->aw_dev = dev;
|
|
|
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sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
|
|
|
|
#ifndef MMCCAM
|
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sc->aw_req = NULL;
|
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#endif
|
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if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
|
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device_printf(dev, "cannot allocate device resources\n");
|
|
return (ENXIO);
|
|
}
|
|
if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES],
|
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INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_mmc_intr, sc,
|
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&sc->aw_intrhand)) {
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bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
|
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device_printf(dev, "cannot setup interrupt handler\n");
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return (ENXIO);
|
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}
|
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mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc",
|
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MTX_DEF);
|
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callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0);
|
|
|
|
/* De-assert reset */
|
|
if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) {
|
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error = hwreset_deassert(sc->aw_rst_ahb);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot de-assert reset\n");
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
/* Activate the module clock. */
|
|
error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot get ahb clock\n");
|
|
goto fail;
|
|
}
|
|
error = clk_enable(sc->aw_clk_ahb);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot enable ahb clock\n");
|
|
goto fail;
|
|
}
|
|
error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot get mmc clock\n");
|
|
goto fail;
|
|
}
|
|
error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY,
|
|
CLK_SET_ROUND_DOWN);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot init mmc clock\n");
|
|
goto fail;
|
|
}
|
|
error = clk_enable(sc->aw_clk_mmc);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot enable mmc clock\n");
|
|
goto fail;
|
|
}
|
|
|
|
sc->aw_timeout = 10;
|
|
ctx = device_get_sysctl_ctx(dev);
|
|
tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
|
|
SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
|
|
&sc->aw_timeout, 0, "Request timeout in seconds");
|
|
|
|
/* Soft Reset controller. */
|
|
if (aw_mmc_reset(sc) != 0) {
|
|
device_printf(dev, "cannot reset the controller\n");
|
|
goto fail;
|
|
}
|
|
|
|
if (aw_mmc_setup_dma(sc) != 0) {
|
|
device_printf(sc->aw_dev, "Couldn't setup DMA!\n");
|
|
goto fail;
|
|
}
|
|
|
|
if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0)
|
|
bus_width = 4;
|
|
|
|
if (regulator_get_by_ofw_property(dev, 0, "vmmc-supply",
|
|
&sc->aw_reg_vmmc) == 0) {
|
|
if (bootverbose)
|
|
device_printf(dev, "vmmc-supply regulator found\n");
|
|
}
|
|
if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply",
|
|
&sc->aw_reg_vqmmc) == 0 && bootverbose) {
|
|
if (bootverbose)
|
|
device_printf(dev, "vqmmc-supply regulator found\n");
|
|
}
|
|
|
|
sc->aw_host.f_min = 400000;
|
|
|
|
if (OF_getencprop(node, "max-frequency", &max_freq,
|
|
sizeof(uint32_t)) <= 0)
|
|
max_freq = 52000000;
|
|
sc->aw_host.f_max = max_freq;
|
|
|
|
sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
|
|
sc->aw_host.caps = MMC_CAP_HSPEED | MMC_CAP_UHS_SDR12 |
|
|
MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
|
|
MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52;
|
|
|
|
sc->aw_host.caps |= MMC_CAP_SIGNALING_330 | MMC_CAP_SIGNALING_180;
|
|
|
|
if (bus_width >= 4)
|
|
sc->aw_host.caps |= MMC_CAP_4_BIT_DATA;
|
|
if (bus_width >= 8)
|
|
sc->aw_host.caps |= MMC_CAP_8_BIT_DATA;
|
|
|
|
#ifdef MMCCAM
|
|
child = NULL; /* Not used by MMCCAM, need to silence compiler warnings */
|
|
sc->ccb = NULL;
|
|
if ((sc->devq = cam_simq_alloc(1)) == NULL) {
|
|
goto fail;
|
|
}
|
|
|
|
mtx_init(&sc->sim_mtx, "awmmcsim", NULL, MTX_DEF);
|
|
sc->sim = cam_sim_alloc(aw_mmc_cam_action, aw_mmc_cam_poll,
|
|
"aw_mmc_sim", sc, device_get_unit(dev),
|
|
&sc->sim_mtx, 1, 1, sc->devq);
|
|
|
|
if (sc->sim == NULL) {
|
|
cam_simq_free(sc->devq);
|
|
device_printf(dev, "cannot allocate CAM SIM\n");
|
|
goto fail;
|
|
}
|
|
|
|
mtx_lock(&sc->sim_mtx);
|
|
if (xpt_bus_register(sc->sim, sc->aw_dev, 0) != 0) {
|
|
device_printf(dev, "cannot register SCSI pass-through bus\n");
|
|
cam_sim_free(sc->sim, FALSE);
|
|
cam_simq_free(sc->devq);
|
|
mtx_unlock(&sc->sim_mtx);
|
|
goto fail;
|
|
}
|
|
|
|
mtx_unlock(&sc->sim_mtx);
|
|
#else /* !MMCCAM */
|
|
child = device_add_child(dev, "mmc", -1);
|
|
if (child == NULL) {
|
|
device_printf(dev, "attaching MMC bus failed!\n");
|
|
goto fail;
|
|
}
|
|
if (device_probe_and_attach(child) != 0) {
|
|
device_printf(dev, "attaching MMC child failed!\n");
|
|
device_delete_child(dev, child);
|
|
goto fail;
|
|
}
|
|
#endif /* MMCCAM */
|
|
return (0);
|
|
|
|
fail:
|
|
callout_drain(&sc->aw_timeoutc);
|
|
mtx_destroy(&sc->aw_mtx);
|
|
bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
|
|
bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
|
|
|
|
#ifdef MMCCAM
|
|
if (sc->sim != NULL) {
|
|
mtx_lock(&sc->sim_mtx);
|
|
xpt_bus_deregister(cam_sim_path(sc->sim));
|
|
cam_sim_free(sc->sim, FALSE);
|
|
mtx_unlock(&sc->sim_mtx);
|
|
}
|
|
|
|
if (sc->devq != NULL)
|
|
cam_simq_free(sc->devq);
|
|
#endif
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_detach(device_t dev)
|
|
{
|
|
|
|
return (EBUSY);
|
|
}
|
|
|
|
static void
|
|
aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
|
|
sc = (struct aw_mmc_softc *)arg;
|
|
if (err) {
|
|
sc->aw_dma_map_err = err;
|
|
return;
|
|
}
|
|
sc->aw_dma_desc_phys = segs[0].ds_addr;
|
|
}
|
|
|
|
static int
|
|
aw_mmc_setup_dma(struct aw_mmc_softc *sc)
|
|
{
|
|
int error;
|
|
|
|
/* Allocate the DMA descriptor memory. */
|
|
error = bus_dma_tag_create(
|
|
bus_get_dma_tag(sc->aw_dev), /* parent */
|
|
AW_MMC_DMA_ALIGN, 0, /* align, boundary */
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg*/
|
|
AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */
|
|
AW_MMC_DMA_DESC_SIZE, /* maxsegsize */
|
|
0, /* flags */
|
|
NULL, NULL, /* lock, lockarg*/
|
|
&sc->aw_dma_tag);
|
|
if (error)
|
|
return (error);
|
|
|
|
error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc,
|
|
BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
|
|
&sc->aw_dma_map);
|
|
if (error)
|
|
return (error);
|
|
|
|
error = bus_dmamap_load(sc->aw_dma_tag,
|
|
sc->aw_dma_map,
|
|
sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE,
|
|
aw_dma_desc_cb, sc, 0);
|
|
if (error)
|
|
return (error);
|
|
if (sc->aw_dma_map_err)
|
|
return (sc->aw_dma_map_err);
|
|
|
|
/* Create the DMA map for data transfers. */
|
|
error = bus_dma_tag_create(
|
|
bus_get_dma_tag(sc->aw_dev), /* parent */
|
|
AW_MMC_DMA_ALIGN, 0, /* align, boundary */
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg*/
|
|
sc->aw_mmc_conf->dma_xferlen *
|
|
AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */
|
|
sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */
|
|
BUS_DMA_ALLOCNOW, /* flags */
|
|
NULL, NULL, /* lock, lockarg*/
|
|
&sc->aw_dma_buf_tag);
|
|
if (error)
|
|
return (error);
|
|
error = bus_dmamap_create(sc->aw_dma_buf_tag, 0,
|
|
&sc->aw_dma_buf_map);
|
|
if (error)
|
|
return (error);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
|
|
{
|
|
int i;
|
|
struct aw_mmc_dma_desc *dma_desc;
|
|
struct aw_mmc_softc *sc;
|
|
|
|
sc = (struct aw_mmc_softc *)arg;
|
|
sc->aw_dma_map_err = err;
|
|
|
|
if (err)
|
|
return;
|
|
|
|
dma_desc = sc->aw_dma_desc;
|
|
for (i = 0; i < nsegs; i++) {
|
|
if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen)
|
|
dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */
|
|
else
|
|
dma_desc[i].buf_size = segs[i].ds_len;
|
|
dma_desc[i].buf_addr = segs[i].ds_addr;
|
|
dma_desc[i].config = AW_MMC_DMA_CONFIG_CH |
|
|
AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC;
|
|
|
|
dma_desc[i].next = sc->aw_dma_desc_phys +
|
|
((i + 1) * sizeof(struct aw_mmc_dma_desc));
|
|
}
|
|
|
|
dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD;
|
|
dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD |
|
|
AW_MMC_DMA_CONFIG_ER;
|
|
dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC;
|
|
dma_desc[nsegs - 1].next = 0;
|
|
}
|
|
|
|
static int
|
|
aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
|
|
{
|
|
bus_dmasync_op_t sync_op;
|
|
int error;
|
|
struct mmc_command *cmd;
|
|
uint32_t val;
|
|
|
|
#ifdef MMCCAM
|
|
cmd = &sc->ccb->mmcio.cmd;
|
|
#else
|
|
cmd = sc->aw_req->cmd;
|
|
#endif
|
|
if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS))
|
|
return (EFBIG);
|
|
error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
|
|
cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
|
|
if (error)
|
|
return (error);
|
|
if (sc->aw_dma_map_err)
|
|
return (sc->aw_dma_map_err);
|
|
|
|
if (cmd->data->flags & MMC_DATA_WRITE)
|
|
sync_op = BUS_DMASYNC_PREWRITE;
|
|
else
|
|
sync_op = BUS_DMASYNC_PREREAD;
|
|
bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op);
|
|
bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE);
|
|
|
|
/* Enable DMA */
|
|
val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
|
|
val &= ~AW_MMC_GCTL_FIFO_AC_MOD;
|
|
val |= AW_MMC_GCTL_DMA_ENB;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
|
|
|
|
/* Reset DMA */
|
|
val |= AW_MMC_GCTL_DMA_RST;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
|
|
|
|
AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_DMAC,
|
|
AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST);
|
|
|
|
/* Enable RX or TX DMA interrupt */
|
|
val = AW_MMC_READ_4(sc, AW_MMC_IDIE);
|
|
if (cmd->data->flags & MMC_DATA_WRITE)
|
|
val |= AW_MMC_IDST_TX_INT;
|
|
else
|
|
val |= AW_MMC_IDST_RX_INT;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val);
|
|
|
|
/* Set DMA descritptor list address */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys);
|
|
|
|
/* FIFO trigger level */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_reset(struct aw_mmc_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
int timeout;
|
|
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
|
|
reg |= AW_MMC_GCTL_RESET;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
|
|
timeout = AW_MMC_RESET_RETRY;
|
|
while (--timeout > 0) {
|
|
if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0)
|
|
break;
|
|
DELAY(100);
|
|
}
|
|
if (timeout == 0)
|
|
return (ETIMEDOUT);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_init(struct aw_mmc_softc *sc)
|
|
{
|
|
uint32_t reg;
|
|
int ret;
|
|
|
|
ret = aw_mmc_reset(sc);
|
|
if (ret != 0)
|
|
return (ret);
|
|
|
|
/* Set the timeout. */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
|
|
AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
|
|
AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
|
|
|
|
/* Unmask interrupts. */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0);
|
|
|
|
/* Clear pending interrupts. */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
|
|
|
|
/* Debug register, undocumented */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb);
|
|
|
|
/* Function select register */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000);
|
|
|
|
AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
|
|
|
|
/* Enable interrupts and disable AHB access. */
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
|
|
reg |= AW_MMC_GCTL_INT_ENB;
|
|
reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;
|
|
reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
aw_mmc_req_done(struct aw_mmc_softc *sc)
|
|
{
|
|
struct mmc_command *cmd;
|
|
#ifdef MMCCAM
|
|
union ccb *ccb;
|
|
#else
|
|
struct mmc_request *req;
|
|
#endif
|
|
uint32_t val, mask;
|
|
int retry;
|
|
|
|
#ifdef MMCCAM
|
|
ccb = sc->ccb;
|
|
cmd = &ccb->mmcio.cmd;
|
|
#else
|
|
cmd = sc->aw_req->cmd;
|
|
#endif
|
|
#ifdef DEBUG
|
|
if (bootverbose) {
|
|
device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error);
|
|
}
|
|
#endif
|
|
if (cmd->error != MMC_ERR_NONE) {
|
|
/* Reset the FIFO and DMA engines. */
|
|
mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST;
|
|
val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
|
|
|
|
retry = AW_MMC_RESET_RETRY;
|
|
while (--retry > 0) {
|
|
if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) &
|
|
AW_MMC_GCTL_RESET) == 0)
|
|
break;
|
|
DELAY(100);
|
|
}
|
|
if (retry == 0)
|
|
device_printf(sc->aw_dev,
|
|
"timeout resetting DMA/FIFO\n");
|
|
aw_mmc_update_clock(sc, 1);
|
|
}
|
|
|
|
callout_stop(&sc->aw_timeoutc);
|
|
sc->aw_intr = 0;
|
|
sc->aw_resid = 0;
|
|
sc->aw_dma_map_err = 0;
|
|
sc->aw_intr_wait = 0;
|
|
#ifdef MMCCAM
|
|
sc->ccb = NULL;
|
|
ccb->ccb_h.status =
|
|
(ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
|
|
xpt_done(ccb);
|
|
#else
|
|
req = sc->aw_req;
|
|
sc->aw_req = NULL;
|
|
req->done(req);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
aw_mmc_req_ok(struct aw_mmc_softc *sc)
|
|
{
|
|
int timeout;
|
|
struct mmc_command *cmd;
|
|
uint32_t status;
|
|
|
|
timeout = 1000;
|
|
while (--timeout > 0) {
|
|
status = AW_MMC_READ_4(sc, AW_MMC_STAR);
|
|
if ((status & AW_MMC_STAR_CARD_BUSY) == 0)
|
|
break;
|
|
DELAY(1000);
|
|
}
|
|
#ifdef MMCCAM
|
|
cmd = &sc->ccb->mmcio.cmd;
|
|
#else
|
|
cmd = sc->aw_req->cmd;
|
|
#endif
|
|
if (timeout == 0) {
|
|
cmd->error = MMC_ERR_FAILED;
|
|
aw_mmc_req_done(sc);
|
|
return;
|
|
}
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
if (cmd->flags & MMC_RSP_136) {
|
|
cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3);
|
|
cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2);
|
|
cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1);
|
|
cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
|
|
} else
|
|
cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
|
|
}
|
|
/* All data has been transferred ? */
|
|
if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len)
|
|
cmd->error = MMC_ERR_FAILED;
|
|
aw_mmc_req_done(sc);
|
|
}
|
|
|
|
|
|
static inline void
|
|
set_mmc_error(struct aw_mmc_softc *sc, int error_code)
|
|
{
|
|
#ifdef MMCCAM
|
|
sc->ccb->mmcio.cmd.error = error_code;
|
|
#else
|
|
sc->aw_req->cmd->error = error_code;
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
aw_mmc_timeout(void *arg)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
|
|
sc = (struct aw_mmc_softc *)arg;
|
|
#ifdef MMCCAM
|
|
if (sc->ccb != NULL) {
|
|
#else
|
|
if (sc->aw_req != NULL) {
|
|
#endif
|
|
device_printf(sc->aw_dev, "controller timeout\n");
|
|
set_mmc_error(sc, MMC_ERR_TIMEOUT);
|
|
aw_mmc_req_done(sc);
|
|
} else
|
|
device_printf(sc->aw_dev,
|
|
"Spurious timeout - no active request\n");
|
|
}
|
|
|
|
static void
|
|
aw_mmc_print_error(uint32_t err)
|
|
{
|
|
if(err & AW_MMC_INT_RESP_ERR)
|
|
printf("AW_MMC_INT_RESP_ERR ");
|
|
if (err & AW_MMC_INT_RESP_CRC_ERR)
|
|
printf("AW_MMC_INT_RESP_CRC_ERR ");
|
|
if (err & AW_MMC_INT_DATA_CRC_ERR)
|
|
printf("AW_MMC_INT_DATA_CRC_ERR ");
|
|
if (err & AW_MMC_INT_RESP_TIMEOUT)
|
|
printf("AW_MMC_INT_RESP_TIMEOUT ");
|
|
if (err & AW_MMC_INT_FIFO_RUN_ERR)
|
|
printf("AW_MMC_INT_FIFO_RUN_ERR ");
|
|
if (err & AW_MMC_INT_CMD_BUSY)
|
|
printf("AW_MMC_INT_CMD_BUSY ");
|
|
if (err & AW_MMC_INT_DATA_START_ERR)
|
|
printf("AW_MMC_INT_DATA_START_ERR ");
|
|
if (err & AW_MMC_INT_DATA_END_BIT_ERR)
|
|
printf("AW_MMC_INT_DATA_END_BIT_ERR");
|
|
printf("\n");
|
|
}
|
|
|
|
static void
|
|
aw_mmc_intr(void *arg)
|
|
{
|
|
bus_dmasync_op_t sync_op;
|
|
struct aw_mmc_softc *sc;
|
|
struct mmc_data *data;
|
|
uint32_t idst, imask, rint;
|
|
|
|
sc = (struct aw_mmc_softc *)arg;
|
|
AW_MMC_LOCK(sc);
|
|
rint = AW_MMC_READ_4(sc, AW_MMC_RISR);
|
|
idst = AW_MMC_READ_4(sc, AW_MMC_IDST);
|
|
imask = AW_MMC_READ_4(sc, AW_MMC_IMKR);
|
|
if (idst == 0 && imask == 0 && rint == 0) {
|
|
AW_MMC_UNLOCK(sc);
|
|
return;
|
|
}
|
|
#ifdef DEBUG
|
|
device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n",
|
|
idst, imask, rint);
|
|
#endif
|
|
#ifdef MMCCAM
|
|
if (sc->ccb == NULL) {
|
|
#else
|
|
if (sc->aw_req == NULL) {
|
|
#endif
|
|
device_printf(sc->aw_dev,
|
|
"Spurious interrupt - no active request, rint: 0x%08X\n",
|
|
rint);
|
|
aw_mmc_print_error(rint);
|
|
goto end;
|
|
}
|
|
if (rint & AW_MMC_INT_ERR_BIT) {
|
|
if (bootverbose)
|
|
device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
|
|
aw_mmc_print_error(rint);
|
|
if (rint & AW_MMC_INT_RESP_TIMEOUT)
|
|
set_mmc_error(sc, MMC_ERR_TIMEOUT);
|
|
else
|
|
set_mmc_error(sc, MMC_ERR_FAILED);
|
|
aw_mmc_req_done(sc);
|
|
goto end;
|
|
}
|
|
if (idst & AW_MMC_IDST_ERROR) {
|
|
device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst);
|
|
set_mmc_error(sc, MMC_ERR_FAILED);
|
|
aw_mmc_req_done(sc);
|
|
goto end;
|
|
}
|
|
|
|
sc->aw_intr |= rint;
|
|
#ifdef MMCCAM
|
|
data = sc->ccb->mmcio.cmd.data;
|
|
#else
|
|
data = sc->aw_req->cmd->data;
|
|
#endif
|
|
if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) {
|
|
if (data->flags & MMC_DATA_WRITE)
|
|
sync_op = BUS_DMASYNC_POSTWRITE;
|
|
else
|
|
sync_op = BUS_DMASYNC_POSTREAD;
|
|
bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
|
|
sync_op);
|
|
bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map,
|
|
BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
|
|
sc->aw_resid = data->len >> 2;
|
|
}
|
|
if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait)
|
|
aw_mmc_req_ok(sc);
|
|
|
|
end:
|
|
AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint);
|
|
AW_MMC_UNLOCK(sc);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
|
|
{
|
|
int blksz;
|
|
struct aw_mmc_softc *sc;
|
|
struct mmc_command *cmd;
|
|
uint32_t cmdreg, imask;
|
|
int err;
|
|
|
|
sc = device_get_softc(bus);
|
|
|
|
AW_MMC_LOCK(sc);
|
|
#ifdef MMCCAM
|
|
KASSERT(req == NULL, ("req should be NULL in MMCCAM case!"));
|
|
/*
|
|
* For MMCCAM, sc->ccb has been NULL-checked and populated
|
|
* by aw_mmc_cam_request() already.
|
|
*/
|
|
cmd = &sc->ccb->mmcio.cmd;
|
|
#else
|
|
if (sc->aw_req) {
|
|
AW_MMC_UNLOCK(sc);
|
|
return (EBUSY);
|
|
}
|
|
sc->aw_req = req;
|
|
cmd = req->cmd;
|
|
|
|
#ifdef DEBUG
|
|
if (bootverbose)
|
|
device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
|
|
cmd->opcode, cmd->arg, cmd->flags,
|
|
cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
|
|
cmd->data != NULL ? cmd->data->flags: 0);
|
|
#endif
|
|
#endif
|
|
cmdreg = AW_MMC_CMDR_LOAD;
|
|
imask = AW_MMC_INT_ERR_BIT;
|
|
sc->aw_intr_wait = 0;
|
|
sc->aw_intr = 0;
|
|
sc->aw_resid = 0;
|
|
cmd->error = MMC_ERR_NONE;
|
|
|
|
if (cmd->opcode == MMC_GO_IDLE_STATE)
|
|
cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
|
|
|
|
if (cmd->flags & MMC_RSP_PRESENT)
|
|
cmdreg |= AW_MMC_CMDR_RESP_RCV;
|
|
if (cmd->flags & MMC_RSP_136)
|
|
cmdreg |= AW_MMC_CMDR_LONG_RESP;
|
|
if (cmd->flags & MMC_RSP_CRC)
|
|
cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
|
|
|
|
if (cmd->data) {
|
|
cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
|
|
|
|
if (cmd->data->flags & MMC_DATA_MULTI) {
|
|
cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
|
|
imask |= AW_MMC_INT_AUTO_STOP_DONE;
|
|
sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
|
|
} else {
|
|
sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
|
|
imask |= AW_MMC_INT_DATA_OVER;
|
|
}
|
|
if (cmd->data->flags & MMC_DATA_WRITE)
|
|
cmdreg |= AW_MMC_CMDR_DIR_WRITE;
|
|
#ifdef MMCCAM
|
|
if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) {
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
|
|
} else
|
|
#endif
|
|
{
|
|
blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
|
|
}
|
|
} else {
|
|
imask |= AW_MMC_INT_CMD_DONE;
|
|
}
|
|
|
|
/* Enable the interrupts we are interested in */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask);
|
|
AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
|
|
|
|
/* Enable auto stop if needed */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_A12A,
|
|
cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff);
|
|
|
|
/* Write the command argument */
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
|
|
|
|
/*
|
|
* If we don't have data start the request
|
|
* if we do prepare the dma request and start the request
|
|
*/
|
|
if (cmd->data == NULL) {
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
|
|
} else {
|
|
err = aw_mmc_prepare_dma(sc);
|
|
if (err != 0)
|
|
device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
|
|
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
|
|
}
|
|
|
|
callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
|
|
aw_mmc_timeout, sc);
|
|
AW_MMC_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_read_ivar(device_t bus, device_t child, int which,
|
|
uintptr_t *result)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
|
|
sc = device_get_softc(bus);
|
|
switch (which) {
|
|
default:
|
|
return (EINVAL);
|
|
case MMCBR_IVAR_BUS_MODE:
|
|
*(int *)result = sc->aw_host.ios.bus_mode;
|
|
break;
|
|
case MMCBR_IVAR_BUS_WIDTH:
|
|
*(int *)result = sc->aw_host.ios.bus_width;
|
|
break;
|
|
case MMCBR_IVAR_CHIP_SELECT:
|
|
*(int *)result = sc->aw_host.ios.chip_select;
|
|
break;
|
|
case MMCBR_IVAR_CLOCK:
|
|
*(int *)result = sc->aw_host.ios.clock;
|
|
break;
|
|
case MMCBR_IVAR_F_MIN:
|
|
*(int *)result = sc->aw_host.f_min;
|
|
break;
|
|
case MMCBR_IVAR_F_MAX:
|
|
*(int *)result = sc->aw_host.f_max;
|
|
break;
|
|
case MMCBR_IVAR_HOST_OCR:
|
|
*(int *)result = sc->aw_host.host_ocr;
|
|
break;
|
|
case MMCBR_IVAR_MODE:
|
|
*(int *)result = sc->aw_host.mode;
|
|
break;
|
|
case MMCBR_IVAR_OCR:
|
|
*(int *)result = sc->aw_host.ocr;
|
|
break;
|
|
case MMCBR_IVAR_POWER_MODE:
|
|
*(int *)result = sc->aw_host.ios.power_mode;
|
|
break;
|
|
case MMCBR_IVAR_VDD:
|
|
*(int *)result = sc->aw_host.ios.vdd;
|
|
break;
|
|
case MMCBR_IVAR_VCCQ:
|
|
*(int *)result = sc->aw_host.ios.vccq;
|
|
break;
|
|
case MMCBR_IVAR_CAPS:
|
|
*(int *)result = sc->aw_host.caps;
|
|
break;
|
|
case MMCBR_IVAR_TIMING:
|
|
*(int *)result = sc->aw_host.ios.timing;
|
|
break;
|
|
case MMCBR_IVAR_MAX_DATA:
|
|
*(int *)result = (sc->aw_mmc_conf->dma_xferlen *
|
|
AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
|
|
break;
|
|
case MMCBR_IVAR_RETUNE_REQ:
|
|
*(int *)result = retune_req_none;
|
|
break;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_write_ivar(device_t bus, device_t child, int which,
|
|
uintptr_t value)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
|
|
sc = device_get_softc(bus);
|
|
switch (which) {
|
|
default:
|
|
return (EINVAL);
|
|
case MMCBR_IVAR_BUS_MODE:
|
|
sc->aw_host.ios.bus_mode = value;
|
|
break;
|
|
case MMCBR_IVAR_BUS_WIDTH:
|
|
sc->aw_host.ios.bus_width = value;
|
|
break;
|
|
case MMCBR_IVAR_CHIP_SELECT:
|
|
sc->aw_host.ios.chip_select = value;
|
|
break;
|
|
case MMCBR_IVAR_CLOCK:
|
|
sc->aw_host.ios.clock = value;
|
|
break;
|
|
case MMCBR_IVAR_MODE:
|
|
sc->aw_host.mode = value;
|
|
break;
|
|
case MMCBR_IVAR_OCR:
|
|
sc->aw_host.ocr = value;
|
|
break;
|
|
case MMCBR_IVAR_POWER_MODE:
|
|
sc->aw_host.ios.power_mode = value;
|
|
break;
|
|
case MMCBR_IVAR_VDD:
|
|
sc->aw_host.ios.vdd = value;
|
|
break;
|
|
case MMCBR_IVAR_VCCQ:
|
|
sc->aw_host.ios.vccq = value;
|
|
break;
|
|
case MMCBR_IVAR_TIMING:
|
|
sc->aw_host.ios.timing = value;
|
|
break;
|
|
/* These are read-only */
|
|
case MMCBR_IVAR_CAPS:
|
|
case MMCBR_IVAR_HOST_OCR:
|
|
case MMCBR_IVAR_F_MIN:
|
|
case MMCBR_IVAR_F_MAX:
|
|
case MMCBR_IVAR_MAX_DATA:
|
|
return (EINVAL);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
|
|
{
|
|
uint32_t reg;
|
|
int retry;
|
|
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
|
|
reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |
|
|
AW_MMC_CKCR_MASK_DATA0);
|
|
|
|
if (clkon)
|
|
reg |= AW_MMC_CKCR_ENB;
|
|
if (sc->aw_mmc_conf->mask_data0)
|
|
reg |= AW_MMC_CKCR_MASK_DATA0;
|
|
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
|
|
|
|
reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
|
|
AW_MMC_CMDR_WAIT_PRE_OVER;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);
|
|
retry = 0xfffff;
|
|
|
|
while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);
|
|
DELAY(10);
|
|
}
|
|
AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
|
|
|
|
if (reg & AW_MMC_CMDR_LOAD) {
|
|
device_printf(sc->aw_dev, "timeout updating clock\n");
|
|
return (ETIMEDOUT);
|
|
}
|
|
|
|
if (sc->aw_mmc_conf->mask_data0) {
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
|
|
reg &= ~AW_MMC_CKCR_MASK_DATA0;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_switch_vccq(device_t bus, device_t child)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
int uvolt, err;
|
|
|
|
sc = device_get_softc(bus);
|
|
|
|
if (sc->aw_reg_vqmmc == NULL)
|
|
return EOPNOTSUPP;
|
|
|
|
switch (sc->aw_host.ios.vccq) {
|
|
case vccq_180:
|
|
uvolt = 1800000;
|
|
break;
|
|
case vccq_330:
|
|
uvolt = 3300000;
|
|
break;
|
|
default:
|
|
return EINVAL;
|
|
}
|
|
|
|
err = regulator_set_voltage(sc->aw_reg_vqmmc, uvolt, uvolt);
|
|
if (err != 0) {
|
|
device_printf(sc->aw_dev,
|
|
"Cannot set vqmmc to %d<->%d\n",
|
|
uvolt,
|
|
uvolt);
|
|
return (err);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_update_ios(device_t bus, device_t child)
|
|
{
|
|
int error;
|
|
struct aw_mmc_softc *sc;
|
|
struct mmc_ios *ios;
|
|
unsigned int clock;
|
|
uint32_t reg, div = 1;
|
|
|
|
sc = device_get_softc(bus);
|
|
|
|
ios = &sc->aw_host.ios;
|
|
|
|
/* Set the bus width. */
|
|
switch (ios->bus_width) {
|
|
case bus_width_1:
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1);
|
|
break;
|
|
case bus_width_4:
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4);
|
|
break;
|
|
case bus_width_8:
|
|
AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8);
|
|
break;
|
|
}
|
|
|
|
switch (ios->power_mode) {
|
|
case power_on:
|
|
break;
|
|
case power_off:
|
|
if (bootverbose)
|
|
device_printf(sc->aw_dev, "Powering down sd/mmc\n");
|
|
|
|
if (sc->aw_reg_vmmc)
|
|
regulator_disable(sc->aw_reg_vmmc);
|
|
if (sc->aw_reg_vqmmc)
|
|
regulator_disable(sc->aw_reg_vqmmc);
|
|
|
|
aw_mmc_reset(sc);
|
|
break;
|
|
case power_up:
|
|
if (bootverbose)
|
|
device_printf(sc->aw_dev, "Powering up sd/mmc\n");
|
|
|
|
if (sc->aw_reg_vmmc)
|
|
regulator_enable(sc->aw_reg_vmmc);
|
|
if (sc->aw_reg_vqmmc)
|
|
regulator_enable(sc->aw_reg_vqmmc);
|
|
aw_mmc_init(sc);
|
|
break;
|
|
};
|
|
|
|
/* Enable ddr mode if needed */
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
|
|
if (ios->timing == bus_timing_uhs_ddr50 ||
|
|
ios->timing == bus_timing_mmc_ddr52)
|
|
reg |= AW_MMC_GCTL_DDR_MOD_SEL;
|
|
else
|
|
reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
|
|
|
|
if (ios->clock && ios->clock != sc->aw_clock) {
|
|
sc->aw_clock = clock = ios->clock;
|
|
|
|
/* Disable clock */
|
|
error = aw_mmc_update_clock(sc, 0);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
if (ios->timing == bus_timing_mmc_ddr52 &&
|
|
(sc->aw_mmc_conf->new_timing ||
|
|
ios->bus_width == bus_width_8)) {
|
|
div = 2;
|
|
clock <<= 1;
|
|
}
|
|
|
|
/* Reset the divider. */
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
|
|
reg &= ~AW_MMC_CKCR_DIV;
|
|
reg |= div - 1;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
|
|
|
|
/* New timing mode if needed */
|
|
if (sc->aw_mmc_conf->new_timing) {
|
|
reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);
|
|
reg |= AW_MMC_NTSR_MODE_SELECT;
|
|
AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);
|
|
}
|
|
|
|
/* Set the MMC clock. */
|
|
error = clk_set_freq(sc->aw_clk_mmc, clock,
|
|
CLK_SET_ROUND_DOWN);
|
|
if (error != 0) {
|
|
device_printf(sc->aw_dev,
|
|
"failed to set frequency to %u Hz: %d\n",
|
|
clock, error);
|
|
return (error);
|
|
}
|
|
|
|
if (sc->aw_mmc_conf->can_calibrate)
|
|
AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN);
|
|
|
|
/* Enable clock. */
|
|
error = aw_mmc_update_clock(sc, 1);
|
|
if (error != 0)
|
|
return (error);
|
|
}
|
|
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_get_ro(device_t bus, device_t child)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_acquire_host(device_t bus, device_t child)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
int error;
|
|
|
|
sc = device_get_softc(bus);
|
|
AW_MMC_LOCK(sc);
|
|
while (sc->aw_bus_busy) {
|
|
error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0);
|
|
if (error != 0) {
|
|
AW_MMC_UNLOCK(sc);
|
|
return (error);
|
|
}
|
|
}
|
|
sc->aw_bus_busy++;
|
|
AW_MMC_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_mmc_release_host(device_t bus, device_t child)
|
|
{
|
|
struct aw_mmc_softc *sc;
|
|
|
|
sc = device_get_softc(bus);
|
|
AW_MMC_LOCK(sc);
|
|
sc->aw_bus_busy--;
|
|
wakeup(sc);
|
|
AW_MMC_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t aw_mmc_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, aw_mmc_probe),
|
|
DEVMETHOD(device_attach, aw_mmc_attach),
|
|
DEVMETHOD(device_detach, aw_mmc_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar),
|
|
|
|
/* MMC bridge interface */
|
|
DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios),
|
|
DEVMETHOD(mmcbr_request, aw_mmc_request),
|
|
DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro),
|
|
DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq),
|
|
DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host),
|
|
DEVMETHOD(mmcbr_release_host, aw_mmc_release_host),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t aw_mmc_devclass;
|
|
|
|
static driver_t aw_mmc_driver = {
|
|
"aw_mmc",
|
|
aw_mmc_methods,
|
|
sizeof(struct aw_mmc_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL,
|
|
NULL);
|
|
#ifndef MMCCAM
|
|
MMC_DECLARE_BRIDGE(aw_mmc);
|
|
#endif
|