3226c13778
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
/*-
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* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0var.h, rev 1
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*
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* $FreeBSD$
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*/
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#ifndef _MVVAR_H_
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#define _MVVAR_H_
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#include <sys/rman.h>
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struct obio_softc {
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bus_space_tag_t obio_bst; /* bus space tag */
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struct rman obio_mem;
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struct rman obio_irq;
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struct rman obio_gpio;
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};
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struct obio_device {
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const char *od_name;
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u_long od_base;
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u_long od_size;
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u_int od_irqs[7 + 1]; /* keep additional entry for -1 sentinel */
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u_int od_gpio[2 + 1]; /* as above for IRQ */
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u_int od_pwr_mask;
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struct resource_list od_resources;
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};
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struct decode_win {
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int target; /* Mbus unit ID */
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int attr; /* Attributes of the target interface */
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vm_paddr_t base; /* Physical base addr */
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uint32_t size;
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int remap;
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};
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extern bus_space_tag_t obio_tag;
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extern struct obio_device obio_devices[];
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extern const struct decode_win *cpu_wins;
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extern const struct decode_win *idma_wins;
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extern int cpu_wins_no;
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extern int idma_wins_no;
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/* Function prototypes */
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int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
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void (*hand)(void *), void *arg, int pin, int flags, void **cookiep);
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void mv_gpio_intr_mask(int pin);
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void mv_gpio_intr_unmask(int pin);
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int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask);
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void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable);
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uint8_t mv_gpio_in(uint32_t pin);
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int platform_pmap_init(void);
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int soc_decode_win(void);
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void soc_id(uint32_t *dev, uint32_t *rev);
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void soc_identify(void);
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void soc_dump_decode_win(void);
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uint32_t soc_power_ctrl_get(uint32_t mask);
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int decode_win_overlap(int, int, const struct decode_win *);
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int win_cpu_can_remap(int);
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void decode_win_idma_dump(void);
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void decode_win_idma_setup(void);
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int decode_win_idma_valid(void);
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int ddr_is_active(int i);
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uint32_t ddr_base(int i);
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uint32_t ddr_size(int i);
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uint32_t ddr_attr(int i);
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uint32_t ddr_target(int i);
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uint32_t cpu_extra_feat(void);
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uint32_t get_tclk(void);
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uint32_t read_cpu_ctrl(uint32_t);
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void write_cpu_ctrl(uint32_t, uint32_t);
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enum mbus_device_ivars {
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MBUS_IVAR_BASE,
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};
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#define MBUS_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(mbus, var, MBUS, ivar, type)
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MBUS_ACCESSOR(base, BASE, u_long)
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#undef MBUS_ACCESSOR
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#endif /* _MVVAR_H_ */
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