317 lines
7.3 KiB
C
317 lines
7.3 KiB
C
/*
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* Copyright (c) 2017-2018 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _QLNX_IOCTL_H_
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#define _QLNX_IOCTL_H_
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#include <sys/ioccom.h>
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#define QLNX_MAX_HW_FUNCS 2
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/*
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* Read grcdump and grcdump size
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*/
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struct qlnx_grcdump {
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uint16_t pci_func;
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uint32_t grcdump_size[QLNX_MAX_HW_FUNCS];
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void *grcdump[QLNX_MAX_HW_FUNCS];
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uint32_t grcdump_dwords[QLNX_MAX_HW_FUNCS];
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};
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typedef struct qlnx_grcdump qlnx_grcdump_t;
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/*
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* Read idle_chk and idle_chk size
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*/
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struct qlnx_idle_chk {
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uint16_t pci_func;
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uint32_t idle_chk_size[QLNX_MAX_HW_FUNCS];
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void *idle_chk[QLNX_MAX_HW_FUNCS];
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uint32_t idle_chk_dwords[QLNX_MAX_HW_FUNCS];
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};
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typedef struct qlnx_idle_chk qlnx_idle_chk_t;
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/*
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* Retrive traces
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*/
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struct qlnx_trace {
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uint16_t pci_func;
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uint16_t cmd;
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#define QLNX_MCP_TRACE 0x01
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#define QLNX_REG_FIFO 0x02
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#define QLNX_IGU_FIFO 0x03
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#define QLNX_PROTECTION_OVERRIDE 0x04
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#define QLNX_FW_ASSERTS 0x05
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uint32_t size[QLNX_MAX_HW_FUNCS];
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void *buffer[QLNX_MAX_HW_FUNCS];
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uint32_t dwords[QLNX_MAX_HW_FUNCS];
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};
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typedef struct qlnx_trace qlnx_trace_t;
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/*
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* Read driver info
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*/
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#define QLNX_DRV_INFO_NAME_LENGTH 32
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#define QLNX_DRV_INFO_VERSION_LENGTH 32
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#define QLNX_DRV_INFO_MFW_VERSION_LENGTH 32
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#define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH 32
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#define QLNX_DRV_INFO_BUS_INFO_LENGTH 32
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struct qlnx_drvinfo {
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char drv_name[QLNX_DRV_INFO_NAME_LENGTH];
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char drv_version[QLNX_DRV_INFO_VERSION_LENGTH];
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char mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH];
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char stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH];
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uint32_t eeprom_dump_len; /* in bytes */
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uint32_t reg_dump_len; /* in bytes */
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char bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH];
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};
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typedef struct qlnx_drvinfo qlnx_drvinfo_t;
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/*
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* Read Device Setting
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*/
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struct qlnx_dev_setting {
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uint32_t supported; /* Features this interface supports */
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uint32_t advertising; /* Features this interface advertises */
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uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */
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uint32_t duplex; /* Duplex, half or full */
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uint32_t port; /* Which connector port */
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uint32_t phy_address; /* port number*/
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uint32_t autoneg; /* Enable or disable autonegotiation */
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};
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typedef struct qlnx_dev_setting qlnx_dev_setting_t;
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/*
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* Get Registers
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*/
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struct qlnx_get_regs {
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void *reg_buf;
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uint32_t reg_buf_len;
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};
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typedef struct qlnx_get_regs qlnx_get_regs_t;
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/*
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* Get/Set NVRAM
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*/
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struct qlnx_nvram {
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uint32_t cmd;
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#define QLNX_NVRAM_CMD_WRITE_NVRAM 0x01
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#define QLNX_NVRAM_CMD_READ_NVRAM 0x02
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#define QLNX_NVRAM_CMD_SET_SECURE_MODE 0x03
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#define QLNX_NVRAM_CMD_DEL_FILE 0x04
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#define QLNX_NVRAM_CMD_PUT_FILE_BEGIN 0x05
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#define QLNX_NVRAM_CMD_GET_NVRAM_RESP 0x06
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#define QLNX_NVRAM_CMD_PUT_FILE_DATA 0x07
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void *data;
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uint32_t offset;
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uint32_t data_len;
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uint32_t magic;
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};
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typedef struct qlnx_nvram qlnx_nvram_t;
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/*
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* Get/Set Device registers
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*/
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struct qlnx_reg_rd_wr {
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uint32_t cmd;
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#define QLNX_REG_READ_CMD 0x01
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#define QLNX_REG_WRITE_CMD 0x02
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uint32_t addr;
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uint32_t val;
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uint32_t access_type;
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#define QLNX_REG_ACCESS_DIRECT 0x01
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#define QLNX_REG_ACCESS_INDIRECT 0x02
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uint32_t hwfn_index;
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};
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typedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t;
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/*
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* Read/Write PCI Configuration
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*/
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struct qlnx_pcicfg_rd_wr {
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uint32_t cmd;
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#define QLNX_PCICFG_READ 0x01
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#define QLNX_PCICFG_WRITE 0x02
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uint32_t reg;
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uint32_t val;
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uint32_t width;
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};
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typedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t;
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/*
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* Read MAC address
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*/
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struct qlnx_perm_mac_addr {
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char addr[32];
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};
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typedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t;
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/*
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* Read STORM statistics registers
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*/
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struct qlnx_storm_stats {
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/* xstorm */
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uint32_t xstorm_active_cycles;
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uint32_t xstorm_stall_cycles;
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uint32_t xstorm_sleeping_cycles;
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uint32_t xstorm_inactive_cycles;
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/* ystorm */
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uint32_t ystorm_active_cycles;
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uint32_t ystorm_stall_cycles;
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uint32_t ystorm_sleeping_cycles;
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uint32_t ystorm_inactive_cycles;
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/* pstorm */
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uint32_t pstorm_active_cycles;
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uint32_t pstorm_stall_cycles;
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uint32_t pstorm_sleeping_cycles;
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uint32_t pstorm_inactive_cycles;
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/* tstorm */
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uint32_t tstorm_active_cycles;
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uint32_t tstorm_stall_cycles;
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uint32_t tstorm_sleeping_cycles;
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uint32_t tstorm_inactive_cycles;
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/* mstorm */
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uint32_t mstorm_active_cycles;
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uint32_t mstorm_stall_cycles;
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uint32_t mstorm_sleeping_cycles;
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uint32_t mstorm_inactive_cycles;
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/* ustorm */
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uint32_t ustorm_active_cycles;
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uint32_t ustorm_stall_cycles;
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uint32_t ustorm_sleeping_cycles;
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uint32_t ustorm_inactive_cycles;
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};
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typedef struct qlnx_storm_stats qlnx_storm_stats_t;
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#define QLNX_STORM_STATS_SAMPLES_PER_HWFN (10000)
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#define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \
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QLNX_STORM_STATS_SAMPLES_PER_HWFN)
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struct qlnx_storm_stats_dump {
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int num_hwfns;
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int num_samples;
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void *buffer[QLNX_MAX_HW_FUNCS];
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};
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typedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t;
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/*
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* Read grcdump size
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*/
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#define QLNX_GRC_DUMP_SIZE _IOWR('q', 1, qlnx_grcdump_t)
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/*
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* Read grcdump
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*/
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#define QLNX_GRC_DUMP _IOWR('q', 2, qlnx_grcdump_t)
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/*
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* Read idle_chk size
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*/
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#define QLNX_IDLE_CHK_SIZE _IOWR('q', 3, qlnx_idle_chk_t)
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/*
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* Read idle_chk
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*/
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#define QLNX_IDLE_CHK _IOWR('q', 4, qlnx_idle_chk_t)
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/*
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* Read driver info
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*/
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#define QLNX_DRV_INFO _IOWR('q', 5, qlnx_drvinfo_t)
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/*
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* Read Device Setting
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*/
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#define QLNX_DEV_SETTING _IOR('q', 6, qlnx_dev_setting_t)
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/*
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* Get Registers
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*/
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#define QLNX_GET_REGS _IOR('q', 7, qlnx_get_regs_t)
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/*
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* Get/Set NVRAM
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*/
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#define QLNX_NVRAM _IOWR('q', 8, qlnx_nvram_t)
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/*
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* Get/Set Device registers
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*/
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#define QLNX_RD_WR_REG _IOWR('q', 9, qlnx_reg_rd_wr_t)
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/*
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* Read/Write PCI Configuration
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*/
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#define QLNX_RD_WR_PCICFG _IOWR('q', 10, qlnx_pcicfg_rd_wr_t)
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/*
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* Read MAC address
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*/
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#define QLNX_MAC_ADDR _IOWR('q', 11, qlnx_perm_mac_addr_t)
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/*
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* Read STORM statistics
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*/
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#define QLNX_STORM_STATS _IOWR('q', 12, qlnx_storm_stats_dump_t)
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/*
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* Read trace size
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*/
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#define QLNX_TRACE_SIZE _IOWR('q', 13, qlnx_trace_t)
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/*
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* Read trace
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*/
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#define QLNX_TRACE _IOWR('q', 14, qlnx_trace_t)
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#endif /* #ifndef _QLNX_IOCTL_H_ */
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