eb95689a82
The OpenCores I2C IP core can be found on any bus. Split out the PCI bus specifics into their own file, only compiled on systems with PCI. Reviewed by: kp Sponsored by: Axiado
107 lines
3.6 KiB
C
107 lines
3.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __OPENCORE_I2C_H__
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#define __OPENCORE_I2C_H__
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/* I2C specific registers */
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#define OC_I2C_PRESCALE_LO_REG 0x00
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#define OC_I2C_PRESCALE_HI_REG 0x01
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#define OC_I2C_CTRL_REG 0x02
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#define OC_I2C_TRANSMIT_REG 0x03 /* tx and rx - same reg */
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#define OC_I2C_RECV_REG 0x03 /* tx and rx - same reg */
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#define OC_I2C_DATA_REG 0x03 /* tx and rx - same reg */
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#define OC_I2C_CMD_REG 0x04 /* cmd and status - same reg */
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#define OC_I2C_STATUS_REG 0x04 /* cmd and status - same reg */
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#define XLP_I2C_CLKFREQ 133333333 /* XLP 133 MHz IO clock */
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#define XLP_I2C_FREQ 100000 /* default 100kHz */
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#define I2C_TIMEOUT 500000
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/*
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* These defines pertain to the OpenCores
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* I2C Master Host Controller used in XLP
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*/
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#define OC_PRESCALER_LO 0
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#define OC_PRESCALER_HI 1
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#define OC_CONTROL 2
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#define OC_CONTROL_EN 0x80
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#define OC_CONTROL_IEN 0x40
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#define OC_DATA 3 /* Data TX & RX Reg */
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#define OC_COMMAND 4
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#define OC_COMMAND_START 0x90
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#define OC_COMMAND_STOP 0x40
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#define OC_COMMAND_READ 0x20
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#define OC_COMMAND_WRITE 0x10
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#define OC_COMMAND_RDACK 0x20
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#define OC_COMMAND_RDNACK 0x28
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#define OC_COMMAND_IACK 0x01 /* Not used */
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#define OC_STATUS 4 /* Same as 'command' */
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#define OC_STATUS_NACK 0x80 /* Did not get an ACK */
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#define OC_STATUS_BUSY 0x40
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#define OC_STATUS_AL 0x20 /* Arbitration Lost */
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#define OC_STATUS_TIP 0x02 /* Transfer in Progress */
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#define OC_STATUS_IF 0x01 /* Intr. Pending Flag */
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struct iicoc_softc {
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device_t dev; /* Self */
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u_int reg_shift; /* Chip specific */
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u_int clockfreq;
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u_int i2cfreq;
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struct resource *mem_res; /* Memory resource */
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int mem_rid;
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int sc_started;
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uint8_t i2cdev_addr;
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device_t iicbus;
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struct mtx sc_mtx;
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};
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#endif
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extern devclass_t iicoc_devclass;
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int iicoc_iicbus_start(device_t dev, u_char slave, int timeout);
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int iicoc_iicbus_stop(device_t dev);
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int iicoc_iicbus_read(device_t dev, char *buf, int len, int *read, int last,
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int delay);
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int iicoc_iicbus_write(device_t dev, const char *buf, int len, int *sent,
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int timeout);
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int iicoc_iicbus_repeated_start(device_t dev, u_char slave, int timeout);
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int iicoc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr);
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int iicoc_init(device_t dev);
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